TW474011B - Manufacturing method of trench-type flash memory - Google Patents

Abstract

A manufacturing method of trench-type flash memory is provided, which comprises first forming plural shallow trench isolations in a silicon substrate and at least isolating one active region; then forming a doped area and an insulated layer on the substrate; second, proceeding a first photo-etch process to make two trenches at the active region and sequentially forming channel oxide layer, floating gate and ONO dielectric layer on the sidewall of each trench; third forming a doped polysilicon layer to fill in the trench and etching out a part of doped polysilicon to make two control gates on the active region; finally forming a self-aligned common source between the two control gates and plural spacers on the sidewalls of each control gate; then forming metal silicide on the surfaces of control gates and common source.

Description

474011 V. Description of the invention (1) Field of the invention The present invention provides a method for manufacturing trenched flash memory cell, especially a method that can improve the coupling ratio (CR) of the capacitor to improve Method for manufacturing trench-type flash memory unit with electrical performance of components. Background note. A stacked gate flash memory cell (stacked-gatef 1 ash memory ce 1 1) includes a floating gate for storing charge, and an ONO (〇xide-nitride-oxide) structure. A dielectric layer and a control 1 ing gate for controlling data access. The memory can use a similar capacitor principle to store the induced charge in the stacked gates so that the memory stores the signal "1". If the data in the memory needs to be replaced, only a little extra energy is needed to neutralize the electricity stored in the stacked gates, and the data storage can be resumed. Please refer to FIG. 1. FIG. 1 is a schematic diagram of a cross-sectional structure of a conventional flash memory unit 10. As shown in FIG. 1, the conventional flash memory unit 10 includes a stacked gate 14 disposed on a silicon substrate 12 surface, and a source 2 4 and a drain 2 6 disposed on the stacked gate 1 4. On both sides of the silicon substrate 12. The stacked gates 1 and 4 consist of a tunnel oxide layer 16, a floating gate 18, a

474011 V. Description of the Invention (2) The ONO dielectric layer 20 and a control gate electrode 22 are sequentially stacked from bottom to top. Utilizing the channel hot electrons (CHE) effect, the hot electrons generated near; and the electrode 26 can pass through the channel oxide layer 6 and shoot into the floating gate 1 8 ′ to achieve the purpose of storing data. When erasing, the control gate 2 2 is grounded or connected to a negative voltage using F 乐 w 1 er N rdheimtu η ne 1 ing technology, and The drain electrode 26 is set to a high voltage state so that the electrons stored in the floating gate electrode 18 are emitted. · In general, the performance of flash memory early yuan 10 can use a stolen value (CR) as an indicator, assuming that the capacitance between floating gate 18 and control gate 22 is C i, floating gate The capacitance between 18 and the source 24 is C 2, the capacitance between the floating gate 1 8 and the surface of the silicon substrate 12 is C 3, and the capacitance between the floating gate 18 and the drain 26 is Is C 4, the combined value of flash memory unit 10 can be defined as: CR 20! / (〇! + C2 + C3 + C4) where a higher CR value indicates that the flash memory is writing. Or, the lower the operating voltage required for the erasing operation, the better the performance. From the above relationship, it can be seen that the method of increasing the CR value can increase C or decrease C 2, C #, and C 4. Since the size of the capacitor is directly proportional to the area of the capacitor, increasing the combined area between the floating gate 18 and the control gate 2 2 can effectively increase c 1. However, due to the requirement of component accumulation, the line width (1 inewidth) of the floating gate 18 and the control gate 22 is limited, so it is impossible to increase the capacitance by increasing the area of the two and cause the memory. The access speed of unit 10 cannot be further improved. In addition,

474011 V. Description of the invention (3) Although this stacked gate flash memory unit 10 occupies less area, it has the disadvantage of over erase, and it is very easy to cause errors or failure to write when writing data. Into. SUMMARY OF THE INVENTION The object of the present invention is to provide a method for fabricating a trench type flash memory cell, so as to effectively increase the capacitance value and improve the electrical performance of the device. In a preferred embodiment of the present invention, a plurality of shallow trench isolations are first formed in a silicon substrate and at least one active region is isolated. Next, a first ion implantation process is performed on the silicon substrate to form a doped region, and then an insulating layer is formed on the surface of the silicon substrate. A first yellow light and etching process is then performed to form two trenches in the active area. A channel oxide layer, a floating gate electrode, and a 0N0 dielectric layer are sequentially formed on the inner wall surface of each trench. Then, a doped polycrystalline silicon layer is formed on the surface of the silicon substrate to fill each of the trenches, and a doped polycrystalline silicon layer is etched in the second yellow light and etching process to form two control gates on the active region. Then, a self-aligned source etching process is performed to form a common source between the two control gates, and a plurality of sidewalls are formed around each control gate. Finally, a self-aligned silicide process is performed to form a metal silicide on the surface of each control gate and the common source, and the manufacturing of the trench type flash memory unit of the present invention is completed.

474011 V. Description of the invention (4) Because the invention and the invention form a stacked gate, the ΐ2 trench flash memory between the trench structure of the silicon substrate and the control electrode is buried. The increase in the depth and width of the floating gate of the unit ^ ΐ can be increased with the stacked gate embedded in the silicon substrate formed on the surface of the Shixi substrate ... This will not affect the subsequent two or two sets of flash memory cells The detailed description of the invention can be improved while referring to FIG. 2 ′. FIG. 2 is a schematic cross-sectional structure diagram of a trench flash memory unit 30 fabricated on the surface of a silicon substrate 32 according to the present invention. As shown in Figure 2, the Shixi substrate 3 2 is a Shixi covered insulation (3 丨 1 丨 〇〇11_〇11_ 丨 1131113 < |: 〇] :, SOI) substrate or a single crystal silicon (singie crystal silicon ) Substrate, and a memory array area and a peripheral circuits region are defined in advance on the surface thereof, and at least one P-type well 34 is formed in the Shixi substrate 32 of the memory array area. And an N-well. In a preferred embodiment of the present invention, the trench flash memory unit 30 includes two stacked gates 42 buried in a P-type well 34 on the surface of a silicon substrate 32, and a common source 36 is provided. On the surface of the silicon substrate 3 2 between the two stacked gates 42, two drain electrodes 38 are provided on the surface of the silicon substrate 32 on the other side of the stacked gate 4 2, and a dielectric layer 40 is provided on the common source. 3 6 and the surface of the drain electrode 3 8 serve as the separation between the stacked gate 4 2 and the common source electrode 3 6 and the drain electrode 3 8.

474011 V. Description of the invention (5) Delamination. Among them, the stacked gate 42 is composed of a channel oxide layer 4 4 ′, a floating interlayer 46, a 100N dielectric layer 48, and a control gate 50 sequentially stacked from bottom to top and partially buried in the silicon substrate 32. . In addition, the trench-type flash memory unit 30 further includes a sidewall 52 structured on each of the stacked gates 42 ^ and two sidewall surfaces, and a metal silicide layer 54 is disposed on each of the stacked gates 4 2 and a common source. To reduce the resistance of the electrode. Please refer to FIG. 3. FIG. 3 is a top view of the structure of the trench-type, flash memory unit 30 in FIG. As shown in FIG. 3, the silicon substrate 32 uses a plurality of shallow trench isolations 5 6 as isolations to form two active regions 5 8. A plurality of trenches 61 are provided in the active area 58, which are buried in the broken base 32 and are perpendicular to the parallel zigzag lines 60, and a gap is formed between the two zigzag lines 60. The line 62 ° is shown in FIG. 4 to FIG. 11. FIG. 4 to FIG. 11 are schematic diagrams of a method for fabricating a trench type flash memory unit 3 0 in the Shixi substrate 32 according to the present invention. FIG. 4 is a cross-sectional view taken along the line AA and tangent in FIG. 3. The method of the present invention first performs a shallow trench isolation (STI) process on the surface of the silicon substrate 32, that is, a conventional photolithography is used. ) And #lithography processes form a plurality of shallow trench isolations 5 6 in the silicon substrate 32, and use the shallow trench isolations 5 6 to isolate an active region 5 8 on the surface of the silicon substrate 3 2. Then, a chemical vapor deposition (CVD) process is performed to form an oxide layer 6 4 to fill each shallow trench isolation 56. A photoresist layer (not shown) is then formed to cover the peripheral circuit area and the N-type well in the memory array area.

Page 8 474011 V. Description of the invention (6) region and the first ion implantation process is performed in the active region 58 on the surface of the P-type well 34 to form a buried N + doped region 35. Then, an insulating layer 40 is formed on the surface of the silicon substrate 32. The insulating layer 40 may be a silicon dioxide layer formed by a plasma-enhanced chemical vapor deposition (PECVD) method.

FIG. 5 is a cross-sectional view taken along the BB ′ tangent line in FIG. 3, and then a photoresist layer 6 6 is formed on the surface of the insulating layer 40, and a yellow light process is performed to pattern the photoresist layer 6 6. A position where the trench 61 is to be formed is defined. As shown in FIG. 6, a photoresist layer 66 is used as a mask to perform a etch process to remove the insulating layer 40 to a predetermined depth of the P-type well 34 to form a second trench in the P-type well 34. 61 'and a ditch 61 separates the replacement area 3 5 into a common source 36, located between the two ditch 61, and two drains 38, respectively, on the other side of the second ditch 61 . Then a thermal oxidation method is performed to form a silicon dioxide layer on the inner wall surface of the trench 61 as a channel oxide layer 44 °

Then, as shown in FIG. 7, a doped polycrystalline silicon layer (not shown) is formed on the surface of the silicon substrate 32 by a CVD process. In order to avoid filling the trench 6 1, the doped polycrystalline silicon layer is deposited to a thickness of about the thickness of the trench 6 1. One-half to three-quarters of the length of the radius. Subsequently, the doped polycrystalline silicon layer deposited in the area outside the trench 61 is removed so that the doped polycrystalline silicon layer remaining in the trench 61 becomes a floating gate 46.

Page 9 Wucheng 48, the description of the invention as shown in (7) 8 memory array (do PEP after doping), etch 'control gate 60, and control the gate with a yellow light as shown in Figure 9 After that, a piece of crystals with yellow light and engraved part of the pole was 50, and it was around the week. Next, the process is performed between 50 ′ and then a 100N dielectric layer CVD process is formed on the surface of the silicon substrate 32 in the oxidation / nitriding / oxidation (NONO) process zone to deposit another 4 9 on the entire surface of the silicon substrate 32. The doped polycrystalline silicon layer 49 fills the trench 6 丨. Photo and etching process (doped polysilicon layer 49) is formed over trench 6 i.e. a plurality of gates are formed on the two-word line-edge circuit area across active area 58 in FIG. 3 ( (Not shown), if a photoresist layer 68 is formed on the surface of the silicon substrate 32, and an opening is formed on the photoresist layer 68 to expose the insulating layer 40 located at the second. As shown in FIG. The patterned photoresist layer 68 is used as the cover 2 and 5 rows of alignment source #etching process (Self_alignment souae SAS) to remove the insulating layer 40 between the two control gates 50 until the common source face is removed. The insulating layer 40 is removed The last name engraving process can be used—including gasification = (fluorocarbon plasma) for selective etching of silicon dioxide (insulating layer 40) and galvanite (shared source 36), must / 杂 夕 硅 度 # The overly etched part of the common source 36 can completely pass through the insulating layer 40 between the interrogation electrodes 50, and expose the common source 36 / This control is shown in Figure 3 'each common source In the shallow trench isolation 56 between the poles 36, the dibu 'will also be etched to the surface of the silicon substrate 32 in the selective surname engraving. After that, the photoresist layer 68 is used as a mask to perform a second ion distribution value again.

474011 V. Description of the invention (8) The process uses a dopant such as erbium atoms to heavily dope the common source 3 _ — to adjust its dopant concentration and complete the stacking of the gate 4 2 to remove the photoresist layer 68, and after sinking nitrogen on the surface of Shixi substrate 32 ^), an anisotropic dry etch is used to etch back and forth the part of the stomach (= the visible layer, so that the remaining silicon ions on the two stacked gates 42) Side wall member 52. The silicon nitride layer on the straight side wall of the 4Z is formed as shown in Figure 11. Finally, it is coated on a silicon-based cobalt, nickel or tungsten metal layer (not shown), and a titanium layer is formed. , And the control gate 50 and the common source electrode 36, and so on ... place 1 so that the metal layer i-m, the occupant rents this, and the stone layer on the surface of the electrode 36 reacts to form a free Ϊ aHgnment SH1Clde, which becomes ^ resistance), and each share 22 resistances (sheet one phase connected metal stone material (/ alicide) process to form the open trench Zhu type flash memory unit 30 manufacturing. Any or this hair is used because of the present invention A gully is formed in one pass. At the same time, the position of G $ 61 is ★ and the source 36 for etching is used. At this time, the active area test f = 61 forms a region of self-aligned common source 36 between itself; 自行 forms a stack gate 42 and a common process to define the source drain 36, ', so no additional yellow light flash memory unit 30 is needed The source f, because of the periphery of the trench gate 46 of the present invention, makes the floating & / J 38 series horizontally surround the communication between the floating gate 4 6 and the source 3 6 / drain 38.

474011 V. Description of the invention (9) Channel length 1 plus' Therefore, the trench type flash memory unit 3 of the present invention uses the Fowler Nordheim tunnel for storing or erasing data. ing) technology to perform electron injection or neutralization on the floating gate 46. For example, applying a high voltage to the control gate 50 and setting the sum pole 38 and the source 36 to a negative biased state and a floating state, respectively, can make the drain 38 The electrons can be stored in the floating gate 46; otherwise, the control gate 50 is grounded or connected to a negative voltage, and the source 36 and the drain 38 are set to a high voltage state and a floating state, respectively. , The electrons stored in the floating gate 46 can be emitted. Compared with the conventional method for making a flash memory cell, the method of the present invention uses a trench structure embedded in a silicon substrate to form a stacked gate. Therefore, the floating gate and the control gate of the trench flash memory cell are formed. The occlusion area between the electrodes can be effectively improved as the depth and width of the stacked gate embedded in the silicon substrate are increased, and this will not cause a reduction in the degree of accumulation of the subsequent components formed on the silicon substrate surface. Can improve the access speed of the entire flash memory unit. In addition, the present invention uses a self-alignment method to form a common source and an electrode, so that the process of forming the source drain after the gate is formed can be avoided from damaging other components, and the invention also uses The metal oxide layer on the surface of the gate electrode and the source electrode reduces the resistance, so the electrical performance and quality reliability of the flash memory cell can be improved. The above are only the preferred embodiments of the present invention.

Page 12 474011

Page 13 474011 Brief description of diagrams Brief description of diagrams Figure 1 is a schematic cross-sectional structure diagram of a conventional flash memory unit. FIG. 2 is a schematic cross-sectional view of a trench type flash memory unit according to the present invention. FIG. 3 is a top view of the structure of the trench type flash memory unit in FIG. 2. FIG. 4 to FIG. 11 are schematic diagrams of a method for manufacturing a trench type flash memory unit according to the present invention. Explanation of Symbols in the Figure 10 Flash Memory Mouth —- Early 12 Silicon substrate 14 Stacked gate 16 Channel oxide layer 18 Floating gate 20 0 N 0 Dielectric layer 22 Control gate 24 Source 26 Drain 30 Flash memory X3XJ — early 32 substrate 34 P-type well 35 doped region 36 common source 38 drain 40 insulating layer 42 stacked gate 44 channel oxide layer 46 floating gate 48 0 N 0 dielectric layer 49 doped Polycrystalline silicon layer 50 Control gate 52 Side wall 54 Metal silicide layer 56 Shallow trench isolation 58 Active area

474011

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Claims (1)

474011 6. Application patent scope 1. Kind of trench-type flashing method § Trenched f 1 ashmem 〇ry ce 1 1) manufacturing method, the manufacturing method includes the following steps: a silicon substrate ), And a memory array area and a peripheral circuits region have been defined on the surface of the Shi Xi substrate; a shallow trench isolation (STI) process is performed on the silicon substrate Forming a plurality of shallow trench isolations, and forming at least one active area separated and separated by each of the shallow trench isolations on the surface of the silicon substrate; performing a first ion implantation process on the silicon substrate on the memory array region, Forming a doped region; forming an insulating layer on the surface of the Shi Xi substrate; performing a first yellow light and etching process (PEP), etching the insulating layer and the silicon substrate to form two layers in the active region; A trench; a tunnel ox i de layer is sequentially formed on the inner wall surface of each trench and the floating of the trench flash memory cell A floating gate; forming a dielectric layer on the surface of each of the floating gates; forming a doped polysilicon 'on the surface of the silicon substrate and filling each of the trenches; performing a second yellow light In the etching process, the doped polycrystalline silicon layer is etched to form two control gates (c ο ntr ο 1 1 inggate) on the far active area, and a plurality of gates are formed on the peripheral circuit area; Perform a self-alignment source (SAS) Page 16474011 VI. Patent application range etching process, the part of the insulating layer between the two control gates is etched to the surface of the doped region, so that the doped region between the two control gates forms a common source Common source; forming a plurality of spacers around each of the control gates; and performing a self-alignment silicide (sa 1 ici de) process for each of the control gates And a surface of the common source electrode form a metal lithoate;. The doped region where the two control gates and the common source are not formed in each of the active regions is the drain of the trench flash memory cell. 2. The method according to item 1 of the patent application scope, wherein the silicon substrate is a silicon substrate (si 1 ic ο η-ο η-insu 1 at 〇r, S 0 I) substrate or a single crystal substrate . 3. The method of claim 1, wherein the surface of the Shi Xi substrate in the memory array region further includes a P-well. 4. The method of claim 3, wherein the doped region is a buried N + doped region. 5. The method according to item 1 of the patent application, wherein the dielectric layer is a 0N0 (oxidized-silicon nitride-silicon oxide) dielectric Page 17 474011 Sixth, the scope of patent application ^ ^-layer. 6. Please refer to the special method of the "Janfan" ® $ 1 method, wherein the floating gate is composed of doped poly si 1 icon. 7. If the method of applying for the scope of the first item of the patent is ′, after the self-aligning source (SAS) surname engraving process is completed, a second ion implantation process must be performed using the SAS mask. 8. The method according to item 1 of the scope of patent application, wherein the trench-type flash memory ΐ ΐ writer and erase operations are all profitable "": Tunneling (Fowier Nordheim tunneling) effect to complete the re] 1) wood-manufactured, flash § memory unit (trenched flash memory provided-stone method 'the manufacturing method includes the following steps: the area and a tone i substrate' and the stone evening substrate A memory array has been defined on the surface for the = side circuit area; several shallow trench isolations (ST 1) processes are used to form multiple isolation barriers in the silicon substrate and 5 and multiple substrates are formed on the surface of the stone substrate. Each of the shallow trenches corresponds to the active area arranged by the array of Buu Gu; the process is to form a first ion implantation of the Shi Xi base on α ° on the silicon-based region; Insulation; Page 18 474011 6. The edge layer of the patent application is adjacent to the trench in the trench. Into the silicon layer, the array area has the control region of the floating element above, and the surface is etched. Each of the common silicon substrates is subjected to a first yellow light and etching process (PEP), and the insulating substrate is etched to form two phases and the silicon channel in each of the active regions; An inner wall surface of the silicon-based channel is sequentially formed with a channel oxide layer and a floating gate of the memory cell; a dielectric layer is formed on the surface of the gate; a doped polycrystalline silicon layer is formed on the bottom surface and fills each The trench performs a second yellow light and etching process, and the doped polycrystals in the etched portion form a plurality of gates on the peripheral circuit region, and a plurality of word lines (w ow 1 ine) are formed on the memory. ), And each of the word lines that are not adjacent to each other in the active area crosses, and each word line crosses a portion above each gate to relatively constitute the trench flash memory single gate; A self-aligned source (SAS) etching process, Engraving the insulating layer between each of the two active control gates until the doped region table causes the doped region between the two control gates to form a common source, and each of the shallow ones between the common sources Trench isolation until a plurality of sidewalls are formed around each of the word lines on the silicon substrate table; and a self-aligned salicide process is performed to form a metal silicide on the control plane and to each of the common sources The electrode surface and the surface of the silicon substrate between the source electrodes form a plurality of connected metals to form a bit line (bit 1 ine); Page 19 474011 VI. Scope of patent application The doped region where the two control gates and the common source are not formed in each of the active regions is the drain of the trench flash memory cell. 10. The method according to item 9 of the scope of patent application, wherein the silicon substrate is a silicon-on-insulator (SO I) substrate or a single-crystal silicon substrate. 1 1. The method according to item 9 of the scope of patent application, wherein the surface of the Shi Xi substrate in the memory array region further includes a P-well. 12. The method according to item 9 of the scope of patent application, wherein the doped region is a buried N + doped region. 13. The method according to item 9 of the scope of patent application, wherein the dielectric layer is a 0 N 0 dielectric layer. 14. The method according to item 9 of the scope of patent application, wherein the control gate is composed of doped polycrystalline silicon. 1 5. The method according to item 9 of the patent application scope, wherein after the self-aligning source (SAS) etching process is completed, a second ion implantation process must be performed using the SAS mask. 16. The method according to item 9 of the scope of patent application, wherein the trench type flash memory Page 474 011 Page 21