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A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（） 5-1發明領域 本發明係有關於一種使用於雙埠（d u a卜p 〇「t)靜態隨 機存取記憶體（static random access memo「y: SRAM) 的高準確性（high accuracy)自動計時（self-timing)電路 中所使用的餘置記憶胞（d u m m y c e Μ )，特別是有關於一種 運作於高速且低耗能的雙埠靜態隨機存取記憶體的高準 確性自動計時電路中所使用的餘置記憶胞。 5-2發明背景 在傳統的S RAM中，每一個記憶胞都通過一位元線 施以一電壓，使其經由閘極控制耦合電晶體，作為一個驅 動電晶體的負載。位元線上的電壓，係由負載電晶體的通 路電阻，對於耦合電晶體及記憶胞的其中一個驅動電晶體 結合起來的通路電阻之比值所決定。因為這些電晶體之電 晶體之操作特性會隨著製造及溫度變化所導致的原件差 異而改變，而設計記憶體時，必須將這些差異性，在其安 全邊限中納入這些因素，並且因此之記憶體的運作表現並 不會到達最大的極限。 特別是在設計現代的嵌入式（e m b e d d e d)靜態隨機 存取記憶體（Static Random Access Memory: SRAM)時， 因為高速元件的趨勢，自動計時（self-timing)電路或者是 閂鎖式（丨a t c h t y p e)放大器，越來越廣泛運用於加快存取 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公餐） -----I ---- - - I ----- I I I ----II--- (請先閱讀背面之注意事項再填寫本頁) 472255 經濟部智慧財產局員工消費合作社印製 A7 _B7_ 五、發明說明（） 時間（a c c e s s t i m e)及週期。然而當製程尺寸縮小，並且 當記憶體位元線的寬度變窄時，自動計時的正確性會變得 越來越差。甚至當一些製程條件些微變化時，也會導致自 動計時無法容忍的誤差，自動計時的不正確性可大部分歸 因於位元線的活動。 在一傳統的計時電路内，在追蹤位元線的狀態時， 只模擬其上的電壓。雖然在一些較先進的設計中，也會去 模擬位元線的電阻，但是用於驅動餘置（d u m m y b i t丨i n e) 位元線的電流源，並不如真正記憶胞中的電流源一般之準 確，換句話說，餘置位元線上的電壓變化不會與真正記憶 胞令的位元線上的電壓變化一致。所以在大部分的自動計 時電路設計中，對於位元線負載以及存取活動的模擬都是 加以忽略的。 因為製程的縮小，現今多使用窄線寬的元件，而在 中尺寸元件及窄尺寸元件之間，電性的差別因此便得更為 明顯。此外，為了在一邏輯處理器中使用嵌入式記憶體， 由晶圓廠所提供的邏輯S P I C E模組，特別是當用了其他 外加的製程以製造遷入式記憶胞時，通常無法極正確的反 映出記憶胞的活動。因此用了較不正確的電流源之後，通 常會使得計時的不準確性較以前提高。 為了要顯示在嵌入式記憶胞中使用餘置位元線的 自動計時電路，其控制電路之結構及餘置記憶胞之圖樣顯 示在圖一 A中，舉例而言，圖一 A控制電路可以是字元 線脈波產生器1 〇，並且字元線脈波是由字元線脈波產生 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公t ) ---------------------訂-------- (請先閱讀背面之注意事項再填寫本頁) 472255 經濟部智慧財產局員工消費合作社印 Α7 Β7 五、發明說明（） 器1 0的dmy_wl端所傳输到反相器Ή，然後反相器1 1 對由Ν個餘置半記憶胞預充電（p「e - c h a「g e )。位元線1 3 被連.接到反相器1 1的輸出，並且位元線1 3被連接到由 作為反相器1 1的負載的複數個記憶胞所組成的餘置記憶 胞陣列1 5。複數個記憶胞中的每一個記憶胞如記憶胞1 7 所示，記憶胞1 7是一種雙埠（dua卜port)記憶胞，其電路 圖顯示於圖二申，其中字元線VVL1以及字元線WL2，分 別笨連接到電晶體N4、N5以及N6、N7的閘極，電晶體 N 4以及N 6的源極被輕合到.點DATA，而前者的；；及極分別 被耦合到位元線B L以及B L 2。相似的，電晶體N 5及N 7 的源極被電性耦合到點ZDATA，並且前者的汲極分別被 電性麵合到反相位元線Z B L以及Z B L 2。電晶體p 〇的閘 極經由點N〇D E 1被電性耦合到電晶體N 2的閘極。另外， 電晶體P0的汲極在點DATA處被電性耦合到電晶體N2 的汲極。電晶體P 0的源極被電性耦合到電壓V D D，並且 電晶體N 2的源極被電性搞合到V s s，電晶體p 1的閘極 經由點N0DE2被電性耦合到電晶體N3的閘極，此外， 電晶體P 1的汲_極在點Z D A T A處’被電性麵合到電晶體 N 4的及極。電晶體P 1的源極被電性稱合到電壓v d d，並 且電晶體N 3的源極被電性耦合到電壓v s s。此外，電線 WIRE1電性搞合點.DATA與點N0DE2，並且電線N0DE2 電性耦合點ZD ΑΤΑ與點NODE 1。 在習知的餘置記憶胞陣列的另外—個例子中，反相 器1 1可以被電晶體（例如N Μ 0 S )所取代，而且耗合到控 本紙張尺度適用中國國家標準（CNS)A4燒格（210 X 297公t ) ---------------------訂·-------~ (請先閱讀背面之注音？事項再填寫本頁) 4 2255 . A7 _B7 五、發明說明（） 制電路的記憶胞陣列之電路圖顯示在圖一 B中。為了要 達成高速元件之目的，必須將時間邊限降低到最小值。所 以最好可以追蹤普通記憶胞中位元線上的電壓，以盡量降 低所需的時間邊限。然而不論使用任何一種習知的餘置記 憶胞陣列，餘置位元線上的電壓因為下列的原因而無法準 確的追蹤一般記憶胞的位元線上之電壓。首先，習知技術 的餘置記憶胞之電流源是一個反相器或一記憶體，並且在 習知技術的記憶胞所使用的電流源之閘極寬度以及閘極 長度和其佈局（丨a y 〇 u t )，與一般記憶胞者不同，所以其放 電電流與餘置記憶胞中的餘置位元線上之放電電流不 同。其次，在製造反相器N Μ〇S的製程條件與用以製造 一般記憶胞之製程條件不同。 另外，在設計記憶體時，相關於餘置位元線的圖樣 (p a 11 e「η )及負載並未考慮到最壞的狀況。因此當耦合到 位元線的複數個負載記憶胞皆為邏輯” 1 ”或為高電壓準 位，並且W L1與W L 2皆被存取時，餘置位元線上的電壓 就無法準確地追蹤一般記憶胞的位元線上的電壓。特別是 在高密度元件的趨勢下，記憶胞的數目會持續增加，負載 電容之差異就會嚴重影響追蹤一般記憶胞之位元線之電 壓的準確性。因為上述原因，所以必須要改進餘置記憶胞 以達成高速元件的目的。 5-3發明目的及概述 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公t ) i n 11— 1^1 ί i 111 m ^^1 n I 1 n 1 1^1 i 1 m 一。，> l m n n n ^^1 an λ (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 4 2255 A7 _B7 五、發明說明（） 為了要在高速運作的情形下，準確的模擬一般記憶 胞區域中的位元線上之活動（例如電壓變化），本發明提出 一種餘置記憶胞的餘置位元線，其可以用來追蹤雙埠靜態 隨機存取記憶體上的位元線之電壓變化。上述的餘置記憶 體包含複數個字元線、兩對位元線（其一作為餘置位元 線，另一作為連接之用）、兩對負載電路以及一列記憶胞。 上述的字元線被用來接收一存取訊號，而兩對負載 電路係用以分別連接到上述的兩對位元線，藉以在預充電 (p「e-cha「ge)週期中，對餘置位元線預充電。在上述存取 訊號抵達耦合到一般位元線的一般記憶胞時，被耦合到記 憶胞陣列之兩對位元線上的電壓會追蹤一般位元線上之 電壓。一般位元線被電性耦合到電壓源，並且每一個記憶 胞陣列中的記憶胞之元件具有連接到字元線的控制端，以 及一對反向並聯（anti-pa「all el)的反相器，每一個耦合電 晶體相應於存取訊號，在兩對字元線中的其中一個與兩個 反向器中的其中一個建立導通路徑，以使得上述的那對反 相器二位元狀態中的其中一種狀態。此對反相器中的其中 一個反相器之閘極係被耦合至電壓源，而此對反相器中的 另一個反相器之閘極係被耦合至一源極電壓準位，此兩對 耦合電晶體中的其中一個電晶體之第一控制端係被電性 耦合至此兩對耦合電晶體中的另一個電晶體之第二控制 端。 上述之記憶體可以是一種雙埠（d u a卜ρ 〇 r t)靜態隨機 存取記憶體（Static Random Access Memory: SRAM)， 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公f ) 1 I - ---i I I---^4· 1 1---- -—訂---------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印*''< 472255 經濟部智慧財產局員工消費合作社印ϋ衣 A7 _B7 五、發明說明（） 而其中的兩對負載電路至少包含第一場效電晶體（Field Effect Transistor ·· FET) '第二場效電晶體、第三場效電 晶體以及第四場效電晶體，其中每一個場效電晶體在上述 電壓源及陣列記憶胞之間具有源極-汲極導通路徑，並且 第一場效電晶體之閘極被電性耦合到第二場效電晶體、第 二場效電晶體及第四場效電晶體之閘極。 而上述的陣列記憶胞中更包含第一群記憶胞以及 第二群記憶胞。第一群記憶胞係用於提供電流，此第一群 記憶胞係作為記憶胞陣列中的驅動器，第二群記憶胞係用 於由第一群記憶胞接收電流，上述的第二群記憶胞係作為 此列記憶胞中的負載。第一群餘置記憶胞中的每一個具有 第一反相器，此第一反相器被設定為二位元狀態中的第一 狀態，並且被電性轉合到兩對位元線中的第一位元線。而 第一群記憶胞中的每一個具有第一字元線，此第一群記憶 胞中，每一個所具有之第一字元線被電性耦合，以接收上 述的存取訊號。 第二群記憶胞中的每一個具有第二反相器，並且第 二反相器被設定為二位元狀態中的第二狀態，每一個第二 反相器係被電性耦合到此對位元線中的此第一位元線，上 述的第二群記憶胞中的每一個記憶胞具有第二字元線，第 二群記憶胞中的第二字元線被電性耦合到上述的源極電 壓準位。 為了獲得可以用來精確追蹤一般位元線上的電壓 之變化，將一觸發裝置電性耦合到上述的第一位元線，並 本紙張尺度適用中國國家標準（CNS)A-l規格（210 X 297公t ) i - I III—— — — — — — -— — — ill— « I i I I I I I I (請先閱讀背面之注意事項再填寫本頁) 472255 經濟部智慧財產局員工消費合作社印製 Δ7 B7_ 五、發明說明（） 且觸發裝置的輸出被電性耦合到產生存取訊號的控制電 路。在本發明的較佳實施例中之觸發裝置可以是施密特觸 發器（Schmitt trigger)或是反相器。 5-4圖式簡單說明 將後續的說明配合下列圖式，將可以對於本發明的 特徵有更為清楚之了解，其中·· 圖一 A所顯示的是使用反相器作為電流源的傳統餘 置記憶胞陣列； 圖一 B所顯示的是使用 N型金氧半場效電晶體 (N Μ 0 S )作為電流源的傳統餘置記憶胞陣列； 圖二顯示的是傳統記憶胞之電路圖； 圖三顯示的是依據本發明的一較佳實施例中，使用 於餘置記憶胞陣列中的記憶胞之電路圖； 圖四Α顯示的是當記憶胞的一個埠在”讀取”狀態時 的等效電路圖； 圖四B顯示的是當記憶胞的兩個埠都在”讀取”狀態 時的等效電路圖； 圖五A顯示的是依據本發明的一較佳實施例中，模 擬雙埠隨機存取記憶體之位元線上的活動之電路的電路 圖，其包含餘置記憶胞陣列； 圖五B顯示的是依據本發明的一較佳實施例中，使 用於餘置記憶胞陣列中的記憶胞之電路圖； 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公t )A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the Invention (5-1) Field of the Invention The present invention relates to a dual-port (dua, p 0, t) static random access memory (static random access memory). access memo "y: SRAM) high accuracy (dummyce M) used in a self-timing circuit, in particular, it relates to a dual The remaining memory cells used in the high-accuracy automatic timing circuit of the port's static random access memory. 5-2 Background of the Invention In the traditional S RAM, each memory cell applies a voltage through a bit line, It controls the coupling transistor through the gate to act as a load for driving the transistor. The voltage on the bit line is determined by the path resistance of the load transistor. For one of the coupling transistor and the memory cell, the driving transistor combines the path. The resistance ratio is determined. Because the operating characteristics of these transistors will change with the original differences caused by manufacturing and temperature changes, when designing the memory These differences must be factored into their safety margins, and as a result, the performance of the memory will not reach the maximum limit. Especially in the design of modern embedded static random access memory ( Static Random Access Memory: SRAM), because of the trend of high-speed components, self-timing circuits or latch-type amplifiers are increasingly being used to speed up access to this paper. Standards apply to Chinese national standards (CNS) A4 specification (210 X 297 meals) ----- I ------I ----- III ---- II --- (Please read the precautions on the back before filling in this Page) 472255 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 _B7_ V. Description of the invention () Time (accesstime) and cycle. However, when the process size is reduced and the width of the memory bit line is narrowed, the automatic timing is correct The performance will become worse and worse. Even when some process conditions change slightly, it will lead to unacceptable errors in automatic timing, and most of the errors in automatic timing can be attributed to the position. Line activity. In a traditional timing circuit, only the voltage on the bit line is simulated when tracking the state of the bit line. Although in some more advanced designs, the resistance of the bit line is also simulated, it is used for The current source driving the dummy bit line is not as accurate as the current source in the real memory cell. In other words, the voltage change on the dummy bit line will not be the same as the bit in the real memory cell. The voltage on the line is consistent. Therefore, in most automatic timing circuit designs, the simulation of bit line loading and access activity is ignored. Due to the shrinking of the manufacturing process, components with narrow line widths are now used, and the difference in electrical properties between medium-sized components and narrow-sized components is more obvious. In addition, in order to use embedded memory in a logical processor, the logical SPICE module provided by the fab, especially when other external processes are used to make the migrating memory cell, is usually not very correct. Reflects memory cell activity. As a result, the use of a less accurate current source will often result in more inaccurate timing than before. In order to show the automatic timing circuit using redundant bit lines in the embedded memory cell, the structure of the control circuit and the pattern of the redundant memory cell are shown in Figure 1A. For example, the control circuit of Figure 1A can be Character line pulse wave generator 10, and the character line pulse wave is generated by the character line pulse wave. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ------- -------------- Order -------- (Please read the notes on the back before filling out this page) 472255 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Α7 Β7 V. Description of the invention () The dmy_wl terminal of the inverter 10 is transmitted to the inverter Ή, and then the inverter 1 1 precharges the N remaining half memory cells (p "e-cha" ge). Bit line 1 3 is connected to the output of the inverter 1 1 and the bit line 1 3 is connected to a spare memory cell array 15 composed of a plurality of memory cells as a load of the inverter 1 1. Each memory cell in the memory cell is shown as memory cell 17. Memory cell 17 is a dua port memory cell. The circuit diagram is shown in Figure II. VVL1 and word line WL2 are connected to the gates of transistors N4, N5, N6, and N7, respectively. The sources of transistors N4 and N6 are closed to the point DATA, and the former; Are coupled to the bit lines BL and BL 2. Similarly, the sources of the transistors N 5 and N 7 are electrically coupled to the point ZDATA, and the drains of the former are electrically connected to the anti-phase element lines ZBL and ZBL 2. The gate of transistor p 0 is electrically coupled to the gate of transistor N 2 via point NODE 1. In addition, the drain of transistor P 0 is electrically coupled to transistor N 2 at point DATA. Drain. The source of transistor P 0 is electrically coupled to voltage VDD, and the source of transistor N 2 is electrically coupled to V ss. The gate of transistor p 1 is electrically coupled to point N0DE2. The gate of transistor N3. In addition, the drain of transistor P1 is electrically connected to the sum of transistor N4 at the point ZDATA. The source of transistor P1 is electrically connected to the voltage vdd, and the source of transistor N 3 is electrically coupled to the voltage vss. In addition, the wire WIRE1 electrically meets the point .DATA and the point N0DE2, and the wire N0DE2 is electrically Coupling point ZD ΑΑ and point NODE 1. In another example of the conventional spare memory cell array, the inverter 11 can be replaced by a transistor (such as N M 0 S), and it consumes the control cost. Paper size applies Chinese National Standard (CNS) A4 grid (210 X 297 metric t) --------------------- Order · ------- ~ (Please read the Zhuyin on the back? Please fill in this page again for matters) 4 2255. A7 _B7 V. Description of the invention () The circuit diagram of the memory cell array of the circuit is shown in Figure 1B. In order to achieve the goal of high-speed components, the time margin must be reduced to a minimum. Therefore, it is best to track the voltage on the bit lines in ordinary memory cells to minimize the required time margin. However, no matter what kind of conventional spare memory cell array is used, the voltage on the spare bit line cannot accurately track the voltage on the bit line of the general memory cell due to the following reasons. First, the current source of the remaining memory cell of the conventional technology is an inverter or a memory, and the gate width, gate length, and layout of the current source used in the memory cell of the conventional technology (丨 ay 〇ut), different from ordinary memory cells, so its discharge current is different from the discharge current on the spare bit lines in the spare memory cells. Secondly, the process conditions for manufacturing the inverter NMOS are different from the process conditions for manufacturing general memory cells. In addition, when designing the memory, the pattern (pa 11 e "η) and the load related to the remaining bit lines did not consider the worst case. Therefore, when a plurality of load memory cells coupled to the bit line are logic "1" or high voltage level, and when both W L1 and WL 2 are accessed, the voltage on the remaining bit lines cannot accurately track the voltage on the bit lines of general memory cells. Especially on high density devices Under the trend, the number of memory cells will continue to increase, and the difference in load capacitance will seriously affect the accuracy of tracking the voltage of bit lines of general memory cells. Because of the above reasons, the remaining memory cells must be improved to achieve high-speed components The purpose of this invention is 5-3. The purpose of this invention and its outline are applicable to China National Standard (CNS) A4 (210 X 297 g) in 11— 1 ^ 1 ί i 111 m ^^ 1 n I 1 n 1 1 ^ 1 i 1 m i., > lmnnn ^^ 1 an λ (Please read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 2255 A7 _B7 V. Description of Invention For high-speed operation, accurate mold The activity on bit lines in a general memory cell area (such as voltage changes). The present invention provides a bit line of a spare memory cell, which can be used to track bits on a dual-port static random access memory. The voltage of the line changes. The above-mentioned spare memory includes a plurality of word lines, two pairs of bit lines (one of which is a spare bit line and the other for connection), two pairs of load circuits, and a row of memory cells. The above word line is used to receive an access signal, and the two pairs of load circuits are respectively connected to the above two pairs of bit lines, so that during the pre-charge (p "e-cha" ge) cycle, the The remaining bit lines are precharged. When the above access signal reaches the general memory cell coupled to the general bit line, the voltage on the two pairs of bit lines coupled to the memory cell array will track the voltage on the general bit line. General The bit line is electrically coupled to a voltage source, and each memory cell element in the memory cell array has a control terminal connected to the word line, and a pair of anti-pa "all el" inverters Converter, each coupling transistor In response to the access signal, a conduction path is established between one of the two pairs of word lines and one of the two inverters, so that one of the two-bit states of the pair of inverters described above is established. The gate system of one of the inverters is coupled to a voltage source, and the gate system of the other inverter of the pair of inverters is coupled to a source voltage level. The first control terminal of one of the coupled transistors is electrically coupled to the second control terminal of the other of the two coupled transistors. The above-mentioned memory may be a dual-port (duabu ρ 〇rt) Static Random Access Memory (SRAM), this paper size applies to China National Standard (CNS) A4 specifications (210 X 297 male f) 1 I---- i I I --- ^ 4 · 1 1 ------- Order --------- line (please read the precautions on the back before filling this page) Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs * '' < 472255 Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, Aiyinyi A7 _B7 V. Description of Invention () and two of them are negative The circuit includes at least a first field effect transistor (FET), a second field effect transistor, a third field effect transistor, and a fourth field effect transistor, and each of the field effect transistors is in the above voltage source. And array memory cells have a source-drain conduction path, and the gate of the first field effect transistor is electrically coupled to the second field effect transistor, the second field effect transistor, and the fourth field effect transistor Gate. The array memory cell further includes a first group of memory cells and a second group of memory cells. The first group of memory cell lines is used to provide current. The first group of memory cell lines is used as a driver in the memory cell array. The second group of memory cell lines is used to receive current from the first group of memory cells. This line acts as a load in this column of memory cells. Each of the first group of spare memory cells has a first inverter, the first inverter is set to the first state of the two-bit state, and is electrically converted into two pairs of bit lines First bit line. Each of the first group of memory cells has a first word line, and the first word line of each of the first group of memory cells is electrically coupled to receive the access signal. Each of the second group of memory cells has a second inverter, and the second inverter is set to a second state in a two-bit state, and each second inverter is electrically coupled to the pair This first bit line in the bit line, each of the above-mentioned second group of memory cells has a second word line, and the second word line in the second group of memory cells is electrically coupled to the above Source voltage level. In order to obtain a voltage that can be accurately tracked on a general bit line, a triggering device is electrically coupled to the above-mentioned first bit line, and this paper size applies the Chinese National Standard (CNS) Al specification (210 X 297 mm) t) i-I III—— — — — — — — — — — ill— «I i IIIIII (Please read the notes on the back before filling out this page) 472255 Printed by the Intellectual Property Bureau Employee Consumer Cooperatives of the Ministry of Economic Affairs Δ7 B7_ Five 2. Description of the invention () and the output of the triggering device is electrically coupled to the control circuit that generates the access signal. The triggering device in the preferred embodiment of the present invention may be a Schmitt trigger or an inverter. 5-4 Brief Description of the Schematic The following descriptions, combined with the following diagrams, will give a clearer understanding of the features of the present invention, of which: Figure 1A shows the traditional surplus using an inverter as a current source Memory cell array; Figure 1B shows a traditional spare memory cell array using N-type metal-oxide-semiconductor field-effect transistor (N M 0 S) as a current source; Figure 2 shows a circuit diagram of a traditional memory cell; Figure 3 shows a circuit diagram of the memory cells used in the spare memory cell array in a preferred embodiment according to the present invention; Figure 4A shows the time when a port of the memory cell is in the "reading" state, etc. Fig. 4B shows the equivalent circuit diagram when both ports of the memory cell are in the "reading" state. Fig. 5A shows an analog dual port random in a preferred embodiment according to the present invention. A circuit diagram of an active circuit on a bit line for accessing a memory, which includes a spare memory cell array. FIG. 5B shows a memory used in the spare memory cell array according to a preferred embodiment of the present invention. Circuit diagram of cell Zhang scale applicable Chinese National Standard (CNS) A4 size (210 X 297 male t)
In HI HI In i I in ϋ In In i ί I —111 I— ft i In 1—· ^ 0< _ I I I-1 UK n m I - I (請先閱讀背面之注意事項再填寫本頁) 472255 A7 _B7 五、發明說明（） 圖六顯示的是依據本發明的一較佳實施例中，在餘 置位元線上的餘置記憶胞之圖樣（p a 11 e r η )，並顯示餘置 記憶胞陣列以及一般記憶胞陣列之安排； (請先閱讀背面之注意事項再填寫本頁) 圖七顯示的是一般位元線上之電壓變化及依據本 發明的一較佳實施例所製造出來的餘置位元線上的電壓 變化之比較； 圖八顯示的是預充電電路之運作和’預充電’端所控 制的Ρ Μ 0 S、位元線B L、以及由字元線B L所控制的Ν Μ〇S 上的電壓變化。 5-5發明詳細說明 經濟部智慧財產局員工消費合作社印製 為了要在各種不同的工作狀態中，正確的追蹤一般 記憶胞的位元線上之電壓，所以在本發明中，用以製造餘 置位元線的製程條件亦是用來製造一般位元線的相同製 程。此外，在本發明的餘置記憶胞陣列中的電晶體之佈線 (I a y 〇 u t)的長與寬，應該與一般記憶胞者相同，以對於餘 置位元線提供與一般記憶胞中的位元線上相同之電流。因 為位元線和記憶胞之間存在有電容，一般記憶胞的位元線 之時間常數，特別在記憶胞數目增加時，也會隨著增加。 然而一般傳統的餘置記憶胞中的位元線並不位於餘置記 憶胞上方，所以餘置位元線的電容效應與一般位元線之電 容效應不同，故習知技術並不能準確追蹤位元線上的電 壓。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 472255 經濟部智慧財產局員工消費合作社印5衣 A7 B7 五、發明說明（） 因為習知技術的上述缺點，本發明提出一種餘置記 憶胞，其具有與一般記憶胞相同的電晶體（例如金氧半電 晶體：Metal Oxide Semiconductor transistor)佈 '線，因 為用於製造餘置記憶胞的電晶體之製程，與用於製造一般 記憶胞之電晶體之製程為相同製程，所以餘置記憶胞中電 流源上的電流，與一般記憶胞中的電流源上之電流相同。 此外，本發明使用作為餘置記憶胞者，其是將記憶胞中的 導線WIRE1與WIRE2(圖二中）去除，並且將其中的位元 線W L 1與W L 2相連接。依據本發明的一較佳實施例所製 造的餘置記憶胞之電路顯示於圖三中，藉由上述的原理， 本發明可以模擬兩個埠都位於高電壓準位，亦即，最差的 狀況下，依據本發明的記憶胞可以模擬此最差狀況下，記 憶胞中之電流。 為了解釋在記憶胞陣列中所發生的最差之狀況，存 取電晶體的等效電路圖顯示於圖四A與圖四B中。當記 憶胞在運作時，可能記憶胞的兩個埠都是在”讀取"的運作 狀態下。此時，兩字元線（例如圖二中的W L 1與W L 2 )是 在高邏輯電壓準位，所以存取電晶體（例如N 4、N 6、N 5、 N 7)在電路中是等效於電阻器。參照回圖二中，當一個埠 在”讀取”運作狀態下時，亦即，一個埠是在高邏輯電壓準 位時，字元線B L是位於高邏輯電壓準位，並且電晶體N 4 被打開，所以電晶體N 4與N 2的等效電路為電阻器，並 且其電路中每一個節點（node)上的電壓都顯示於圖四 A 中。然而當兩個埠都是在”讀取”運作狀態下時，亦即，兩 本紙張尺度適用中國國家標準（CNSM4規格（210 X 297公t ) en i 1^y--1ί ^^1 m 訂---------線 (請先閱讀背面之注意事項再填寫本頁) 472255 A7 B7_ 五、發明說明（) (請先閱讀背面之注意事項再填寫本頁) 個埠都是在高邏輯電壓準位時，字元線B L與B L 2是位於 高邏輯電壓準位，並且電晶體N 4與N 6被打開，所以電 晶體N4、N6與N2的等效電路為電阻器，並且其電路中 每一個節點上的電壓都顯示於圖四 B中。其中，圖四 B 中的節點DATA上的電壓，較圖四A中者為高，其原因 是因為在兩個埠都在”讀取”運作狀態時，電晶體N 4與N 6 是並聯的。 經濟部智慧財產局員工消費合作社印裂 因為兩個埠都在”讀取”運作狀態時的節點D ATA上 之電壓的壓降較只有一個埠在”讀取”運作狀態時的節點 D A T A上之電壓的壓降為高，所以電晶體N 4之臨界電壓 (threshold voltage)因為節點DATA上的電壓提高所導致 的body effect而提高，又因為電晶體N4中的源汲電流 (sou「ce-d「a in current)之大小與源極汲極壓降減去臨界 電壓之後的值成正比，因此電晶體 N 4的源汲電流會減 小。據上所述，在最差狀況下的位元線上的電流大小與只 有一個埠為高邏輯電壓準位的狀況下的位元線上的電流 大小並不相同，其中上述的最差之狀況即是兩個埠都為高 邏輯電壓準位的情形。此外，傳統記憶胞中的每一個存取 電晶體（例如電晶體N 4與N 6 )分別被電性耦合到越過記 憶胞上方的字元線（例如 W L 1 與 W L 2 )，所以其佈線 (丨a y 〇 u t)所遭遇的問題將極為複雜，並且橫越過餘置記憶 胞的字元線也可能導致無法預期的影響。因此最好可以使 用其他金屬層以連接餘置記憶胞中所必需要的兩條字元 線，以減少橫越過餘置記憶胞的字元線之數目。一般記憶 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） 472255 經濟部智慧財產局員工消費合作社印*1衣 A7 B7 五、發明說明（） 胞中的字元線w L1與w L 2需要空間以越過餘置記憶胞而 到達一般記憶胞。 本發明提出一種使用於餘置記憶胞陣列（dummy memory cell array)中的一種記憶胞，並且依據本發明的 一較佳實施例中的餘置記憶胞之電路圖顯示在圖五 A 中，如其所示，記憶胞3 7是一個雙埠（d u a l·- ρ 〇 r t)靜態隨 機存取記憶體（SRAM)，其電路圖如圖五B所示，其中餘 置記憶胞中的字元線DMYWL12’被耦合到電晶體 N4’、 N 5 ’以及電晶體N 6、N 7 ’的閘極。電晶體N 4 ’及N 6 源極 (source)被電性耦合到節點 DATA，，並且前者的汲極 (drain)被分別連接到位元線DM YBL’以及 DM YBL2’。電 晶體N ^的閘極被連接到電晶體N 6 ’的閘極。相似的，電 晶體N5'及N7'的源極在節點ZDATA’耦合在一起，並且 前者的汲極分別被連.接到位元線的反相，亦即Z D Μ Y B L ’ 以及 ZDMYBL21。 於圖五Β中，電晶體P CT的閘極經由點Ν 0 D Ε 1 ’被 電性耦合到電晶體Ν 2 ’的閘極以連接到電壓V d d，另外， 電晶體 P0’的汲極在節點 DATA’處被電性耦合到電晶體 N2’的汲極。電晶體 PCT的源極被電性耦合到節點 N0DE1 ’，並且電晶體N2>源極被電性耦合到電壓Vss， 電晶體P 1 ’的閘極經由節點N 0 D E 2 4皮電性耦合到電晶體 N 3 ^的閘極以連接到電壓 V s s，此外，電晶體 P 1 ’的汲極 在節點ZD ΑΤΑ’處，被電性耦合到電晶體Nt的汲極。電 晶體P 1'的源極被電性耦合到電壓Vdd，並且電晶體N 3' 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公坌） --------^----------I (請先閱讀背面之注意事項再填寫本頁) 472255 經濟部智慧財產局員工消費合作社印製 A7 ______B7 _^_ 五、發明說明（） 的源極被電性耦合到電壓Vs s。值得注意的是在本發明的 餘置記憶胞中的節點N 0 D E r與N 0 D E 2 ’之間，並沒有交 互耦合，並且此為本發明與習知技術的餘置記憶胞有差異 之處的其中之一。 當顯示於圖五A的記憶胞3 7被用來作為本發明中 作為餘置記憶胞時，本發明的餘置記憶胞陣列之一較佳實 施例之電路圖如圖五B所示。字元線D Μ 丫 W L 1 2 ’（圖五B 中）被連接到端點DMYWL1 2’（圖五Α中），位元線DMYBU (圖五B中）被連接到端點D Μ 丫 B L ’ （圖五A中），位元線 DMYBL2’（圖五B令）被連接到端點DMYBL2,（圖五A中）， 而反相位元線 Z D Μ Y B L'(圖五 Β 中）被連接到端點 ZDMYBL’（圖五Α争），並且反相位元線ZDMYBL2，（圖五Β 中）被連接到端點ZDMYBL2’（圖五A _)。 此外’電流源4 0 a對負載4 0 b提供電流，假設記憶 胞陣列4 0是由η個記憶胞所構成，電流源4 0 a可以由k 個記憶胞所構成，而在本發明的—較佳實施例中，k可以 是4，一般而言k.值不會小於4。而在本發明的一較佳實 施例中’負載40b可以是由（n-k)個記憶胞所構成。而由 控制電路46的餘置字元線端dmy_wl'所輸出的訊號被饋 送到電流源4 0 a的每一個記憶胞的字元線D Μ Y W L 1 2 1 中，其中電流源40a是作為驅動器，以對負載40b的記 憶胞提供電流。 由電流源4 0 a的k個記憶胞輸出之電流，經由餘置 位元線DMY_BL'被饋入至反相器43，並且反相器43的 本紙張尺度適用中國國家標準（CNS)A4規>格（2〖〇χ 297公釐） — II---— III -III — — — — -----I I I I (請先閱讀背面之注意事項再填寫本頁) 472255 經濟部智慧財產局員工消t合作社印製 A7 B7_ 五、發明說明（） 輸出被連接到反相餘置字元線Z D Μ Y_ B LJ，其上之訊號為 位元線D Μ Y_ B L1之反相。反相餘置位元線上的訊號係由 反相器4 3饋入到控制電路4 6 (例如位元線脈波產生器）的 端點zdmy — bl1上，反相器43是一個觸發（trigger)裝置， 其在本發明的一較佳實施例中，可以是一個施密特 (S c h m i 11)觸發電路，然後字元線脈波經由控制電路4 6的 字元線脈波產生器的端點 wl_plus'而輸出到點 WLPULSE、圖五A中複數個PM〇S中的每一個都是被用 來作為位元線預充電所用的。當一個位元線要被進行存取 時，連接到位元線的P Μ〇S是”關”的，然而在對位元線完 成存取動作之後，連接到該位元線的Ρ Μ 0 S是”開”的，以 對於耦合到該 PMOS的相關之記憶胞預充電到電壓 V d d，以準備下一次存取運作。 為了更進一步說明一般記憶胞陣列聯合餘置記憶 胞陣列之運作，一般記憶胞陣列以及依據本發明的一較佳 實施例之餘置記憶胞的排列顯示於圖六中，其中餘置記憶 胞區域60a以及一般記憶胞區域60b是在同一晶片的一 個區域6◦中，所以用於製造區域60a中的元件之製程， 與用於製造區域60b内元件之製程是相同的製程。 因此在餘置記憶胞區域 6 0 a 中的餘置位元線 D Μ 丫_ B L'的電性（例如電阻或電容），會與位於一般記憶胞 區域6 0 b中的一般位元線B L/之電性相同。在本發明的一 較佳實施例之一種態樣中，一般記憶胞陣列區域6 0 b包 含複數個一般記憶胞陣列’例如6 1、6 2以及6 3。一般記 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公f ) ---^ HI n n ^if n n. m 1rf厂^-1 4 n (n ^^1 n f^i -»-1 n 一 .辛 I i ---1 m I m HI- i I (請先閱讀背面之注意事項再填寫本頁) 472255 A7 B7 五、發明說明（） (請先閱讀背面之注意事項再填寫本頁) 憶胞陣列6 1包含一個作為驅動器的記憶胞陣列6 1 a，以 及複數個作為負載的記憶胞6 1 b。使用於一般記憶胞區域 6 0 b的記憶胞（例如6 1 a或6 1 b )具有與圖二所示的記憶胞 1 7相同的結構。 餘置記憶胞陣列 65包含電流源 65a以及負載 6 5 b，在本發明的一較佳實施例中，電流源6 5 a包含了四 個本發明所提出的記憶胞，其結構與圖五B所示的記憶 胞3 7相同。本發明所提出的記憶胞之餘置記憶胞區域内 的兩子元線被連接在· 起’並且在電流源6 5 3的記憶胞 是由控制電路4 6 (圖五A)所控制。如圖六所示，在電流源 65a的記憶胞中儲存邏輯”0”的電晶體被耦合到餘置位元 線DMY_BU，此外，負載65b的圖樣顯示於圖六申，其 中在負載6 5 b中儲存有邏輯” 1 ”的電晶體都被耦合到位元 線 DMY_BL'。 經濟部智慧財產局員工消費合作社印製 所以依據本發明的較佳實施例中的餘置記憶胞，其 可以模擬當一個雙埠記憶體的兩個埠同時被讀進行存取 動作，使得在位元.線上具有最差情況下的放電電流。值得 注意的是，在現代的記憶胞設計中，金屬導線常被用來作 為交互耦合之導線，而在後段製程中，金屬導線之間一些 小小的差異，並不會導致餘置記憶胞中的電晶體與一般記 憶胞中的電晶體不匹配（m i s m a t c h )。然而在對於這兩個反 相器（參閱圖五B，耦合在N2’的P0和耦合在N3旧P1) 都必.須如同一般記憶胞，必須將其形成相同的元件圖樣， 以避免0D以及POLY(未圖示）在前段製程中不匹配。依 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公蜚） 472255 經濟部智慧財產局員工消費合作社印*'1农 A7 B7_ 五、發明說明（） 據上述兩個考慮，本發明的一較佳實施例在所提出的雙埠 餘置記憶胞中，以一個外加的導線3 8 (圖五B )耦合兩個字 元線DMYWL12、並且不使用交互耦合導線（圖二中的 W I R E 1及WI R E 2 )，以使其可以提供與一般記憶胞提供相 同的電流。 甚至因為負載6 5 b中的圖樣（對於儲存有邏輯” 1”而 耦合到餘置位元線的電晶體之安排），其中在位元線上不 動作的記憶胞之電容效應，會延緩電壓之降低。因為餘置 位元線的主要目的就是要模擬一般位元線的放電活動，所 以負載65b(圖六中）的圖樣可以防止位元線由預充電的 值放電時，可能遭遇的最差之負載電容效應，也因此本發 明的餘置位元線上的電壓就可以準確地追蹤一般位元線 上的電壓變化。在用以模擬一般位元線上的電壓變化之傳 統電路當中，傳統的餘置位元線上之電壓並不會隨著一般 位元線上的電壓而線性的改變。然而用以模擬一般位元線 上的電壓變化之電路所具有之特性，是本發明的餘置位元 線上的電壓可以隨著一般位元線上的電壓變化而線性的 變化。所以不論多少記憶胞被用來作為電流源，本發明都 可以高度準確地模擬一般位元線上的電壓。如果用以製造 記憶胞與位元線的製程改變了，傳統的餘置位元線上的電 流可能飄移掉，因此在習知技術中，對於一般位元線上的 電流之模擬會失敗，然而在本發明中，縱使製程改變，餘 置位元線也可以準確地模擬一般位元線上的電流。總之， 不管製程改變、操作溫度改變以及V d d改變，本發明都 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公t ) II--------1 I--33V·---I ---^ --------- (請先閱讀背面之注意事項再填寫本頁) 472255 經濟部智慧財產局員工消費合作社印製 A7 B7__ 五、發明說明（） 可以高度準確的模擬一般位元線上的電壓。 以一個可以提供與一般記憶胞相同放電電流的餘 置記憶胞’連同對於位元線放電最差情形下的電容負載之 圖樣為例’具有K個記憶胞的餘置位元線上的電壓降就 是一般位元線的最小壓降之K倍。例如圖七中的線8 0所 示的’其為一個一般記憶胞在放電過程中之電廢變化，則 餘置記憶胞在放電過程中的電壓變化就如線8 1所示，其 中線8 1是代表有K個一般記憶胞被用來作為電流源。因 為本發明可以線性地因應一般位元線上的電壓變化，而提 供準確的電壓模擬，以致使得對於下一級的計時控制 (timing control)變為可行，而此在習知技術中是做不到 的。 為了彳苗述用於模擬一般位元線上的電壓變化之預 充電電路的運作，端點precharge'、位元線DMYBL1、以 及字元線DMYWL12’上的電壓變化都顯示在圖八中。當 端點 precharge’上的電壓變低（例如 0)時，由端點 p r e c h a r g e'(圖六中）所控制的 P Μ〇S是打開的，位元線 DMYBL’上的電壓是Vdd，並且由字元線DMYWL12’所控 制的N Μ〇S是關閉的。因為端點p r e c h a「g e ’由低邏輯準 位被充電到高邏輯準位，P Μ〇S由打開轉變到關閉。並且 在一段預設時間之後，由字元線 DMYWL 12'所控制的 N Μ 0 S由關閉轉變到打開，並且字元線D Μ Y B L ’上的電壓 線性地由Vdd下降，直到由字元線DMYWL1 2'所控制的 N Μ 0 S由打開切換到關閉。在N Μ 0 S的週期當中，記憶 本纸張尺度適用中國國家標準（CNS)A4規格（2】0 X 297公釐） n I— II ί n I n n n· mm— I · n n n n n .1 n ^ e* · n n n n n n ( (請先閱讀背面之注意事項再填寫本頁) 472255 經濟部智逑时產局員工消費合作社印製 A7 B7_ 五、發明說明（） 胞是在”讀取”狀態，並且當N Μ 0 S由高邏輯準位（V d d )切 換到低邏輯準位（0)時，位元線上的電壓保持在電壓值為 Vd d - △ V處，直到由端點p recharge'所控制的PMQS由 關閉切換到打開，然後位元線DMYBU由電壓Vdd - △ V充 電到電壓值Vdd。 在線8 0與線81之間的比例關係是線性的，例如當 在一個特定時間中，一般記憶胞的電壓降是V d r ο p，同時 餘置記憶胞上的壓降就是其K倍（K · Vd「op)，所以其線性 比例關係可以施於具有不同製程及不同尺寸電晶體的記 憶胞中。 當本發明被使用於一個字元線脈波控制電路時，於 本發明中並不需要用到在一般傳統字元線脈波控制電路 所必須的時間邊限，在一般傳統字元線脈波控制電路中， 為了要在位元線之間獲得足夠的電壓差’並且為了有足夠 的時間作為寫入動作所需，所以字元線脈波寬度不可以太 小，因此在傳統的隨機靜態存取記憶體（SRAM)的設計 中，字元線脈波寬度必須具有一定的額外餘裕邊限（extra m a r g i η )，以應付一些較差的情況。雖然如此，這些額外 的餘裕邊限並不一定能完全包容所有的最差的情況（例如 因為位元線的製程缺陷所導致的時間常數變化），但是這 種做法卻一定會造成記憶體的週期被延長，而上述情形也 會使得在大量生產時的良率降低。 一個高準確度的餘置位元線電路（圖五 Α六中的餘 置記憶胞陣列4 0)可以提供一個負回授，以控制一個字元 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 訂--- 線 472255 A7 _B7__ 五、發明說明（） 線脈波寬度控制電路（圖五A中的控制電路46)，所以與 本發明的較佳實施例中的餘置位元線連同運作的字元線 脈波寬度控制器可以高度準確的追蹤一般位元線上的電 性活動。並且因為在本發明中可以省略額外的餘裕邊限， 所以字元線脈波寬度可以被設計成最窄的寬度，以作為讀 /寫操作所需，這些字元線脈波寬度可以因為不同的操作 狀況或製程所導致的位元線活動之改變，而改變其字元線 脈波寬度。 這些可以使得内嵌式（e m b e d d e d)記憶胞的設計，在 製造這些記憶體的製程更具有彈性，以一般或較典型的製 程而言，通常希望記憶胞有較短操作週期，而沒有固定字 元線脈衝寬度的限制，並且避免原來為了一些較差的情況 所必須增加的額外時間餘裕邊限。對於一些較慢的元件之 製程或是記憶胞位元線中一些較次要的缺陷而言，這種自 動計時字元線脈波控制電路可以產生較長的字元線脈波 寬度，以保護記憶胞免於失敗（f a i丨u「e)。因此-，對於那些 可能需要容忍一些額外記憶胞運作時間的晶片設計而 言，本發明可以有較佳的良率，而不必理會字元線脈波之 脈波寬度。 -------------f * tn I m n a 1 訂---------線 (請先閱讀背面之注意事項再填冩本頁) 以示 用揭 fcr 斤 Ja, 戶 並明 ，發 已本 而離 例脫 施未實它 佳其 較凡 之 明 發 本 為 僅 述 所 上 以 經濟部智竓財產局員'工消費合作社印製 圍 範 利專 請申 之 明 發 本 定 限 如發故 例本。，在弋 ， ^^方 或圖改 變載修 改負其 效之知 等列得 之陣者 成胞藝 完憶技 所記項 下置該 神餘知 精中習 之例使 在明 施即之 實，露 的後揭 明之明 發露發 本揭本 在 本紙張尺度適用中國國家標準（CNS)A4規烙（21〇χ 297公坌） 472255 __B7_ 五、發明說明（） 後，任何對於本發明實施例所作之修改，皆不脫本發明的 精神和範圍之外，故其應包含在下述之申請專利範圍内。 經-部智慧时產局員工消費合作社印製 20 -------------矿--------訂. (請先閱讀背面之注意事項再填冩本頁) 本紙張尺度適用中國國家標準（CNS)A4規烙（210 X 297公發）In HI HI In i I in ϋ In In i ί I —111 I— ft i In 1— · ^ 0 < _ II I-1 UK nm I-I (Please read the precautions on the back before filling this page) 472255 A7 _B7 V. Description of the invention (Figure 6) shows a pattern (pa 11 er η) of the spare memory cells on the spare bit line in a preferred embodiment according to the present invention, and displays the spare memory cells Array and general memory cell array arrangement; (Please read the precautions on the back before filling this page) Figure 7 shows the voltage change on the general bit line and the surplus produced according to a preferred embodiment of the present invention Comparison of the voltage changes on the bit line; Figure 8 shows the operation of the precharge circuit and the PM0S controlled by the 'precharge' terminal, the bit line BL, and the NM controlled by the word line BL. Voltage change on S. 5-5 Detailed description of the invention Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. In order to accurately track the voltage on the bit line of general memory cells in various working states, in the present invention, it is used to create surplus The bit line process conditions are also the same process used to make general bit lines. In addition, the length and width of the wiring (I ay ut) of the transistor in the spare memory cell array of the present invention should be the same as those of ordinary memory cells, so as to provide the spare bit lines with the The same current on the bit line. Because there is capacitance between the bit line and the memory cell, the time constant of the bit line of the general memory cell, especially as the number of memory cells increases, also increases. However, the bit line in the conventional conventional memory cell is not located above the redundant memory cell, so the capacitive effect of the redundant bit line is different from that of the general bit line, so the conventional technology cannot accurately track the bit. Voltage on the element line. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 472255 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention () Because of the above-mentioned shortcomings of the known technology, the present invention proposes A spare memory cell having the same transistor (for example, Metal Oxide Semiconductor transistor) wiring as a general memory cell, because the manufacturing process of the transistor for the spare memory cell and the The manufacturing process of the general memory cell transistor is the same process, so the current on the current source in the remaining memory cell is the same as the current on the current source in the general memory cell. In addition, the present invention is used as a spare memory cell, which is to remove the wires WIRE1 and WIRE2 (in Fig. 2) in the memory cell and connect the bit lines W L 1 and W L 2 therein. The circuit of the spare memory cell manufactured according to a preferred embodiment of the present invention is shown in FIG. 3. By the principle described above, the present invention can simulate that both ports are at a high voltage level, that is, the worst Under the condition, the memory cell according to the present invention can simulate the current in the memory cell in this worst case. In order to explain the worst situation that occurs in the memory cell array, the equivalent circuit diagrams of the memory transistors are shown in Figure 4A and Figure 4B. When the memory cell is operating, it is possible that both ports of the memory cell are in the "reading" operating state. At this time, the two-character lines (such as WL 1 and WL 2 in Figure 2) are in high logic Voltage level, so the access transistor (such as N 4, N 6, N 5, N 7) is equivalent to a resistor in the circuit. Referring back to Figure 2, when a port is in the "read" operating state When a port is at a high logic voltage level, the word line BL is at a high logic voltage level and the transistor N 4 is turned on, so the equivalent circuit of the transistors N 4 and N 2 is a resistor And the voltage on each node in the circuit is shown in Figure 4A. However, when both ports are in the "reading" operating state, that is, the two paper standards are applicable to the Chinese country Standard (CNSM4 specification (210 X 297g t) en i 1 ^ y--1ί ^^ 1 m order --------- line (Please read the precautions on the back before filling this page) 472255 A7 B7_ V. Description of the invention () (Please read the notes on the back before filling this page) When the ports are at high logic voltage level, the word lines BL and BL 2 are bit High logic voltage level, and transistors N 4 and N 6 are turned on, so the equivalent circuits of transistors N 4, N 6 and N 2 are resistors, and the voltage at each node in the circuit is shown in Figure 4B. The voltage at node DATA in Figure 4B is higher than that in Figure 4A because the transistors N 4 and N 6 are connected in parallel when both ports are in the "reading" operating state. The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs is cracked because the voltage drop across the node D ATA when both ports are in the "reading" operating state compared to the node DATA when only one port is in the "reading" operating state The voltage drop across the voltage is high, so the threshold voltage of transistor N 4 is increased by the body effect caused by the voltage increase at node DATA, and because the source sink current in transistor N 4 (sou "ce -d "a in current" is proportional to the value of the source drain voltage drop minus the threshold voltage, so the source drain current of transistor N 4 will decrease. According to the above, the worst case The amount of current on the bit line and only one port is high logic The current level on the bit line is not the same when the voltage level is set. The worst case is the case where both ports are at high logic voltage levels. In addition, each of the traditional memory cells stores The power-taking transistors (such as transistors N 4 and N 6) are electrically coupled to the word lines (such as WL 1 and WL 2) that pass above the memory cells, respectively, so the problems encountered in their wiring (丨 ay 〇ut) will Extremely complex, and crossing character lines across spare memory cells can also cause unpredictable effects. Therefore, it is better to use other metal layers to connect the two character lines necessary in the remaining memory cells to reduce the number of word lines crossing the remaining memory cells. General memory This paper size applies the Chinese National Standard (CNS) A4 specification (210 x 297 mm) 472255 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs * 1 A7 B7 V. Description of the invention () Character line w L1 And w L 2 needs space to pass the remaining memory cells to reach the general memory cells. The present invention provides a memory cell for use in a dummy memory cell array, and a circuit diagram of the dummy memory cell according to a preferred embodiment of the present invention is shown in FIG. 5A, as shown in FIG. It is shown that the memory cell 37 is a dual-port (dual · -ρ 〇rt) static random access memory (SRAM). The circuit diagram is shown in Figure 5B. The word line DMYWL12 'in the remaining memory cell is Coupled to the gates of transistors N4 ', N5' and transistors N6, N7 '. The transistors N 4 ′ and N 6 source are electrically coupled to the node DATA, and the former drains are connected to the bit lines DM YBL ′ and DM YBL2 ′, respectively. The gate of transistor N ^ is connected to the gate of transistor N6 '. Similarly, the sources of the transistors N5 'and N7' are coupled together at the node ZDATA ', and the drains of the former are connected respectively. They are connected to the inverse of the bit line, that is, Z D M Y B L' and ZDMYBL21. In FIG. 5B, the gate of the transistor P CT is electrically coupled to the gate of the transistor N 2 ′ via the point N 0 D Ε 1 ′ to be connected to the voltage V dd. In addition, the drain of the transistor P 0 ′ It is electrically coupled to the drain of transistor N2 'at node DATA'. The source of the transistor PCT is electrically coupled to the node N0DE1 ', and the source of the transistor N2> is electrically coupled to the voltage Vss, and the gate of the transistor P1' is electrically coupled to the node N0 DE 2 4 The gate of the transistor N 3 ^ is connected to the voltage V ss. In addition, the drain of the transistor P 1 ′ is electrically coupled to the drain of the transistor Nt at the node ZD AT ′. The source of the transistor P 1 'is electrically coupled to the voltage Vdd, and the transistor N 3' is in accordance with the Chinese National Standard (CNS) A4 specification (210 X 297 cm). -------- ^ ---------- I (Please read the notes on the back before filling this page) 472255 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 ______B7 _ ^ _ V. The source of the invention description () Electrically coupled to the voltage Vs s. It is worth noting that there is no cross coupling between the nodes N 0 DE r and N 0 DE 2 ′ in the spare memory cells of the present invention, and this is a difference between the spare memory cells of the present invention and the conventional technology One of them. When the memory cell 37 shown in FIG. 5A is used as the spare memory cell in the present invention, a circuit diagram of a preferred embodiment of the spare memory cell array of the present invention is shown in FIG. 5B. The character line D Μ γ WL 1 2 ′ (in FIG. 5B) is connected to the terminal DMYWL1 2 ′ (FIG. 5 A), and the bit line DMYBU (in FIG. 5B) is connected to the terminal D Μ γ BL '(In Fig. 5A), the bit line DMYBL2' (order in Fig. 5B) is connected to the end point DMYBL2, (in Fig. 5A), and the inverse phase element line ZD Μ YB L '(in Fig. 5B) It is connected to the terminal ZDMYBL '(Figure 5A), and the anti-phase element line ZDMYBL2, (in Figure 5B) is connected to the terminal ZDMYBL2' (Figure 5A_). In addition, the current source 4 a provides current to the load 4 0 b. Assuming that the memory cell array 40 is composed of n memory cells, the current source 4 0 a may be composed of k memory cells. In the present invention— In a preferred embodiment, k may be 4, and generally, the value of k. Is not less than 4. In a preferred embodiment of the present invention, the 'load 40b' may be composed of (n-k) memory cells. The signal output by the redundant word line terminal dmy_wl 'of the control circuit 46 is fed to the word line D M YWL 1 2 1 of each memory cell of the current source 40a, where the current source 40a is used as a driver To provide current to the memory cell at load 40b. The current output by the k memory cells of the current source 4 0 a is fed to the inverter 43 via the remaining bit line DMY_BL ', and the paper size of the inverter 43 is in accordance with the Chinese National Standard (CNS) A4 regulations > Grid (2 〖〇χ 297mm） — II ---— III -III — — — — ----- IIII (Please read the notes on the back before filling this page) 472255 Intellectual Property Bureau, Ministry of Economic Affairs A7 B7_ printed by the employee cooperative. V. Description of the invention () The output is connected to the inverted surplus word line ZD M Y_ B LJ. The signal on it is the inverted of the bit line D M Y_ B L1. The signal on the inverse redundant bit line is fed by the inverter 4 3 to the terminal zdmy — bl1 of the control circuit 4 6 (for example, the bit line pulse generator). The inverter 43 is a trigger (trigger ) Device, which may be a Schmitt (Schmi 11) trigger circuit in a preferred embodiment of the present invention, and then the word line pulse wave passes through the terminal of the word line pulse wave generator of the control circuit 46. The point wl_plus' is output to the point WLPULSE, and each of the plurality of PMOS in FIG. 5A is used to precharge the bit line. When a bit line is to be accessed, the P MOS connected to the bit line is "off". However, after the access to the bit line is completed, the P MOS connected to the bit line is closed. It is "on" to precharge the associated memory cell coupled to the PMOS to the voltage V dd in preparation for the next access operation. In order to further explain the operation of the general memory cell array and the spare memory cell array, the arrangement of the general memory cell array and the spare memory cell according to a preferred embodiment of the present invention is shown in FIG. 6, where the spare memory cell area 60a and the general memory cell region 60b are in a region 6 of the same chip, so the process for manufacturing the elements in the region 60a is the same process as the process for manufacturing the elements in the region 60b. Therefore, the electrical properties (such as resistance or capacitance) of the dummy bit line D Μ _ _ B L 'in the dummy memory cell area 60 a will be the same as the general bit line located in the general memory cell area 60 b. The electrical properties of BL / are the same. In one aspect of a preferred embodiment of the present invention, the general memory cell array region 60b includes a plurality of general memory cell arrays' such as 61, 62, and 63. The size of general paper is applicable to Chinese National Standard (CNS) A4 (210 X 297 male f) --- ^ HI nn ^ if n n. M 1rf factory ^ -1 4 n (n ^^ 1 nf ^ i-» -1 n I. Xin I i --- 1 m I m HI- i I (Please read the precautions on the back before filling this page) 472255 A7 B7 V. Description of the invention () (Please read the precautions on the back before (Fill in this page) The memory cell array 6 1 includes a memory cell array 6 1 a as a drive, and a plurality of memory cells 6 1 b as a load. The memory cells are used in the general memory cell area 6 0 b (for example, 6 1 a Or 6 1 b) has the same structure as the memory cell 17 shown in FIG. 2. The remaining memory cell array 65 includes a current source 65a and a load 6 5 b. In a preferred embodiment of the present invention, the current source 6 5a contains four memory cells proposed by the present invention, the structure of which is the same as the memory cells 3 7 shown in Figure 5B. The two sub-element lines in the region of the remaining memory cells of the memory cell proposed by the present invention are connected The memory cell of the current source 6 5 3 is controlled by the control circuit 4 6 (Fig. 5A). As shown in Fig. 6, the memory cell of the current source 65a is stored. The transistor of logic "0" is coupled to the redundant bit line DMY_BU. In addition, the pattern of load 65b is shown in Figure 6; in which the transistor of logic "1" is stored in the load 6 5 b is coupled to the bit. Line DMY_BL '. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economics. According to the remaining memory cells in the preferred embodiment of the present invention, it can simulate when two ports of a dual-port memory are read simultaneously for access. This makes the worst-case discharge current on the bit line. It is worth noting that in modern memory cell design, metal wires are often used as cross-coupling wires. In the later process, the metal wires Some small differences between them will not cause mismatch between the transistors in the remaining memory cells and the transistors in general memory cells. However, for these two inverters (see Figure 5B, the coupling between Both P0 of N2 'and the old P1 of N3 must be coupled. It must be the same as the general memory cell, and it must be formed into the same component pattern to avoid the mismatch between 0D and POLY (not shown) in the previous process. Zhang scale is applicable to China National Standard (CNS) A4 specification (210 X 297 gong) 472255 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs * '1 Nong A7 B7_ 5. Description of the invention () According to the above two considerations, In the proposed dual-port redundant memory cell, two word lines DMYWL12 are coupled with an additional wire 3 8 (Figure 5B), and no cross-coupling wires are used (WIRE 1 and WIRE in Figure 2). WI RE 2), so that it can provide the same current as the general memory cell. Even because of the pattern in the load 6 5 b (for the transistor that is coupled to the spare bit line with the logic “1” stored), the capacitive effect of the memory cells that do not operate on the bit line will delay the voltage. reduce. Because the main purpose of the spare bit line is to simulate the discharge activity of the general bit line, the pattern of load 65b (Figure 6) can prevent the worst load that the bit line may encounter when it is discharged from the precharged value. The capacitance effect, therefore, the voltage on the spare bit line of the present invention can accurately track the voltage change on the general bit line. In the traditional circuit used to simulate the voltage change on the general bit line, the voltage on the conventional redundant bit line does not change linearly with the voltage on the general bit line. However, the characteristic of the circuit for simulating the voltage change on the general bit line is that the voltage on the spare bit line of the present invention can change linearly with the voltage change on the general bit line. So no matter how many memory cells are used as the current source, the present invention can highly accurately simulate the voltage on general bit lines. If the process used to make the memory cell and bit line is changed, the current on the conventional redundant bit line may drift away. Therefore, in the conventional technology, the simulation of the current on the general bit line will fail. In the invention, even if the process is changed, the surplus bit line can accurately simulate the current on the general bit line. In short, the unregulated process changes, the operating temperature changes, and the V dd changes. The paper size of this invention applies to the Chinese National Standard (CNS) A4 specification (210 X 297 g t) II -------- 1 I--33V · --- I --- ^ --------- (Please read the precautions on the back before filling out this page) 472255 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7__ V. Description of Invention () Can accurately simulate the voltage on general bit lines. Take an example of a spare memory cell that can provide the same discharge current as a normal memory cell, together with a pattern of capacitive load for the worst-case discharge of the bit line as an example. The voltage drop on the spare bit line with K memory cells is K times the minimum voltage drop of a general bit line. For example, the line 80 shown in FIG. 7 is' the change of the electrical waste of a general memory cell during the discharge process, and the voltage change of the remaining memory cell during the discharge process is shown as line 81, where line 8 1 means that K general memory cells are used as the current source. Because the present invention can linearly respond to voltage changes on general bit lines, and provide accurate voltage simulation, so that timing control for the next stage becomes feasible, which is not possible in the conventional technology . In order to describe the operation of the precharge circuit for simulating voltage changes on general bit lines, the voltage changes on the terminal precharge ', bit line DMYBL1, and word line DMYWL12' are shown in Figure 8. When the voltage on terminal precharge 'becomes low (for example, 0), P MOS controlled by terminal precharg e' (in Fig. 6) is turned on, the voltage on bit line DMYBL 'is Vdd, and N MOS controlled by the character line DMYWL12 'is turned off. Because the endpoint precha "ge 'is charged from a low logic level to a high logic level, P MOS changes from on to off. And after a preset time, N Μ controlled by the word line DMYWL 12' 0 S transitions from off to on, and the voltage on the word line D M YBL 'linearly decreases from Vdd until N M 0 S controlled by word line DMYWL1 2' switches from on to off. At N M 0 In the cycle of S, the paper size of the paper applies to the Chinese National Standard (CNS) A4 specification (2) 0 X 297 mm. N I— II ί n I nnn · mm— I · nnnnn .1 n ^ e * · nnnnnn ((Please read the precautions on the back before filling this page) 472255 Printed by the Consumers Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7_ V. Description of the invention () The cell is in the state of "reading", and when N Μ 0 S When switching from a high logic level (V dd) to a low logic level (0), the voltage on the bit line remains at the voltage value Vd d-△ V until the PMQS controlled by the endpoint p recharge 'is turned off Switch to ON, then the bit line DMYBU is charged from voltage Vdd-△ V to voltage value Vdd The proportional relationship between line 80 and line 81 is linear. For example, in a specific time, the voltage drop of the general memory cell is V dr ο p, and the voltage drop on the remaining memory cell is K times (K Vd "op", so its linear proportional relationship can be applied to memory cells with different processes and different size transistors. When the present invention is used in a word line pulse wave control circuit, it is not necessary in the present invention The time margin necessary in the conventional conventional word line pulse wave control circuit is used. In the conventional conventional word line pulse wave control circuit, in order to obtain a sufficient voltage difference between the bit lines, and in order to have enough Time is required for the writing action, so the pulse width of the character line cannot be too small. Therefore, in the traditional random static memory (SRAM) design, the pulse width of the character line must have a certain extra margin. (Extra margi η) to deal with some of the worst cases. Nonetheless, these extra margins may not fully tolerate all the worst cases (for example, because of bit line process defects) Caused by the time constant change), but this method will definitely cause the period of the memory to be extended, and the above situation will also reduce the yield during mass production. A highly accurate redundant bit line circuit (Figure The remaining memory cell array in 5A6 4 0) can provide a negative feedback to control a character. The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the back Note for this page, please fill in this page) Order --- Line 472255 A7 _B7__ V. Description of the invention () Line pulse width control circuit (control circuit 46 in Fig. 5A), so the same as the rest of the preferred embodiment of the present invention The bit line, together with the working word line pulse width controller, can track electrical activity on general bit lines with high accuracy. And because extra margins can be omitted in the present invention, the word line pulse wave width can be designed to be the narrowest width as required for read / write operations. These word line pulse wave widths can be different because of different The change in bit line activity caused by operating conditions or manufacturing processes changes the word line pulse width. These can make the design of embedded memory cells more flexible in the process of manufacturing these memories. In terms of general or typical processes, it is generally desirable that the memory cells have a short operating cycle without fixed characters. Limits on line pulse widths and avoids extra margins of time that would otherwise have to be added for some worse cases. For the processing of some slower components or some minor defects in the memory cell line, this automatic timing word line pulse wave control circuit can generate a longer word line pulse width to protect Memory cells are protected from failure (fai 丨 u 「e). Therefore-for chip designs that may need to tolerate some additional memory cell operating time, the present invention can have a better yield without having to bother with the character lines The wave width of the wave. ------------- f * tn I mna 1 Order --------- line (Please read the precautions on the back before filling this page) In order to show the use of fcr Jin Ja, households and Mingming, issued a copy of the original but not implemented it is better than its more extraordinary Mingfa is only described in the Ministry of Economic Affairs, the Intellectual Property Office of the Ministry of Industry and Consumer Cooperatives printed around Fan Li specially requested Shen Zhiming to issue a set limit, such as an example copy. Please place the record in the record of Yi Wan Yi Ji, a member of the group who has been listed in 弋, ^^ or the plan to change the load and modify the negative effects. The example of God ’s knowledge and practice is to be true in the Ming dynasty. The dimensions are in accordance with the Chinese National Standard (CNS) A4 (21〇χ297297). 472255 __B7_ 5. After the description of the invention, any modification made to the embodiments of the present invention will not depart from the spirit and scope of the present invention. Therefore, it should be included in the scope of patent application as described below. Printed by the Ministry of Economics and Labor Bureau Consumer Consumption Cooperatives 20 ------------- Mine -------- Order. (Please read the precautions on the back before filling this page) This paper size applies the Chinese National Standard (CNS) A4 (210 X 297)