471046 A7471046 A7
經濟部智慧財產局員工消費合作社印製 發明領域： 本發明係有關於一種半導體元件的製程方法，特別是 有關於一種使用氮電漿脈衝摻雜防止硼穿透閘極介電層Z 方法。 胃g 發明背景： 金氧半（MOS)電晶體的製造對於熟習此技藝者而言乃 是热知的技術。首先提供一具有輕微P型或η型摻雜之單 晶石夕基底。接著電晶體及其他主動元件所在的主動區域藉 由隔離結構加以隔離。隔離結構包括熟知的場氧化結構 (LOCOS)或是淺溝渠隔離（STI)。然後藉由熱氧化法氧化矽 基底在基底上形成一層氧化層’即二氧化矽層，以作為閘 極介電層。之後在閘極介電層上沉積一層複晶矽層，並進 行微影及餘刻步驟形成閘極導電層。隨後ϋ極 雜η型或P型摻質，同時在閘極導電層兩側摻雜高劑量的 π型或ρ型摻質形成源極/汲極區。若摻質為ρ型，則所形 成的電晶體稱為PMOS電晶體。 藉由在複晶矽閘極導電層中摻雜摻質可以有效地降低 . 一 、- 一-一一 其電阻值。為了使閘極導電層的片電阻（sheet ressistance) 降到夠低的程度’例如500 〇hms/sq，必須摻雜足釣的摻 2 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） C請先閱讀背面之注音？事項1 裳·— 尊寫本頁} 訂： --線· 471046 A7 B7 Λ發明說明（ 質。在傳統的離子植入製程中，藉由調整離子植入的能量 來控制摻質的植人深度。然而，傳統的離子植入深度= 約在200埃左右，因此無法獲得更淺的植入深度。一 一—— 而且，在後續的製程步驟中需要使用高溫的埶製程。 例如，在離子植入後通常需要進行^入後回火，藉以活化 植入到閘極導電層與源極/汲極區的^一質。然而，二般較小 尺寸的摻質具有較高的擴散力，且容易擴散到較深又的又深 度。例如’ PMOS電晶體-般常使用棚來摻雜複晶石夕問極 與極區。不幸的是1的高擴散性會在後續的献處 ^ t ^ t is ϋ ^ ^ ^ ^ ^ ^ ^ ^ ^ 晶體的通道區…域二硼穿透到通道區域導致一些不良的效 應’比如增加電子捕陷機率’降低電子電洞的移-動力，使 電晶體的電流衰退’以及增加次臨界（油hreshQid) 等。 因此，當元件尺寸縮小到0.18微米以下時，閘極介電 層的厚度縮至20埃，甚至更薄’因而硼穿透效應愈來愈顯 著，如何防止硼穿透閘極介電層進入到元件的通道區域， 影響到元件運作’改變臨界電壓等電性問題，已成為改善 元件特性之重要的一環。 發明目的及概述： 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------------裝--- (請先閱讀背面之注音？事項寫本頁) . 經濟部智慧財產局員工消費合作社印製 ^1046 A7 B7 五、發明說明（） 鑒於上述之發明背景中，硼穿透閘極介電層進入到通 道區域’影響元件運作，改變元件操作特性等問題，因此 本發明提供一種使用氮電漿脈衝摻雜防止侧穿透閘極介電 層的方法，形成緊密度較高的氮氧化層與氧化層混合作為-間極介電層’可有效地防止硼穿透閘極介電層。 本發明提供一種使用氮電漿脈衝摻雜防止硼穿透閘極 介電層的方法，包括下列步驟。首先提供—半導體基底， 其具有一通道區域。進行一氮電漿脈衝摻雜步驟，在通道 區域之表層中摻雜氮離子。接著選擇性地進行一氣哲火步 驟，以加強氮離子摻雜的效果。然後進行一熱氧化成長步 驟’在半導體基底上形成一閘極介電層。 依照本發明之製造方法所形成之閘極介電層，由於其 摻雜有氮離子，形成含有氮氧化層的薄層，對於後續在閘 極介電層上形成之硼摻雜複晶矽層中的硼離子可以有效地 提供阻隔效果，防止硼穿透閘極介電及，避免電晶體的臨 界電壓受到硼穿透的影響。 經濟部智慧財產局員工消費合作社印製 圖式簡單說明： 本發明的較佳實施例將於往後之說明文字中輔以下列 4 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ^α〇46 Α7FIELD OF THE INVENTION The present invention relates to a method for manufacturing semiconductor devices, and more particularly, to a method for preventing boron from penetrating the gate dielectric layer Z by using nitrogen plasma pulse doping. Stomach g Background of the Invention: The manufacture of metal oxide semiconductor (MOS) transistors is a well-known technology for those skilled in the art. First, a single crystal substrate with a slight P-type or n-type doping is provided. The active area where the transistor and other active components are located is then isolated by an isolation structure. Isolation structures include the well-known field oxide structure (LOCOS) or shallow trench isolation (STI). Then, the silicon substrate is oxidized by thermal oxidation to form an oxide layer on the substrate, that is, a silicon dioxide layer, as a gate dielectric layer. A polycrystalline silicon layer is then deposited on the gate dielectric layer, and lithography and remaining steps are performed to form a gate conductive layer. Subsequently, a ϋ-type doped n-type or P-type dopant is used, and a high dose of a π-type or p-type dopant is doped on both sides of the gate conductive layer to form a source / drain region. If the dopant is p-type, the transistor formed is called a PMOS transistor. By doping dopants in the polycrystalline silicon gate conductive layer, the resistance can be effectively reduced. In order to reduce the sheet resistance (sheet ressistance) of the conductive layer of the gate electrode to a sufficiently low level, for example, 500 hms / sq, it must be doped with 2% of the paper size. This paper standard applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) C Please read the phonetic notation on the back first? Matter 1— · Write this page} Order: --line · 471046 A7 B7 Λ Description of the invention (mass. In the traditional ion implantation process, the implantation depth is controlled by adjusting the energy of ion implantation. However, traditional ion implantation depth = about 200 angstroms, so shallower implantation depths cannot be obtained. One by one-and, in the subsequent process steps, a high-temperature hafnium process is required. For example, in ion implantation Post-entry tempering is usually required after activation to activate the primary material implanted into the gate conductive layer and the source / drain region. However, dopants of a smaller size have a higher diffusion force, and It is easy to diffuse to a deeper and deeper depth. For example, 'PMOS transistors are often used to dope the interstellar pole and pole region. Unfortunately, the high diffusivity of 1 will be in the subsequent contribution ^ t ^ t is ϋ ^ ^ ^ ^ ^ ^ ^ ^ ^ The channel region of the crystal ... The penetration of the domain diboron into the channel region causes some undesirable effects such as increasing the probability of trapping electrons, reducing the mobility of the electron hole, and making the transistor Current decay 'and increasing subcritical (oil hreshQid) etc. So When the device size is reduced to less than 0.18 microns, the thickness of the gate dielectric layer is reduced to 20 angstroms or even thinner. Therefore, the boron penetration effect becomes more and more significant. How to prevent boron from penetrating the gate dielectric layer into the device? The channel area, which affects the operation of the component, changes electrical characteristics such as the threshold voltage. It has become an important part to improve the characteristics of the component. Purpose and summary of the invention: This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -------------- Install --- (Please read the phonetic on the back? Matters write this page). Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ^ 1046 A7 B7 V. Description of Invention () In view of the above background of the invention, boron penetrates the gate dielectric layer and enters the channel region, which affects the operation of the device and changes the operating characteristics of the device. Therefore, the present invention provides a nitrogen plasma pulse doping to prevent side penetration of the gate. The method of forming a polar dielectric layer, forming a dense nitrogen oxide layer mixed with the oxide layer as an inter-electrode dielectric layer, can effectively prevent boron from penetrating the gate dielectric layer. The invention provides a pulse using a nitrogen plasma. Doping prevention The method for penetrating the gate dielectric layer includes the following steps. First, a semiconductor substrate is provided, which has a channel region. A nitrogen plasma pulse doping step is performed to dope nitrogen ions into the surface layer of the channel region. An air-fire step is performed to enhance the effect of nitrogen ion doping. Then, a thermal oxidation growth step is performed to form a gate dielectric layer on the semiconductor substrate. The gate dielectric layer formed according to the manufacturing method of the present invention Because it is doped with nitrogen ions, a thin layer containing a nitrogen oxide layer is formed, which can effectively provide a barrier effect for boron ions in a boron-doped polycrystalline silicon layer formed on the gate dielectric layer later to prevent boron penetration Dielectric through the gate and to prevent the critical voltage of the transistor from being affected by boron penetration. Brief description of the printed drawings of the employees ’cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs: The preferred embodiment of the present invention will be supplemented by the following explanatory texts. Mm) ^ α〇46 Α7
五、發明說明（） 圖形做更詳細的闡述，其中： 第1A -1 D圖為本發明之一較佳實施例之製程剖面圖； 第2圖為氮電漿脈衝摻雜所使用之反應室之結構示意 圖。 圖號對照說明： 100 半 導 體 基 底 102 隔 離 結 構 104 氮 電 漿 脈 衝摻雜 106 摻 雜 氮 離 子 108 熱 氧 化 成 長步驟 110 閘 極 介 電 層 120 摻 雜 複 晶石夕層 122 閘 極 間 隙 壁 124 源 極/汲極區 126 通 道 區 域 200 晶 圓 202 下 電 極 204 上 電 極 206 電 漿 208 氮 離 子 (請先閱讀背面之注意事項i寫本頁) --裝 訂· 線· 經濟部智慧財產局員工消費合作社印製 發明詳細說明： 請參照第1A圖，首先提供一半導體基底10 0，比如是 單晶矽基底。接著在基底1〇〇中製作元件隔離結構102， 藉以規劃出元件隔離結構之間電晶體所在位置之主動區 域，因此主動區域包括電晶體中的通道區域。隔離結構包 5 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 471046 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（ 括熟知的場氧化結構（L〇C〇s)或是淺溝渠隔離工） ”月多照第1B圖’接著進行氮電漿脈衝摻雜步驟ι〇4， 利用氮電漿進行脈衝式摻雜，在主動區域（包含通道區域） 之表層中摻雜氮離子106。使用此氮電漿脈衝摻雜與傳統 的離子植入製程相比，可以獲得較淺的摻雜深度，其可達 到50埃甚至更低，使摻雜的氮離子1〇6幾乎完全停留每基 底100的表層，使基底100受到甚少的破壞，此有助於後 續在基底100上形成的閘極介電層與基底1〇〇之間介面的 凡整此外’若僅需在通道區域中掺雜氮離子106，可以 在基底100上覆蓋一層圖案化光阻層（未顯示），只暴露出 通道區域，然後再進行氮電漿脈衝摻雜。 接著將進一步對氮電漿脈衝式摻雜進行說明。請參照 第2圖，其繪示氮電漿脈衝摻雜所使用之反應室的結構示 意圖。反應室主要包括下電極2〇2與上電極2〇4，包含半 導體基底100之晶圓200放置在下電極202上，並且加以 固定。在上、下電極204與2〇2之間通入含氮氣體，例如 氮氣’且氣氣亦可混入負載氣體比如氬氣，通入反應室中。 並且’在上、下電極2〇4與2〇2分別施加正、負電壓，使 含敗氣體解離形成電漿2〇6，同時在電漿2〇6中形成帶正 電的氮離子208。帶正電的氮離子2〇8受到下電極2〇2的 負電吸引而植入到晶圓2〇〇中。在此較佳實施例中，使用 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公爱） -------------裝----l·---訂· (請先閱讀背面之注意事項寫本頁) 471046V. Explanation of the invention () The graphics are explained in more detail, in which: Figures 1A-1D are cross-sectional views of the process of a preferred embodiment of the present invention; Figure 2 is a reaction chamber used by nitrogen plasma pulse doping The structure diagram. Comparative illustration of drawing numbers: 100 semiconductor substrate 102 isolation structure 104 nitrogen plasma pulse doping 106 doping nitrogen ions 108 thermal oxidation growth step 110 gate dielectric layer 120 doped polycrystalline stone layer 122 gate spacer 124 source / Drain region 126 Channel region 200 Wafer 202 Lower electrode 204 Upper electrode 206 Plasma 208 Nitrogen ion (please read the notes on the back first to write this page) Detailed description of the manufacturing method: Please refer to FIG. 1A, first provide a semiconductor substrate 100, such as a single crystal silicon substrate. Then, an element isolation structure 102 is fabricated in the substrate 100, so as to plan an active region where the transistor is located between the element isolation structures, so the active region includes a channel region in the transistor. Isolation structure package 5 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 471046 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (including the well-known field oxidation structure (L. C0s) or shallow trench isolation workers) "Monthly according to Figure 1B 'followed by the nitrogen plasma pulse doping step ι04, using the nitrogen plasma for pulse doping, in the active area (including the channel area) The surface layer is doped with nitrogen ions 106. Compared with the traditional ion implantation process, using this nitrogen plasma pulse doping can obtain a shallower doping depth, which can reach 50 angstroms or even lower, so that the doped nitrogen The ions 106 stay almost completely on the surface of each substrate 100, causing little damage to the substrate 100. This helps the interface between the gate dielectric layer formed on the substrate 100 and the substrate 100. 'If only the nitrogen ions 106 need to be doped in the channel region, a patterned photoresist layer (not shown) can be covered on the substrate 100, only the channel region is exposed, and then nitrogen plasma pulse doping is performed. Nitrogen Plasma The punch doping is described. Please refer to FIG. 2 for a schematic diagram of a reaction chamber used for nitrogen plasma pulse doping. The reaction chamber mainly includes a lower electrode 20 and an upper electrode 204, including a semiconductor substrate. A wafer 200 of 100 is placed on the lower electrode 202 and fixed. A nitrogen-containing gas, such as nitrogen, is passed between the upper and lower electrodes 204 and 202, and a gas can also be mixed into a load gas such as argon. In the reaction chamber, and 'positive and negative voltages are applied to the upper and lower electrodes 204 and 202, respectively, so that the gas containing gas is dissociated to form a plasma 206, and a positively charged plasma is formed in the plasma 206 Nitrogen ions 208. The positively charged nitrogen ions 208 are implanted into the wafer 2000 by the negative charge of the lower electrode 002. In this preferred embodiment, the Chinese paper standard applies to this paper size ( CNS) A4 specification (21〇X 297 public love) ------------- install ---- l · --- order · (Please read the precautions on the back to write this page) 471046
經濟部智慧財產局員工消費合作社印製 脈衝式電流施加於下電極202，此氮電漿脈衝摻雜所使用 之製程參數範圍，其中摻雜所使用之能量約為 200-l0000eV，且在晶圓200中所摻雜的劑量（d〇sag勾約為 1E14-1E17/Cm2’並且適當配合其他的製程參數，如通入氣 體的種類、壓力與流速，電極上所施加的偏壓大小，以及 上、下電極之間的距離與摻雜時間等，則可以獲得較佳的 摻雜效果。 在氮電漿脈衝摻雜之後，可以選擇性地進行氮回火步 驟，以強化氮離子的摻雜效果。在溫度約8〇〇_li〇〇cc下， 於反應室中通入純氮，即氮氣的純度為1〇〇%，進行回火製 程，使植入的氮離子106活化，並且修補摻雜時破壞的晶 圓表面。 請參照第1C圖，然後進行—熱氧化成長步驟⑽，利 用傳統的熱氧化製程，例如乾式熱氧化(dry oxidation)，氧 化矽基底100,在基底100上長出一層閘極介電層11〇，由 於之前已在基底100表層中摻雜有氮離子1〇6，因此所形 成的閘極介電層110為上層是氧化層且下層是氮氧化層的 漸層混合結構’並且同時可以修補之前因氮離子摻雜所造 成的破壞。若執行氮回火步驟則可形成由上而下之氧化 層、氮氧化層與氮化層之漸層混合結構。由於下層的氮氧 化層與氮化層結構較氧化層更為緊密，因此I以^效地阻 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------------裝.—l·—訂· c請先閱讀背面之注咅？事項0寫本頁) 471046 A7 B7 五 經濟部智慧財產局員工消費合作社印製 、發明説明（ 擋蝴穿透此閘極介電層〇。 請參照第1D圖，接著進行後續的製程，完成pM〇s電 晶體。例如’在通道區域126上製作硼摻雜複晶矽層以作 為閘極導電層120，在閘極導電層120側壁製作閘極間隙 壁122，然後再製作源極/汲極區124。由於此皆為熟習此 技藝者所熟知之技術，因此不再贅述。此外，本發明之較 佳實施例亦可應用至其他與PM〇S電晶體相關的元件，例 如是互補式金氧半（CMOS)電晶體。 綜上所述’本發明揭露一種使用氮電漿脈衝摻雜防止 爛穿透閘極介電層的方法，利用氮電漿脈衝摻雜可以在某 底表面極淺的地方摻雜氮離子，減少基底受到破壞，保持 基底與閘極介電層之間介面的完整’並且所形成的閘極介 電層含有氮氧化物或氮化物，形成緊密的結構，可以有f 地防止硼穿透效應’避免硼穿透閘極介電層到通道區域， 影響電晶體的電性。 如熟悉此技術之人員所瞭解的’以上所述僅為本發明 之較佳實施例而已’並非用以限定本發明之申請專利範 圍，凡其它未脫離本發明所揭不之精神下所完成之等六文改 變或修飾，均應包含在下述之申請專利範圍内。 本紙張尺度適用中國國家標準（CNS ) M規格（210X297公釐） (請先閎讀背面之注意事項再本頁} -裝·The consumer property cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed a pulsed current applied to the lower electrode 202. The process parameter range used for this nitrogen plasma pulse doping, wherein the energy used for doping is about 200-10000eV, and it is on the wafer. Doped dose in 200 (d0sag is about 1E14-1E17 / Cm2 'and it is appropriately matched with other process parameters, such as the type of gas, pressure and flow rate, the amount of bias applied to the electrode, and , The distance between the lower electrode and the doping time, etc., can obtain a better doping effect. After the nitrogen plasma pulse doping, the nitrogen tempering step can be selectively performed to enhance the doping effect of nitrogen ions. At a temperature of about 800-1000 cc, pure nitrogen was passed through the reaction chamber, that is, the purity of the nitrogen was 100%, and a tempering process was performed to activate the implanted nitrogen ions 106 and repair the doping. The surface of the wafer damaged at the time of failure. Please refer to FIG. 1C, and then proceed to the step of thermal oxidation growth, using a traditional thermal oxidation process, such as dry oxidation, to oxidize the silicon substrate 100, and grow on the substrate 100. Gate Layer 110, since the surface layer of the substrate 100 has been doped with nitrogen ions 106 before, the gate dielectric layer 110 formed is a gradient mixed structure with the upper layer being an oxide layer and the lower layer being an oxynitride layer. It can repair the damage caused by the nitrogen ion doping. If the nitrogen tempering step is performed, a mixed structure of the oxide layer, the oxynitride layer, and the gradual mixed layer of the nitride layer can be formed. Because the lower oxynitride layer and the The structure of the nitrided layer is tighter than that of the oxide layer, so I can effectively prevent the paper size from applying the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ------------- -Install.—l · —Order · c Please read the note on the back? Matters 0 write this page) 471046 A7 B7 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, and the invention description (stop butterfly through this gate Electrical layer 0. Please refer to Figure 1D, and then carry out subsequent processes to complete the pMOS transistor. For example, 'B-doped polycrystalline silicon layer is fabricated on the channel region 126 as the gate conductive layer 120, which is conductive at the gate. A gate spacer 122 is formed on the sidewall of the layer 120, and then a source / drain region 124 is formed. This is a technique well known to those skilled in the art, so it will not be repeated. In addition, the preferred embodiment of the present invention can also be applied to other components related to PMOS transistors, such as complementary metal oxide semiconductor ( In summary, the present invention discloses a method using nitrogen plasma pulse doping to prevent rot from penetrating the gate dielectric layer, and using nitrogen plasma pulse doping can be doped on a very shallow surface. Doped nitrogen ions, reducing damage to the substrate, maintaining the integrity of the interface between the substrate and the gate dielectric layer, and the formed gate dielectric layer contains oxynitride or nitride, forming a compact structure, which can be prevented f Boron penetration effect 'prevents boron from penetrating the gate dielectric layer to the channel area, which affects the electrical properties of the transistor. As understood by those skilled in the art, 'The above description is only a preferred embodiment of the present invention' and is not intended to limit the scope of patent application of the present invention. All other things can be done without departing from the spirit of the present invention. All other six changes or modifications should be included in the scope of patent application described below. This paper size applies to Chinese National Standard (CNS) M specifications (210X297 mm) (Please read the precautions on the back before this page}-Packing ·
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