TW469615B - BGA-type semiconductor device package - Google Patents
BGA-type semiconductor device package Download PDFInfo
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- TW469615B TW469615B TW089114691A TW89114691A TW469615B TW 469615 B TW469615 B TW 469615B TW 089114691 A TW089114691 A TW 089114691A TW 89114691 A TW89114691 A TW 89114691A TW 469615 B TW469615 B TW 469615B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
469615 五、發明說明（l) 所屬拮街領袪 · 本發明係有關於一種「BGA型（球柵陣列型）半導體 裝置封裝」’特別是有關於一種具有密實結構體且設置有 —形狀簡單而能將半導體元件所產生之熱加以散發之散熱 片的「BGA型半導體裝置封裝」。 發明之背f 到目則為止之習知技術，—般係在將内藏一個或者複 數個QFP (quad fiat package,四方扁平封裝）、PGA (pin g ‘ array,針腳柵陣列）、bga (ball grid array，球 拇阵列型封裝）等之半導體IC等單晶片封裝（singU chip Package)或者是混合式（hybrid)IC、MCM (multi chip 〇dU t ’多晶片模組）等之多晶片（mu 111一ch i P )之I C零件 力口以安裝^之半導體封裝中’將這些I c零件安裝在印刷基板 同時’將散熱用散熱片（heat s ink)設置在印刷基板 的反面上。 在由將此散熱用散熱片設置在半導體1(：等封裝上，則 化些半導體晶片上所產生並儲蓄的熱就能夠有效地散 士 乂防止因半導體Ic等之發熱而產生錯誤的動作，同時 p ^抑制半導體的劣質化並延長半導體的使用壽命。 八翻+此如圖3所示係為根據日本特開平1 0 — 24 770 2號 之BGA细所^己載之BGA型半導體封裝。其在設置有散熱片27 導體元钍半導體封裝内，於相當於配置在樹脂基板1 3之半 1 4之位置之樹脂基板1 3之下侧處，將鋼、銘、銅469615 V. Description of the invention (l) Affiliated street collar · The present invention relates to a "BGA (Ball Grid Array) Semiconductor Device Package" ', and more particularly to a compact structure with simple structure and simple structure. "BGA-type semiconductor device package" is a heat sink that can dissipate heat generated by semiconductor elements. The back of the invention is the known technology up to the point of view, which is generally built with one or more QFP (quad fiat package), PGA (pin g 'array, pin grid array), bga (ball grid array (ball grid array type package) and other semiconductor IC and other single-chip packages (singU chip Package) or hybrid (hybrid) IC, MCM (multi chip 〇dU t 'multi-chip module) and many chips (mu 111-ch i P) in the semiconductor package to install the semiconductor package 'install these I c parts on the printed circuit board at the same time' the heat radiating fins (heat ink) are arranged on the reverse side of the printed circuit board. By disposing this heat sink for semiconductor 1 (: and other packages), the heat generated and stored on these semiconductor wafers can be efficiently dissipated, preventing erroneous operation due to the heat generated by the semiconductor IC and the like. p ^ suppresses the deterioration of semiconductors and prolongs the service life of semiconductors. Eight turns + This is shown in Figure 3 is a BGA-type semiconductor package that has been loaded according to the BGA details of Japanese Patent Application Laid-Open No. 10-24 770 2. It In the semiconductor package provided with the heat sink 27 conductor element, the steel, copper, and copper are placed on the lower side of the resin substrate 13 corresponding to the position of half 14 of the resin substrate 13.
6 9 6 1 5 五、發明說明（2) 一· 鶴合金、钴等之「熱之良導體」金屬材料當做散熱片而 加以連接。再者，透過在樹脂模丨5上強制散熱之薄膜型之 散熱塊C散熱片）2 7和高導熱性樹脂板而配置，而加強將儲 蓄熱於樹脂模1 5内的半導體元件1 4等之熱量加以散熱。 又，如圖4所示係為根據曰本特開平丨丨—8 75丨〇號公 報中所s己載之另一種設置有散熱片型半導體封裝。 其在印刷線路基板23上與半導體元件14電性連接之球形端 子11係與印刷線路基板23相連接，而且將半導體元件1 4加 以包裹所形成的保護基板上黏著之銅上鍵上一層鎳之蓋板 (cover pUte)21係以將全體包圍的形式而設置。該蓋板 21之兩端係以做為接地（gr〇und)端子24而與印刷線路基板 23相連接，同時該蓋板2丨之上侧黏著並配置有薄膜型之散 熱塊（散熱片）27，而其兩端與蓋板21之兩端對置之部位之 接地端子24係以螺桿29而加以固定。 如以上所述，到目前為止之習知技術，例如在BGA型 等之半導體封裝内，在安裝這種半導體元件之構造體當 中，半導體元件及其周圍附近會蓄積熱量，這是半導體元 件、特別是超大型積體電路（LSI )晶片等之半導體元件會 產生誤動作的主要原因，因此，在進行這種半導體元件之 封裝當中，這種問題便成為不得不極力防止之重要課題。 然而，由上述公報之發明案件中之圖3及圖4可以瞭解 到’雖然用來做為散熱片之構件具有密實（c〇mpact)之構 造體，但是為了使到目前為止之習知技術能夠使進行封裝 而有效地放熱，則一方面在發熱、儲熱部位的附近周邊設6 9 6 1 5 V. Description of the invention (2) I. “Good Conductor” metal materials such as crane alloy and cobalt are connected as heat sinks. Furthermore, it is arranged through a thin film-type heat sink (C heat sink) 2 7 and a highly thermally conductive resin plate that are forced to dissipate heat on the resin mold 5, and the semiconductor elements 1 4 and the like that store heat in the resin mold 15 are strengthened. The heat is dissipated. In addition, as shown in FIG. 4, it is another heat sink type semiconductor package provided according to Japanese Patent Laid-Open Publication No. 丨 丨 -875 丨 〇. The spherical terminal 11 which is electrically connected to the semiconductor element 14 on the printed circuit board 23 is connected to the printed circuit board 23, and the copper element bonded to the protective substrate formed by wrapping the semiconductor element 14 is coated with a layer of nickel. A cover pUte 21 is provided so as to surround the entire body. The two ends of the cover plate 21 are connected to the printed circuit board 23 as ground terminals 24, and the upper side of the cover plate 2 is provided with a film-type heat sink (heat sink). 27, and the ground terminal 24 at a position where the two ends thereof are opposite to the two ends of the cover plate 21 is fixed by a screw 29. As described above, the conventional technology so far, for example, in a semiconductor package such as a BGA type, in a structure in which such a semiconductor element is mounted, heat is accumulated in the semiconductor element and its surroundings. This is a semiconductor element, particularly This is a major cause of malfunction of semiconductor devices such as ultra-large integrated circuit (LSI) wafers. Therefore, in packaging such semiconductor devices, such problems have become an important issue that must be prevented as much as possible. However, it can be understood from FIG. 3 and FIG. 4 of the invention case of the above-mentioned publication that 'Although the component used as a heat sink has a compact structure, in order to make the conventional technology In order to effectively radiate heat by encapsulation,
第5頁 469 61 5 、發明說明（3) 計多個散熱面 構造就成為不 散熱面·的 ，一方面設計採用每單位面積多個 可欠缺的措施。 因此 構件中， 計。同時 其困難之 於是 係為散熱 屬絕緣性 而在這種 對「熱傳 片構件27 意。 又， 係為散熱 埋入保護 熱於透過 良導體」 層而傳導 構件27。 因此 印刷電路 相連接， 處相通。 ，由 設置 ，由 處。 ，在 片構 ，其 封裝 導速 每單 上述之圖3及圓4可知，用來做為散熱片2?之 具有翼片（f i η )型之散熱塊係常見之— 圖中可以很明顯地看出，使該封裝小型化又有 圖3所不之例子中，兮勒勒+士 φ 4散熱之主要因應對策 :27之设置。不過’通常此散熱片構件”因 …傳導性比較低，且設置在樹脂模丨5上。因 中，為了散熱，這種樹脂模15之熱傳導構 率」起了決定性的作用，而顯著地降低散埶 位時間的散熱效果，因此仍然未能令人滿… 在圖4所示之例子中，該散熱之主要因應對策亦 片構件27之設置。由此構件之作㈣做 基板内之半導體元件U之「熱傳遞路徑」，=二 保護基板上側表面之絕緣性黏著層之具有「埶 之鋼金屬系列材質之蓋板21，並於其上透過 且散熱於同樣屬於銅金屬系列材質之翼型散熱片 ，藉由此散熱片構件27之設置，該接地端子 基板23相連接，且因藉螺桿29而與散熱片構^ 經由蓋板21之「熱傳遞路徑」即在散熱片構件”Page 5 469 61 5. Description of the invention (3) Counting multiple cooling surfaces The structure becomes a non-radiating surface. On the one hand, multiple inadequate measures per unit area are designed. Therefore, the component counts. At the same time, the difficulty lies in the fact that the heat-dissipating material is insulating, and in this sense, the heat-conducting sheet member 27 is embedded. The heat-conducting member 27 is embedded to protect the heat from passing through a good conductor. Therefore, the printed circuits are connected to each other. , Set by, place by. In the chip structure, the package guide speed of each of the above-mentioned Figures 3 and 4 can be seen, the heat sink with a fin (fi η) type used as the heat sink 2? Is common-it can be clearly seen in the figure It can be seen that in the case of miniaturizing the package and in the example shown in Fig. 3, the main reason for the heat dissipation of Xiler + Shi 4 is the setting of 27. However, 'usually this heat sink member' has a relatively low conductivity and is placed on the resin mold 5. Because of this, the thermal conductivity of this resin mold 15 plays a decisive role in order to dissipate heat, which significantly reduces it. The heat dissipation effect of the dissipating bit time is still not satisfactory ... In the example shown in FIG. 4, the main reason for this heat dissipation is the arrangement of the sheet member 27. The work of this component is used to make the "heat transfer path" of the semiconductor element U in the substrate, = the cover plate 21 of the "steel steel metal series material" which protects the insulating adhesive layer on the upper surface of the substrate, and transmits therethrough And the heat is radiated from the wing-type heat sink, which also belongs to the copper metal series material. With the arrangement of the heat sink member 27, the ground terminal substrate 23 is connected, and is connected to the heat sink structure by the screw 29. The heat transfer path "is in the heat sink member"
/16 9 61 5 五 、發明說明（4) 依此’的確’因為透過黏著層蓋板21而與位於其 之散熱片構件27處相通，可以說，我 於其上側 進其散熱效果。 我們預期能多多少少增 然而，不論是在上述公報之舉例中，抑 之習知技術之設置有散熱片構件之车道 :』曰則為止 設置有做為散熱構件之散熱片構件和BGA型式 =然該 體元件之發熱及儲熱部位之「熱傳遞路徑+導 散熱片構件做為有效地利用之構造體，但是， ^將 是仍然還沒有令人十分滿意的半導體封褒。 τ、的狀況 辟明之概述 因此’本發明的目的在提供一机 Τ.ΓΑ ^ ^ W 44 ^ # 種fi又置有散熱片構件之 BGA I +導體裂置封裝’其做為加以配置之散熱片構件， 係為一般所使用者，特別是到目前為止之習知技術。例 如，不使用具有多數翼片（多葉狀葉片）（fin)之散熱塊 (Mock)，而是將封裝儘可能密實（c〇mpact)化之構造， 其不但結構簡單，而且在進行封裝時能夠有效地將熱量散 發至印刷電路基板（mother board)上。 由以上所針對上述問題本發明人銳意進行研究之 結果’使用由「熱之良導體」所構成之簡單的平板狀散熱 片構件，且特別著眼在「熱傳遞路徑」，直接地、比較有 效地找出在進行封裝時能夠使熱量往其下方之印刷電路基 板傳遞，以提高「除熱效率」來完成本發明。 亦即，為達成解决上述問題，本發明提供一種在一半/ 16 9 61 5 V. Explanation of the invention (4) According to this, ‘really’ because it communicates with the heat sink member 27 located there through the adhesive layer cover 21, it can be said that I have the heat dissipation effect on the upper side. We expect to increase more or less. However, no matter in the example of the above-mentioned bulletin, the conventional technology has a lane with a fin member: 『The fin member and the BGA type as the radiating member are set up until the rule = Of course, the "heat transfer path + heat sink member of the heat generating and heat storing part of the body element is used as a effectively used structure, but there will still be no satisfactory semiconductor package. Τ, the situation A clear overview Therefore, the object of the present invention is to provide a machine T. ΓΑ ^ ^ W 44 ^ # BGA I + conductor split package with a heat sink member and a heat sink member configured as a heat sink member. It is generally used, especially the conventional technology so far. For example, instead of using a heat sink (Mock) with a majority of fins (multi-lobed blades) (fin), the package is as dense as possible (c. mpact) structure, which is not only simple in structure, but also can effectively dissipate heat to the printed circuit board (mother board) during packaging. From the above, the present inventors earnestly research Result 'Using a simple flat plate-shaped heat sink member composed of a "good heat conductor", with a special focus on the "heat transfer path", it is possible to directly and more effectively find out the heat that can be transferred below the package. The printed circuit board is transferred to improve the "heat removal efficiency" to complete the present invention. That is, in order to achieve the above-mentioned problem, the present invention provides a
第7頁 469615 五、發明說明（5) ' ^— 導體晶片上設置有一散熱片構件之「BGa型 置封 裝」，此「BGA型半導體裝置封裝」具有下 (1)在平坦化之BGA基板上將半導體晶片加以埋設，且在 此平坦化之BGA基板上，例如，以密封的方造簡 單之平板狀散熱片構件。 C2)在上述平坦化之BGA基板上之多個處所配置「貫穿 孔」，而且，至少與前述之散熱片構件成為一體且至少 與此散熱片構件同樣構件所構成之針腳係嵌入在這此貫穿 孔處，且將此散熱片構件密封在BGA基板上' 一 (3)這些嵌入於前述「貫穿孔」之針腳係以由前述BGA基 板伸出之方式而嵌入者。 藉此’依據本發明之BGA型半導體裝置封裝係透過由 BGA基板伸出之針腳很容易地配合印刷電路基板上之位置 而加以安裝。而且，因為散熱片為一散熱性的簡單結構之 構件’且發熱、儲熱之處所均加以密封，因此，與習知者 相比，其散熱面之「熱傳遞效率」有顯著地提高。同時， 為了使嵌入在此發熱、儲熱之處所所設置之「貫穿孔」之 針腳與散熱片構件結合在一起’使其成為「熱傳遞路 徑」，在進行封裝時’就會將由半導體晶片在印刷電路基 板上所產生之熱有效地進行熱傳遞，並提高其散熱效率。 复立例之詳細説明 以下參考圖卜圖4並依照本發明所設置之散熱片構件 就BGA型半導裝置封裝之實施型態進一步加以說明。Page 7 469615 V. Description of the invention (5) '^ — A "BGa-type package" with a heat sink member provided on the conductor wafer. This "BGA-type semiconductor device package" has the following (1) on a flattened BGA substrate A semiconductor wafer is buried, and a simple flat plate-shaped heat sink member is formed in a sealed manner on the planarized BGA substrate, for example. C2) "through-holes" are arranged in a plurality of places on the flattened BGA substrate, and at least the pins that are integrated with the above-mentioned heat sink member and at least the same member as the heat sink member are embedded here And the heat sink member is sealed on the BGA substrate. One (3) These pins embedded in the aforementioned "through-holes" are embedded in a manner protruding from the BGA substrate. With this, the BGA type semiconductor device package according to the present invention can be easily mounted by fitting the position on the printed circuit board through the pins protruding from the BGA substrate. Furthermore, since the heat sink is a member of a simple structure with heat dissipation properties, and the place where heat and heat are stored is sealed, the "heat transfer efficiency" of the heat dissipation surface is significantly improved compared with the conventional one. At the same time, in order to integrate the "through-hole" pins and heat sink members provided in this place where heat is generated and stored, it will become a "heat transfer path". The heat generated on the printed circuit board efficiently conducts heat transfer and improves its heat dissipation efficiency. Detailed description of the compound example The following describes the implementation form of the BGA type semiconductor device package with reference to FIG. 4 and a heat sink member provided in accordance with the present invention.
-6 9 615 五、 發明說明（6) 接 著參 照 圖 2，如上述之本發明中，針腳5b較佳的是 與 散 熱 片構件2 - '體成形。藉此，此針腳5b就成為從散熱 片 構 件2往BGA 型 基板1之下側方向的「熱傳遞路徑」。再 者 由 於嵌 入 於 貫穿孔5 a中’使得散熱片構件2和BGA型 基 板 1 成為 密 封 的支持體。又，這些貫穿孔5係設置於埋 入 在BGA型基板 1中發熱源之半導體晶片4之周邊附近。 據 此， 由 半 導體晶片4所產生之熱量係由散熱片構件2 之 表 面 散發 出 去 而被辞除，同時，在本發明中，藉由這些 多 數 個 針腳5b 所 構成之「熱傳遞路徑」而將熱量傳遞出 去 j 例 如， 往 底 部之母板（mother board)之熱傳遞產生了 去 除 熱 量的 效 果 0 伸 同 時， 如 圖 2所示’在本發明中’此針腳5b由bGA基板 出 ) 較佳 的 是 ’此伸出部分之尖端係以比設置於該BGA 基 板 之 下側 面 之 錫球之厚度稍小之長度而埋設。 例 又 ，將 依 昭 本發明之BG A型半導體裝置封裝安裝在， 如 印 刷電 路 基 板（以下也有僅寫成「母板」者）時，藉回 焊（ref low) 將 上 述錫球3炼接在此母板上，同時，此針腳 之 尖 端 亦以 焊 錫 加以固定。 時 同 時， 藉 由 此針腳5b之伸出，在其安裝而進行錫焊 就 可以 維 持 有效地防止在傳統上易於產生之锡球發生 朋 塌 t 因而 就 能 顯著地減低此在進行回焊時由於錫球之崩 塌 所 產 生之 不 良 品。 圖 又 ，在 本 發 明中，於BGA基板上做貫穿孔5a時（參照 1) ϊ 最好 是 IIJ· 做 I 多數個。而且，並且該貫穿孔5 a之個數最 ______— Η-6 9 615 V. Description of the invention (6) With reference to FIG. 2, as in the above-mentioned invention, the pin 5b is preferably formed with the heat sink sheet member 2-'. As a result, this pin 5b becomes a "heat transfer path" from the heat sink member 2 to the lower side of the BGA type substrate 1. Furthermore, since it is embedded in the through hole 5a ', the heat sink member 2 and the BGA-type base plate 1 become a sealed support. These through holes 5 are provided near the periphery of the semiconductor wafer 4 embedded in the heat source in the BGA type substrate 1. According to this, the heat generated by the semiconductor wafer 4 is dissipated from the surface of the heat sink member 2 and is removed. At the same time, in the present invention, the "heat transfer path" formed by the plurality of pins 5b is used to remove the heat. The heat is transferred out. For example, the heat transfer to the mother board at the bottom has the effect of removing heat. At the same time, as shown in FIG. 2 (in the present invention, this pin 5b is from the bGA substrate). Yes' The tip of this protruding part is buried with a length slightly smaller than the thickness of the solder ball provided on the lower side of the BGA substrate. For example, when the BG A-type semiconductor device package according to the present invention is mounted on a printed circuit board (hereinafter also referred to as a "mother board"), the solder balls 3 are re-bonded by ref low (ref low). On this motherboard, the tip of this pin is also fixed with solder. At the same time, by extending the pin 5b, soldering can be maintained during its installation to effectively prevent the traditionally easy-to-produce solder balls from collapsing, so that this can be significantly reduced during reflow. Defective products produced by the collapse of solder balls. In the present invention, when the through holes 5a are made in the BGA substrate (refer to 1), it is preferable that the number of IJ is made as many as possible. Moreover, the number of the through holes 5 a is the most ______— Η
4 6 9 61 5 五、發明說明（7) 好是能夠平均分佈且圍繞半導體晶片4之周邊部分，並且_ 在不妨礙半導體晶片4的條件下至少4個以上，更佳的是設 置6個以上較為恰當。 此貫穿孔5a ’已如上述’係嵌入針腳”中。藉由此針 腳5b，為了使散熱片構件在BGA基板上緊密結合，S雖至少 兩個即可達到此目的’但在本發明中，至少個可使其 能更安定而緊密地結合在一起。 然而，做此多數個貫穿孔5a之目的係為了嵌入此處之 針腳5b，且已如前述，亦成為將熱量去除之「埶 徑」。 ，'、、 ，此，在本發明令’其個數最好是有能 圍繞半導體晶片4之周邊部分，並且Α τ , 的條件下至少設置4個以上較為恰當在不妨礙半導體“4 ’做為使用在本發明之散熱片構件，如以上所示， 匕月1適當地使用構造簡單且平板狀之散熱片構件結構。 在此’於本發明中，構造簡單者’特別是考量高放埶 =造因和圖4所示之多葉片翼型謂 =者::以為…位面積的散熱面更大，使用例如 如以上所述，圖3和圖4所示之散熱片構件之設置和本 發明中之散熱片構件之設置加以比較，由本發明之圖2可 以明瞭’將會產生熱源之半導體晶片4埋入基板上，雖然 ^直接與散熱片構件2緊密結合的情況相比，由圓3和圖4 可以明瞭，在傳統的散熱片構件27中，皆直接和熱源直接4 6 9 61 5 V. Description of the invention (7) It is good to be able to evenly distribute and surround the peripheral part of the semiconductor wafer 4, and _ at least 4 or more, and more preferably 6 or more More appropriate. This through hole 5a is 'embedded in a pin as described above'. With this pin 5b, in order to closely bond the heat sink member on the BGA substrate, at least two S can achieve this purpose, but in the present invention, At least one can make it more stable and tightly bound together. However, the purpose of making most of the through holes 5a is to insert the pins 5b here, and as mentioned above, it has also become the "diameter" for removing heat. . ",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, toto ,,,-been allowed to surround the semiconductor wafer 4 In order to use the heat sink member of the present invention, as shown above, Dagger 1 appropriately uses a flat heat sink member structure having a simple structure. Here, in the present invention, a person with a simple structure is particularly considered for high radiation. = Cause and the multi-blade airfoil shown in FIG. 4 ==: It is assumed that the heat dissipation surface of the bit area is larger. For example, as described above, the arrangement and cost of the heat sink member shown in FIG. 3 and FIG. 4 are used. Comparing the arrangement of the heat sink member in the invention, it can be understood from FIG. 2 of the present invention that the semiconductor wafer 4 that will generate a heat source is embedded in the substrate, although ^ is directly compared with the case where the heat sink member 2 is closely combined, the circle 3 It can be seen from FIG. 4 that in the conventional heat sink member 27, both
第10頁 ΙΜΙ 4 69 61 5 五、發明說明（8) 接觸而設置’但报清楚的是，一般均是間接地透過媒介物 而設置者。 又’從將往埋入有半導體元件之基板之方向之散熱做 為目的之熱傳遞策略之觀點看來，本發明之特徵係為，在 基板上之發熱源之半導體晶片之周邊所設置之多數個貫穿 孔内嵌入針腳’特別是，該底部方向具有大散熱面，例 如’設置有往母板方向之「熱傳遞路徑」。根據這些不同 點’藉由將散熱改變為目的之熱的構造特性所產生之效果 已如前述。 相比，雖然是 卻是將此「板 之BGA型基板 來將「板月狀 加以去除。 且嵌入於多數 成為「熱傳遞 大散熱面也與 熱量傳遞出去 從以上所述，根據本發明之板片狀散熱 sink)與習知之多葉片之翼#(fin)型散熱塊 以明顯的簡單形狀而含較小之散熱面積，但 片狀散熱片」緊密結合在埋入有半導體晶片 上之發熱、儲熱之處所而設置。藉此，以用 散熱片」中之散熱面上之熱量有效地散發並 同時，設置於此基板之發熱、儲熱處所 個貫穿孔的多數個針腳與散熱片構件結合且 路徑」’而此針腳之尖端在安裝時，即使有 封裝底部的印刷電路基板相連接而有效地將 並加以去除。 又，此針腳係設計成由BGA型半導體裝置封裝 基板伸出，藉此，在封裝時就能很容易地配合印 板上之位置，而且由於此伸出部分成為支持物，— 技術，藉由將錫球壓壞即可顯著地減低不良品，Page 10 ΙΜΙ 4 69 61 5 V. Description of the invention (8) Setting by contact ', but it is clear that it is generally set by indirectly through the medium. From the viewpoint of a heat transfer strategy for the purpose of dissipating heat in the direction of the substrate on which the semiconductor element is embedded, the present invention is characterized in that a majority of the semiconductor wafers are provided around the semiconductor heat source on the substrate. Pins are embedded in each of the through holes. In particular, the bottom direction has a large heat dissipation surface, for example, "a heat transfer path" is provided toward the motherboard. According to these differences, the effect of the structural characteristics of the heat by changing the heat dissipation as the purpose is as described above. Compared to this, the "plate BGA-type substrate is used to remove the" moon shape "of the plate. It is embedded in most of the" large heat transfer surface and heat transfer surface is also transferred out of the heat. From the above, the plate according to the present invention The fin-shaped heat sink (sink) and the conventional multi-blade wing # (fin) type heat sink have a significantly simpler shape and contain a smaller heat dissipation area, but the fin-shaped heat sink is closely combined with the heat generated by the embedded semiconductor wafer. Set for heat storage. In this way, the heat on the heat sink surface in the heat sink "is efficiently dissipated and at the same time, a plurality of pins provided in the through holes of the heat generating and heat storage spaces of this substrate are combined with the heat sink member and the path is" "and this pin When the tip is mounted, even if the printed circuit board at the bottom of the package is connected, it is effectively removed. In addition, this pin is designed to protrude from the BGA-type semiconductor device package substrate, so that it can easily fit the position of the printed board during packaging, and because this protruding portion becomes a support, — technology, by Defective solder balls can significantly reduce defective products,
第12頁 4 69 61 5 圖式簡單說明 圖1為根據本發明中設置有簡單的平板狀散熱片構件之BG'A 型半導體封裝之立體圖。 圖2為根據本發明中設置有散熱片構件之BGA型半導體封裝 之示意斷面圖。 圖3為習知技術中設置有散熱片構件之半導體裝置封裝之 斷面圖。 圖4為習知技術中另一設置有散熱片構件之半導體裝置封 裝之斷面圖。 符號說明 I BGA型基板 2、 27散熱片構件 3、 1 2 錫球 4 LSI半導體晶片 5 a 貫穿孔 5 b 針腳 II 球形端子 13 樹脂基板 1 4半導體元件 15樹脂模 2 0散熱片 21蓋板 2 3、41 印刷配線基板 24 接地端子Page 12 4 69 61 5 Brief Description of Drawings Figure 1 is a perspective view of a BG'A type semiconductor package provided with a simple flat plate-shaped heat sink member according to the present invention. FIG. 2 is a schematic sectional view of a BGA type semiconductor package provided with a heat sink member according to the present invention. Fig. 3 is a cross-sectional view of a semiconductor device package provided with a heat sink member in a conventional technology. FIG. 4 is a cross-sectional view of another conventional semiconductor device package provided with a heat sink member. DESCRIPTION OF SYMBOLS I BGA substrate 2, 27 heat sink member 3, 1 2 solder ball 4 LSI semiconductor wafer 5 a through hole 5 b pin II ball terminal 13 resin substrate 1 4 semiconductor element 15 resin mold 2 0 heat sink 21 cover 2 3.41 printed wiring board 24 ground terminal
第13頁 469615 圖式簡單說明 29 螺絲 ΙΙΗΙ 第14頁Page 13 469615 Brief description of drawings 29 Screws ΙΙΗΙ Page 14
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11207279A JP2001035975A (en) | 1999-07-22 | 1999-07-22 | Bga-type semiconductor device package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW469615B true TW469615B (en) | 2001-12-21 |
Family
ID=16537175
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW089114691A TW469615B (en) | 1999-07-22 | 2000-07-21 | BGA-type semiconductor device package |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP2001035975A (en) |
| KR (1) | KR20010015387A (en) |
| TW (1) | TW469615B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030058942A (en) * | 2001-04-09 | 2003-07-07 | 가부시키가이샤 스미토모 긴조쿠 엘렉트로 디바이스 | Radiation type bga package and production method therefor |
| JP5155890B2 (en) * | 2008-06-12 | 2013-03-06 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
| KR20160038440A (en) * | 2014-09-30 | 2016-04-07 | 삼성전기주식회사 | Power module package and method of fabricating thereof |
| WO2023032260A1 (en) * | 2021-08-31 | 2023-03-09 | ソニーセミコンダクタソリューションズ株式会社 | Semiconductor device and electronic equipment |
-
1999
- 1999-07-22 JP JP11207279A patent/JP2001035975A/en active Pending
-
2000
- 2000-07-21 KR KR1020000041843A patent/KR20010015387A/en not_active Application Discontinuation
- 2000-07-21 TW TW089114691A patent/TW469615B/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR20010015387A (en) | 2001-02-26 |
| JP2001035975A (en) | 2001-02-09 |
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| GD4A | Issue of patent certificate for granted invention patent | ||
| MM4A | Annulment or lapse of patent due to non-payment of fees |