.66 725 663 ltwf.doc/008 A7 _______B7 _ 五、發明說明（丨） 本發明是'有關於一種晶片之構裝，且特別是有關於 —種多晶片之構裝。 隨著電子科技不斷地演進，積體電路發展的趨勢無 不朝向高積集度、高密度、小體積的方向而設計，創造出 輕、.薄、短、小的電子產品，以提供更舒適的使用。在半 導體構裝的技術上，開發高密度的構裝一直是長久以來的 目標’其中多晶片構裝即是其中一例。 請參照第1圖，其繪示習知多晶片構裝的結構。習 知氣變、裝100保將多個晶片貼合於一碁板I?4之 主’晶片102包括多個墁墊1〇6，透過打上導線1〇8使 得焊墊106與基板104之導線接點110電^性連通，在透過 二封膠的製程，灌上一封膠材料112(第1圖中虛線所包圍 的面積)將晶片102、導線108包覆於內。 在上述構裝中，爹傳愚技均位於一基板之.上.，姐此 -將導致積體電路封裝的體積過大..，使得積體電路的重量過 童而與追求輕、薄、短、小的設計理念相違背。並且在上 述構裝中，晶片間透過基板之電路結構而相互傳導，如此 使得電.癤傳輸的路徑過長，而造-成訊號衰減與延遲的發 生’降低晶片的效能。另外上述之多晶片構裝的製作程序 乃是將晶片製作切割萆成之後，才依序將多個晶片貼覆在 基板之上，而如此之製程實不具效率性，導致製程成本增 ’加。 因此本發明的目的之一就是在提供一種多晶片構 裝，可以縮小積體電路封裝的體積。 * 3 本紙張尺度適用/中國國家標準'(CNS)A4規格（210 X 297公釐） ---I--------Jy1.裝--- j (請先閱讀背面之注意事項再#寫本頁) S . 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 466725 6631 twf.doc/008 五、發明說明（>) 本發明的目的之二就是在提供一種多晶片構裝，可 以縮小晶片間電流傳導的路徑長度，因而可減少訊號衰減 與延遲的發生，並大幅提高記憶體的性能。。 本發明的目的之三就是在提供一種多晶片構裝製 程，可以降低製程成本。 爲達成本發明之上述和其他目的，提出一種多晶片 搆裝包括至少一第二晶片、一第一晶片、多個融合凸塊、 一導鳞結構體。其中第二晶片包括多個半導體單元、多個. 內層導線，而第u二晶片之內層導線與第二晶片之半導體單 元電性連通，另外第二晶片還包括一第二主動表面。再者， 第一晶片包括多個半導體單元、多個連內內層導線、多個 連夕f內層導線，而第一晶片之半導體單元與第一晶片之連 內內層導線電性連通，亦與第一晶片之連外內層導線電性 連寒，另外第一晶片具有一第一主動表面，且第一晶片乏 第一主動表面與第二晶片之第二主動表面相對。再考，屬 &跤策5勗片之第二主動表面與第一晶片之等一主 動表g間，並且融合凸塊與第二晶片之內層導線電性連 通，融合凸塊亦與第一晶片之連內內層導線電性連通。再1 者，導線結構體包括至少一介電材質、一立體化導線結構’ 立體化導線結構交錯於介電材質之內，並且與第一晶片之 連外內層導線電性連通，另外導線結構體包覆第二晶片之 周圍，此外導線結構體還包括一第一表面以及對應之一第 二表面，導線結構體之第一表面與導線結構體之第二表面 分別位於導線結構體的相對之兩側，其中導線結構體之第 4 ---— — — — — — ^ . 1 1 1 ! I 灯.！ :) (請先閱讀背面之注意事項#填寫本頁) 本紙張尺度適用F國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 466725 A7 663 ltwf.doc/008 B7 五、發明說明（巧） 一表面與第一晶片之第一主動表面接觸。 依照本發明的一較佳實施例’其中在第一1晶片的第 —主動表面的表層還具有一保護層，此保護層包覆多個連 內焊墊、多個連外焊塾，而在連內焊墊的一表面之上還包 括多個連內過渡結構體，連內過渡結構體是由鈦、銅之導 電材質所組合而成。另外導線結構體之介電材質包括聚亞 醯胺、苯基環丁烯，而立體化導線結構之導電材質包括銅、 金、鎳、鋁、鎢。此外在導線結構體之第二表面之上方還 包括多個連外凸塊，連外凸塊與立體化導線結構電性連 通，並且本發明之多晶片構裝還包括—基板，此基板具有 基板導線結構，而基板導線結構與連外凸塊電性連通，亦 與多個焊球電性連通，另外在第二晶片與第一晶片之間還 包括一第一塡充材質，而在基板與導線結構體間還包括一 第二塡充材料。 爲達成本發明之上述和其他目的’提出一種多晶片 構裝琴程，依序包括下列步驟：提供多個第二晶片，每 個第二晶片包括多個半導體單元、多個內層導線，而每一 個第二晶片之內層導線分別與每一個第二晶片之半導體單 元電性連通，另外每一個第二晶片還包括一第二主動表 面。再提供一晶圓，此晶圓包括多個晶圓刻劃區、多個第 一晶片，晶圚刻劃區分別位於第一晶片的周圍，而每一個 第一晶片包括多個半導體單元、多個連內內層導線、多個 連外內層導線，而每一個第一晶片之半導體單元分別與每 一個第一晶片之連內內層導線電性連通，亦分別與每-個 5 本紙張尺度適用國國家標準（CNS)A4規格（210 X 297公釐） ^ " .1!丨！ — ！..-)製.丨 I (請先閲讀背面之注意事項再填寫本頁) 訂. --娘i 46672b 663 1 twf.d〇c/008 A7 B7 質 五、發明說明（w) 第一晶片之連外內層導線電性連通，另外每一個第一晶片 具有一第一主動表面。進行一歲程， ，另外第二晶片之第二 晶片之第一主動表面相對。進行一導線結 構體製作的製程，形成一導線結構體包括至少一介電材 立體化導線結構，而立體化導線結構交錯於介電材 內，並且立體化導線結構與第一晶片之連外內層導線 €丨纟連通，此外導線結構體還包括多個導線結構體刻劃 ^，而導線結構體刻劃區分別對應晶圓刻劃區，且位於晶 區之上，另外導線結構體還包括一第一表面以及對 —第二表面，導線結構體之第一表面與導線結構體之 表面分別位於導線結構體的相對之兩側，其中該導線 結構體之該第一表面與該堅第一晶片之該些第一主動表面 /胃0。以及進行一去除刻劃區的製程，將晶圓刻劃區與導 線緖櫸體刻劃區去除。 依照本發明的一較佳實施例，其中在第一晶片的第 —主動表面的表層還具有一保護層’此保護層包覆多個連 內焊蟄、多個連外焊墊，而在連內焊墊的一表面之上還包 括多個連內過渡結構體’此連內過渡結構體是由鈦、銅之 導憾材質所組合而成。另外導線結構體之介電材質包括聚 亞酿肢、苯基環丁烯，而立體化導線結構之導電材質包括 銅、金、鎳、鋁、鎢。此外在導線結構體製作的製程之後， 本紙張尺度適用P國家標準（CNS)A4規格⑵〇 X 297公釐） ------------裝------1—訂|丨| (請先閱讀背面之注意事項再填窝本頁) 經濟部智慧財產局員工消費合作社印製 466725 經濟部智慧財產局員工消費合作社印製 531twf.doc/008 ξ ____B7 ---------- 五、發明說明（《） 還包括植入連外凸塊之製程，多個連外凸塊位於導線結構 體之第一表面之上方，連外凸塊與立體化導線結構電性連 通。並且本發明之多晶片構裝製程還包括提供一基板，此 基板具有基板導線結構，而基板導線結構與連外凸塊電性 連通、，亦與多個焊球電性連遜，另外在晶片接合的製程之 後，還包括一第一塡入塡膠材料之製程’將一第一塡膠材 料塡充於第二晶片與第一晶片之間，而在接合基板的製程 之後，還包括一第二塡入塡膠材料之製程，將一第二塡膠 材料塡充於基板與導線結構體之間。 爲讓本發明之上述和其他目的、特徵、和優點能更 明顯易懂，下文特舉一較佳實施例，並配合所附圖式，作 詳細說明如下： 圖式之簡單說明： 〜 第1圖繪示習知多晶片構裝的結構。 ' 第2圖至第9圖繪示依照本發明第一較佳實施例的 —種多晶片構裝製程剖面示意圖。 _ 第10圖繪示依照本發明第二較佳實施例的一種多 晶片構裝製程之剖面示意圖。 第11圖繪示依照本發明第三較佳實施例的一種多 晶片構裝之剖面示意圖。 第12圖繪示依照本發明第四較佳實施例的一種多 曰曰片構裝之剖面不意圖。 圖式之標示說明： 本紙張尺度適用/中國國家標準（CNS)A4規格（210 X 297公爱 1 (請先閱讀背面之注項再填寫本頁> 裝 缘，- 4 66 725 663 1 twf.doc/008 A7 B7 五、發明說明（ 100 經濟部智慧財產局員工消費合作社印製 多晶片構裝 102 :晶片 104、350 :基板 106 :焊墊 108 :導線 110:導線接點 112 :封膠材料 300 :晶圓 302 :晶圓刻劃區 200、252、400 :第一晶片 202 :半導體單元 204 :連內內層導線 206 :連外內層導線 208 :第一主動表面 210 :保護層 212 :連內焊墊 214 :連外焊墊 216 :表面 220 :連內過渡結構體層 226 :連內過渡結構體 222 :第一過渡層 224 :第二過渡層 230、312 :光阻 232、314 :開口 閱 讀 背 面 之 注 意 事 項, 再( 填 寫 本 頁 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 466 725 663 ltwftdoc/008 A7 B7 五、發明說明（/ 234 236 238 250 254 256 258 316 :導電材質 多餘部份 焊腳 450a、450b :第二晶片 內層導線 第二主動表面 558 :連內凸塊 經濟部智慧財產局員工消費合作社印製 260 :助焊劑 272 :融合凸塊 274 :第一塡膠材料 280 :導線結構體 282 :介電材質 284 :介層窗 286 :導電材質 288 :立體化導線結構 290、358 :第一表面 292、360 :第二表面 294 :連外凸塊 310 :連外過渡結構體層 296 :連外過渡結構體 298 :導線結構體刻劃區 352 :基板導線結構 354 :第一接點 356 :第二接點 1 閱 背 面 之 注 意 事項, 再. 填 寫 本 頁 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） A7 B7 466725 663 1 twf,doc/008 五、發明說明（？） 彳62 :焊球 364 :第二塡膠材料 實施例 請參照第2圖至第9圖’其繪示依照本發明第一較 佳實施例的一種多晶片構裝製程剖面示意圖。 請先參照第2圖，首先提供一晶圓300，晶圓300 包括多個第一晶片2〇〇、多個晶圓刻劃區302,而晶圓刻 劃區302位於第一晶片200之周圍，另外第一晶片200包 括多個半導體單元2〇2、多個連內內層導線204、多個連 外內層導線206，而連內內層導線204與半導體單元202 電性連通，連外內層導線206亦與半導體單元2〇2電性連 通。並且第一晶片200還具有一第一主動表面208，而在 桌—晶片200之第一主動表面208之表層具有一保護層 21〇，保護層210包覆多個連內焊墊212、連外焊墊214， ’而連內焊墊212之一表面216暴露出第一晶片2〇0之第一 主動表面208，連外焊墊214之一表面218亦暴露出第一 晶片200之第一主動表面2〇8，並且連內焊墊212與連內 內層導線204電性連通，而連外焊墊214與連外內層導線 206電性連通。 接下來進行一覆上連內過渡結構體之製程，將一連 內過渡結構體層220(seed metal structure layer)覆於第一晶 片200之第一主動表面208之上，而連內過渡結構體層220 包括一第一過渡層222、一第二過渡層224’而第一過渡 10 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） HI —--丨 ϊίϊ -裝 i I (請先閱讀背面之注意事t#l填寫本頁) 訂： 經濟部智慧財產局員工消費合作社印製 A7 B7 4 6 6 7 2 5 663 ltwf.doc/008 五、發明說明（q) 層222位沾第一晶片200之第一主動表面208之上，第二 過渡層224位於第一過渡層222之上，其中第一過渡層222 之導電材質包括鈦，第二過渡層224之導電材質包括鋁， 接下來再覆上一光阻230於連內過渡結構體層220之上。 §靑參照第3圖，透過微影触刻的製程，定義出多個 開口 232，開口 232貫穿光阻230，再沈積一導電材質234 於開口 232之內，而沈積導電材質234的方式可包括電鍍、 印刷等方式。 請參照第3圖、第4圖，再進行一化學硏磨拋光 (chemical mechanical polish)的製程，將該導電材質234之 多餘部份236(暴露於光阻230之外的導電材質234)磨去， 而形成多個焊腳238。 〆 請參照第4圖、第5圖，將光阻230除去，再透過 / 蝕刻的步驟將未被焊腳238覆蓋之連內過渡結構體層220 除去，而形成多個連內過渡_結構體226，如第5圖所示， 並且連內過渡結構體226與連內焊墊212電性連通，亦與 焊腳238電性連通。接下來提供多個第二晶片250，而每 一第二晶片250的功用與內部結構可以是不一樣的，第二 晶片250包括多個半導體單元252、多個內層導線254， 而第二晶片250之內層導線254與第二晶片250之半導體 單元252電性連通，並且第二晶片2S0還具有一第二主動 表面256，在第二晶片250之第二主動表面256之上還包 括多個連內凸塊258與內層導線254電性連通。 .請參照第5圖、第.6圖，接下來進行一晶片接合之 --------111)1-裝.！ I! — 訂·！ — — 1緣 (請先閱讀背面之注意事^ΐ:、填寫本頁) ί 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 46672b A7 663 1twf.doc/008 _B7____— 五、發明說明（（6) 製程，首先在第二晶片250之連內凸塊258之上在覆上一 助焊劑260，再透過迴焊之製程，將多個連內凸塊258與.66 725 663 ltwf.doc / 008 A7 _______B7 _ V. Description of the Invention (丨) The present invention is' relating to the configuration of one type of wafer, and in particular to the configuration of a type of multi-chip. With the continuous evolution of electronic technology, the development trend of integrated circuits has been designed in the direction of high accumulation, high density, and small volume, creating light, thin, short, and small electronic products to provide more comfort. usage of. In the field of semiconductor packaging technology, the development of high-density packaging has been a long-term goal, and multi-chip packaging is one of them. Please refer to FIG. 1, which illustrates a conventional multi-chip structure. It is known that the main chip of the air change, mounting 100, and bonding a plurality of wafers to a cymbal plate I-4 includes a plurality of cymbal pads 106, and the bonding pads 106 and the conductors of the substrate 104 are made by conducting wires 108. The contacts 110 are electrically connected. During the manufacturing process of the second sealant, a piece of adhesive material 112 (the area enclosed by the dashed line in the first figure) is poured to cover the chip 102 and the lead 108 inside. In the above configuration, the daddy pass-through technique is located on a substrate. This will cause the volume of the integrated circuit package to be too large, making the integrated circuit's weight too small and the pursuit of lightness, thinness, and shortness. Small design concepts are contrary. And in the above-mentioned configuration, the wafers conduct each other through the circuit structure of the substrate, so that the path of the electric transmission is too long, and the generation of signal attenuation and delay is caused to reduce the performance of the chip. In addition, the above-mentioned multi-wafer structure manufacturing procedure is to cut and singulate wafers, and then sequentially attach multiple wafers to the substrate, and such a process is not efficient, resulting in an increase in process costs. Therefore, one of the objects of the present invention is to provide a multi-chip structure, which can reduce the volume of an integrated circuit package. * 3 This paper size is applicable / Chinese National Standard '(CNS) A4 specification (210 X 297 mm) --- I -------- Jy1.pack --- j (Please read the precautions on the back first Again # write this page) S. Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economy Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economy 466725 6631 twf.doc / 008 V. Description of the invention (>) The second purpose of the present invention is By providing a multi-chip structure, the path length of current conduction between chips can be reduced, thereby reducing the occurrence of signal attenuation and delay, and greatly improving the performance of the memory. . A third object of the present invention is to provide a multi-chip fabrication process, which can reduce the process cost. In order to achieve the above and other objects of the present invention, a multi-wafer structure is proposed including at least a second wafer, a first wafer, a plurality of fusion bumps, and a guide scale structure. The second wafer includes a plurality of semiconductor units and a plurality of inner conductors, and the inner conductors of the u-th wafer are in electrical communication with the semiconductor unit of the second wafer, and the second wafer also includes a second active surface. Furthermore, the first chip includes a plurality of semiconductor units, a plurality of interconnected inner-layer wires, and a plurality of interconnected inner-layer wires, and the semiconductor unit of the first wafer is in electrical communication with the interconnected inner-layer wires of the first wafer. It is also electrically connected to the outer and inner wires of the first chip. In addition, the first chip has a first active surface, and the first chip lacks the first active surface and is opposite to the second active surface of the second chip. Re-examination, between the second active surface of the & Wrestling Strategy 5 cymbal and an active surface g of the first chip, and the fusion bump is in electrical communication with the inner wire of the second wafer, and the fusion bump is also connected to the first The inner and inner wires of the chip are in electrical communication. Furthermore, the wire structure includes at least one dielectric material and a three-dimensional wire structure. The three-dimensional wire structure is interleaved with the dielectric material and is in electrical communication with the outer and inner wires of the first chip. The body covers the periphery of the second chip. In addition, the wire structure includes a first surface and a corresponding second surface. The first surface of the wire structure and the second surface of the wire structure are located opposite to the wire structure. On both sides, the fourth of the conductor structure ----------^. 1 1 1! I lamp.! :) (Please read the note on the back #Fill this page first) This paper size applies to National Standard F (CNS) A4 (210 X 297 mm). Printed by the Intellectual Property Bureau Staff Consumer Cooperative of the Ministry of Economic Affairs 466725 A7 663 ltwf. doc / 008 B7 5. Description of the Invention (Clever) A surface is in contact with the first active surface of the first wafer. According to a preferred embodiment of the present invention, wherein the surface layer of the first active surface of the first wafer 1 further has a protective layer, the protective layer covers a plurality of inner pads and a plurality of outer pads, and A plurality of internal transition structures are also formed on one surface of the internal solder pads. The internal transition structure is composed of conductive materials of titanium and copper. In addition, the dielectric materials of the wire structure include polyimide and phenylcyclobutene, and the conductive materials of the three-dimensional wire structure include copper, gold, nickel, aluminum, and tungsten. In addition, a plurality of outer bumps are further included above the second surface of the wire structure, and the outer bumps are in electrical communication with the three-dimensional wire structure, and the multi-chip structure of the present invention further includes a substrate, which has a substrate. Wire structure, and the substrate wire structure is in electrical communication with the external bumps, and is also in electrical communication with a plurality of solder balls. In addition, a second filling material is included between the second chip and the first chip, and the substrate and the A second filling material is further included between the lead structures. In order to achieve the above and other objectives of the invention, a multi-chip assembly process is proposed, which includes the following steps in order: providing a plurality of second wafers, each of which includes a plurality of semiconductor units, a plurality of inner layer wires, and The inner layer wires of each second chip are in electrical communication with the semiconductor units of each second chip, and each second chip further includes a second active surface. A wafer is further provided. The wafer includes a plurality of wafer scribe regions and a plurality of first wafers. The wafer scribe regions are respectively located around the first wafer, and each first wafer includes a plurality of semiconductor units, a plurality of wafers, and a plurality of first wafers. One inner inner conductor, a plurality of outer inner conductors, and the semiconductor unit of each first wafer is electrically connected to the inner inner conductors of each first wafer, respectively, and each of 5 pieces of paper Applicable national standard (CNS) A4 specification (210 X 297 mm) ^ " .1! 丨! —! ..-). 丨 I (Please read the precautions on the back before filling this page) Order.-Niang i 46672b 663 1 twf.d〇c / 008 A7 B7 Quality 5. Description of the invention (w) The first chip The outer and inner wires are electrically connected, and each first chip has a first active surface. The one-year process is performed, and the first active surface of the second wafer of the second wafer is opposite. A manufacturing process of a wire structure is performed to form a wire structure including at least one dielectric material three-dimensional wire structure, and the three-dimensional wire structure is interleaved in the dielectric material, and the three-dimensional wire structure is connected to the outer inner layer wire of the first chip. € 丨 纟 communication, in addition, the wire structure also includes a plurality of wire structure scribes ^, and the wire structure scribe areas correspond to the wafer scribe areas and are located above the crystal area, respectively, and the wire structure also includes a first A surface and a second surface, the first surface of the wire structure and the surface of the wire structure are located on opposite sides of the wire structure, respectively, wherein the first surface of the wire structure and the first wafer The first active surfaces / stomach 0. And a process of removing the scribe region is performed to remove the wafer scribe region and the wire beech scribe region. According to a preferred embodiment of the present invention, a surface layer on the first active surface of the first wafer further includes a protective layer. The protective layer covers a plurality of inner pads and a plurality of outer pads. One surface of the inner pad also includes a plurality of inter-internal transition structures. The inter-internal transition structures are made of titanium and copper. In addition, the dielectric materials of the wire structure include polyurethane, phenylcyclobutene, and the conductive materials of the three-dimensional wire structure include copper, gold, nickel, aluminum, and tungsten. In addition, after the manufacturing process of the wire structure, this paper size applies the P National Standard (CNS) A4 specification ⑵〇X 297 mm) ------------ installation ----- 1— Order | 丨 | (Please read the notes on the back before filling in this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 466725 Printed by the Employee Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 531twf.doc / 008 ξ ____B7 ---- ------ V. Description of the invention (") Also includes the process of implanting the outer bumps, a plurality of outer bumps are located above the first surface of the wire structure, and the outer bumps and the three-dimensional wire structure Electrically connected. In addition, the multi-wafer assembly process of the present invention further includes providing a substrate having a substrate lead structure, and the substrate lead structure is in electrical communication with the external bumps, and also indirectly connected with a plurality of solder balls. After the bonding process, it also includes a first process of inserting the glue material into the first wafer material between the second wafer and the first wafer, and after the substrate joining process, a first The manufacturing process of the second adhesive material is to fill a second adhesive material between the substrate and the wire structure. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: ~ 1st The figure shows the structure of a conventional multi-chip structure. '' FIGS. 2-9 show cross-sectional schematic diagrams of a multi-chip fabrication process according to the first preferred embodiment of the present invention. _ Figure 10 is a schematic cross-sectional view of a multi-chip fabrication process according to a second preferred embodiment of the present invention. FIG. 11 is a schematic cross-sectional view of a multi-chip structure according to a third preferred embodiment of the present invention. Fig. 12 is a schematic diagram showing a cross-section of a multi-chip assembly according to a fourth preferred embodiment of the present invention. Schematic labeling instructions: This paper size is applicable / Chinese National Standard (CNS) A4 specification (210 X 297 Public Love 1 (please read the note on the back before filling this page > mounting margin,-4 66 725 663 1 twf .doc / 008 A7 B7 V. Description of the invention (100 Multi-chip structure printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 102: Wafer 104, 350: Substrate 106: Welding pad 108: Wire 110: Wire contact 112: Sealant Material 300: Wafer 302: Wafer scribed areas 200, 252, 400: First wafer 202: Semiconductor unit 204: Connected to inner inner conductor 206: Connected to outer inner conductor 208: First active surface 210: Protective layer 212 : Inner pad 214: outer pad 216: surface 220: inner transition structure layer 226: inner transition structure 222: first transition layer 224: second transition layer 230, 312: photoresist 232, 314: Read the notes on the back of the book, and then (Fill in this page, the paper size applies to Chinese National Standard (CNS) A4 (210 X 297 mm)) 466 725 663 ltwftdoc / 008 A7 B7 V. Description of the invention (/ 234 236 238 250 254 256 258 316: Welding legs 450a, 450b of excess part of conductive material: The second active surface of the two-chip inner wire. 558: Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 260: Flux 272: Fusion bump 274: First adhesive material 280: Wire structure 282: Dielectric Material 284: Intermediate window 286: Conductive material 288: Three-dimensional wire structure 290, 358: First surface 292, 360: Second surface 294: Outer bump 310: Outer transition structure layer 296: Outer transition structure 298: Wire structure scribed area 352: Substrate wire structure 354: First contact 356: Second contact 1 Please read the precautions on the back, then. Fill in this page. The paper size applies to the Chinese National Standard (CNS) A4 specification ( 210 X 297 mm) A7 B7 466725 663 1 twf, doc / 008 V. Description of the invention (?) 彳 62: Solder ball 364: Second glue material embodiment Please refer to Figure 2 to Figure 9 A schematic cross-sectional view of a multi-wafer assembly process according to the first preferred embodiment of the present invention. Please refer to FIG. 2 first, and firstly provide a wafer 300. The wafer 300 includes a plurality of first wafers 200 and a plurality of wafers. The scribe region 302 is located on the first wafer. Around 200, in addition, the first chip 200 includes a plurality of semiconductor units 202, a plurality of inner inner conductors 204, a plurality of outer inner conductors 206, and the inner and inner conductors 204 are in electrical communication with the semiconductor unit 202 Even the outer and inner wires 206 are also in electrical communication with the semiconductor unit 202. In addition, the first wafer 200 also has a first active surface 208, and a protective layer 21 is provided on the surface of the first active surface 208 of the table-wafer 200. The protective layer 210 covers a plurality of inner pads 212 and outer pads. The pad 214, and one surface 216 of the inner pad 212 exposes the first active surface 208 of the first wafer 2000, and one surface 218 of the outer pad 214 also exposes the first active surface of the first wafer 200. The surface is 208, and the inner pads 212 are in electrical communication with the inner inner conductors 204, and the outer pads 214 are in electrical communication with the outer inner conductors 206. Next, a process of overlaying the inner transition structure is performed. A inner transition structure layer 220 (seed metal structure layer) is coated on the first active surface 208 of the first wafer 200. The inner transition structure layer 220 includes A first transition layer 222, a second transition layer 224 'and the first transition 10 This paper size applies Chinese National Standard (CNS) A4 (210 X 297 mm) HI —-- 丨 ϊί---装 i I (Please First read the notice on the back t # lFill this page) Order: Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 4 6 6 7 2 5 663 ltwf.doc / 008 V. Description of invention (q) 222 Above the first active surface 208 of the first wafer 200, the second transition layer 224 is located above the first transition layer 222. The conductive material of the first transition layer 222 includes titanium, and the conductive material of the second transition layer 224 includes aluminum. Next, a photoresist 230 is placed on the interconnect transition structure layer 220. § 靑 Referring to FIG. 3, through the lithography process, a plurality of openings 232 are defined, the openings 232 penetrate the photoresist 230, and a conductive material 234 is deposited in the openings 232. The method of depositing the conductive material 234 may include Plating, printing, etc. Please refer to FIG. 3 and FIG. 4, and then perform a chemical mechanical polish process to grind away the excess portion 236 of the conductive material 234 (the conductive material 234 exposed to the photoresist 230). To form a plurality of welding legs 238. 〆Please refer to Figure 4 and Figure 5, remove the photoresist 230, and then pass through the etching step to remove the inter-internal transition structure layer 220 that is not covered by the solder feet 238 to form multiple inter-internal transitions_structures 226 As shown in FIG. 5, the internal transition structure 226 is in electrical communication with the internal pad 212 and is also in electrical communication with the solder leg 238. Next, a plurality of second wafers 250 are provided, and the function and internal structure of each second wafer 250 may be different. The second wafer 250 includes a plurality of semiconductor units 252 and a plurality of inner-layer wires 254, and the second wafer 250 The inner conductive wire 254 of 250 is in electrical communication with the semiconductor unit 252 of the second chip 250, and the second chip 2S0 also has a second active surface 256. The second active surface 256 of the second chip 250 further includes a plurality of The inner bump 258 is in electrical communication with the inner wire 254. Please refer to Figure 5 and Figure 6, and then proceed to a wafer bonding -------- 111) 1-assembly.! I! — Ordered! — — 1 Yuan (Please read the note on the back ^ ΐ :, fill out this page) ί The paper printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs is compliant with China National Standard (CNS) A4 (210 X 297 mm) Printed by the Intellectual Property Bureau's Consumer Cooperative of the Ministry of Economic Affairs 46672b A7 663 1twf.doc / 008 _B7____ — V. Description of the invention ((6) Process, firstly, a flux 260 is coated on the inner bump 258 of the second chip 250 , And then through a process of re-soldering, the multiple internal bumps 258 and
I 多個焊腳238融合，而形成多個融合凸塊272，融合凸塊 272與連內過渡結構體226電性連通，且融合凸塊272亦 與第二晶片250之內層導線254電性連通。在迴焊之製程 .之後，會有多餘的助焊劑260殘留在第一晶片200之第一 主動表面208，需用溶劑淸洗。接下來進行一塡入塡膠材 料之製程，將一第一塡膠材料274塡充於第二晶片250與 第一晶片200之間，並且第一塡膠材料274包覆融合凸塊 272，然後再將第一塡膠材料274固化。 請參照第7圖，接下來進行一導線結構體製作的製 程，首先覆上一介電材質282,然後定義出多個介層窗2S4 ’ 再沈積一導電材質286，不斷重複上述之步驟，而形成一 導線結構體280。定義此導線材質的沈積結構爲一立體化 導線結構288，而立體化導線結構288交錯於介電材質282 之內，並且與第一晶片200之連外內層導線206電性連通。 導線結構體280包覆第二晶片250，且導線結構體280還 具有一第一表面290以及對應之一第二表面292，導線結 構體280之第一表面290與導線結構體280之第二表面292 分別位於導線結構體280的相對之兩側，並且導線結構體 280之第一表面290與第一晶片200之第一主動表面208 接觸。此外導線結構體280還包括多個導線結構體刻劃區 298，而導線結構體刻劃區298分別對應晶圓刻劃區302， 且位於晶圓刻劃區302之上。其中介電材質282可使用曰 (請先間讀背面之注意事項再填寫本頁) -裝 's- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員Η消費合作社印製 466725 五、發明說明（（丨） 立·杜邦公司（Hitachi-Dupont)所生產之聚亞醯胺（Polyimide) HD2732 或 HD2734 ，亦可使用苯基環丁烯 (Benzocyclobutene，BCB)。聚亞釀胺的形成方式可以用旋 塗固化的方式形成，旋塗後之聚亞醯胺需在一真空環境中 進行固化或在一氮氣環境下進行固化，溫度保持在250度 至400度之間，所需時間約0.5至1_5個小時。其中，對 於厚度較厚之聚亞醯胺結構，可採用多層旋塗固化的方式 形成。另外立體化導線結構288的導電材質可包括銅、金、 鋁、鎳、鎢等，由於此製作導線結構體的精度（約數十微 米)並不如半導體前段製程(小於一微米)之精密，因此可使 用低成本之製程，如電鍍、無電電鍍之方式形成’亦可使 用濺渡（sputtering)的方式。 接下來再進行一植入連外凸塊之製程，首先以濺鍍 的方式覆上一連外過渡結構體層310,再覆上一光阻層 312，透過微影蝕刻的製程，而形成多個開口 3M ’再塡入 一導電材質316於開口 314之內。 請參照第7圖、第8圖，接下來將光阻312除去’ 再除去未被導電材質316覆蓋住的連外過渡結構體層 310，而形成多個連外過渡結構體296。接下來再進行一迴 焊之製程，將導電材質316平整化’而形成多個連外凸塊 294，如第8圖所示。其中連外過渡結構體296與ii*體化 導線結構288電性連通，連外過渡結構體296亦與連外凸 塊294電性連通。 請參照第8圖、第9圖，進行一除去刻劃區的製程， 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ------------Ί裝--------訂---------線 - (請先閱讀背面之注意事f填寫本頁) /ί 4. 6 6 7 2 5 6631twf.doc/008 _____B7_____l 五、發明說明（(〜） 將晶圓刻劃區302與導線結構體刻劃區298除去’其結構 如第9圖所示，像是覆晶的結構。 匕由於本發明之多晶片構裝係_麗愚上下相疊’ 並透過連內凸塊而電性連通，如此.與習知技藝相較’可以 _ · ·.·* ' — .· _, - , — ·· — ·.· I ·ι 一 . 縮小積體電路封裝.的.體積，並且晶片間電流傳導的路徑長 .· 一 · · : - ...... 度較短，因而降低雜訊，可以提高晶片效能人另外明 之多晶片構裝之製程係在晶圓切割之製程之前如完成’如 此可以降低成本。 請參照第10圖，其繪示依照本發明第二較佳實施 例的一種多晶片構裝製程之剖面示意圖。在前述實施例 中，其連內凸塊之形狀爲/球狀>，然而本發明並非侷限於上 述的方式，連內凸塊558亦可以爲椎狀，其製作方式係先 將連內凸塊製作於第二晶片250的第二主動表面256上， 然後再用氬氣（argon)以離子轟擊(ion bombardment)的方式 使連內凸塊558製作成椎狀的結構。 ' 請參照第Π圖，其繪示依照本發明第三較佳實施 例的一種多晶片構裝之剖面示意圖。前述實施例中，其多 晶片構裝呈現如覆晶的形式，然而多晶片構裝之配置並非 侷限於上述的方式，亦可以將多晶片構裝包覆成BGA(Ball Grid Array)之形式，此時係再提供一基板350.，基板350 包括一基板導線結構352、多個第一接點354、多個第二 接點356 ’另外基板350還具有一第一表面358以及對應 之一第二表面360，並且基板350之第一表面358與基板 350之第二表面360分別位於基板350的相對之兩側，而 14 本紙張尺度適用中國國家標準（CNS)A4規格(210x297公楚） 經濟部智慧財產局員工消費合作社印製 66 725 663 1twf.d〇c/008 A7 _ B7___ 五、發明說明（丨、） 第一接點354暴露出基板350之第一表面358，第二接點 356暴露出基板350之第二表面360，且基板350之第一 接點354和基板350之第二接點3S6均與基板導線結構352 電性連通。並且基板350之第二接點3S6與連外凸塊294 電性連通，而基板350之第一接點354與多個焊球362電 I性連逋％另外2第二塡膠材料364塡充於基板350之第二 表面360與導線結構體280之第二表面292之間，而第二 塡膠材料364包覆連外凸塊294。 請參吗第12圖，其繪示依照本發明第四較佳實施 例的一種多晶片構_之剖面示意圖。在前述實施例中，僅 具有一第二晶片與第一晶片電性連通，然而多晶片構裝之 配置並非侷限於上述的方式，亦可以將一第一晶片400與 多個第二晶片450a、450b電性連通，而第二晶片450a、450b 的功用與內部結構可以是不一樣的° 縱上所述，本發明至少具有下列優點： /本發明之多晶片構裝’係將兩塊晶片上下相疊， 並透過連內凸塊而電性連通’可以縮小積體電路封裝的體 積，並且晶片間電流傳導的路徑長度較短，因而降低雜訊， 可以提高晶片效能。 2.本發明之多晶片構裝之製程’係在晶圓切割之製 程之前即完成’如此可以降低製程成本。 雖然本發明已以一較佳實施例揭露如上’然其並非 用以限定本發明’任何熟習此技藝者’在不脫離本發明之 精神和範圍內，當可作些許之更動與潤飾，因此本發明之 15 本紙張尺度適用中國國家標準（CNS)A4規格(210 X 297公楚) ^ ---— — — I.—- ------II--- _------- - - - 1 1^^^ (請先閲讀背面之注意事嗔美+填寫本頁) （ A7 B7 4 66 725 663 ltwf.doc/008 五、發明說明（（4) 保護範圍當視後附之申請專利範圍所界定者爲準 請 先 閱 背 意 事 項, ί 會裝 本. 頁 訂I The plurality of solder pins 238 are fused to form a plurality of fused bumps 272. The fused bumps 272 are in electrical communication with the inner transition structure 226, and the fused bumps 272 are also electrically connected to the inner conductors 254 of the second chip 250. Connected. After the reflow process, there will be excess flux 260 remaining on the first active surface 208 of the first wafer 200, which needs to be rinsed with a solvent. Next, a process of inserting a rubber material is performed, a first rubber material 274 is filled between the second wafer 250 and the first wafer 200, and the first rubber material 274 covers the fusion bump 272, and then The first glue material 274 is then cured. Please refer to FIG. 7. Next, a wire structure manufacturing process is performed. First, a dielectric material 282 is covered, and then a plurality of interlayer windows 2S4 'are defined, and then a conductive material 286 is deposited, and the above steps are continuously repeated, and A wire structure 280 is formed. The deposition structure of the wire material is defined as a three-dimensional wire structure 288, and the three-dimensional wire structure 288 is staggered within the dielectric material 282 and is in electrical communication with the outer inner wire 206 of the first chip 200. The wire structure 280 covers the second chip 250, and the wire structure 280 further has a first surface 290 and a corresponding second surface 292. The first surface 290 of the wire structure 280 and the second surface of the wire structure 280. 292 are respectively located on opposite sides of the lead structure 280, and the first surface 290 of the lead structure 280 is in contact with the first active surface 208 of the first wafer 200. In addition, the wire structure 280 further includes a plurality of wire structure scribed areas 298, and the wire structure scribed areas 298 respectively correspond to the wafer scribe area 302 and are located above the wafer scribe area 302. The dielectric material 282 can be used (please read the precautions on the back before filling out this page) -packing's- This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm)印 Printed by the Consumer Cooperative 466725 5. Description of the invention ((丨) Polyimide HD2732 or HD2734 produced by Hitachi-Dupont, or Benzocyclobutene (BCB) The formation of polyimide can be formed by spin coating. The polyimide after spin coating needs to be cured in a vacuum environment or a nitrogen atmosphere, and the temperature is maintained at 250 to 400 degrees. The time required is about 0.5 to 1-5 hours. Among them, thicker polyimide structures can be formed by multi-layer spin coating. In addition, the conductive material of the three-dimensional wire structure 288 can include copper and gold. , Aluminum, nickel, tungsten, etc., because the precision of the conductor structure (about tens of microns) is not as precise as that of the previous semiconductor manufacturing process (less than one micron), low-cost processes such as electrical The electroless plating method can be used to form a sputtering method. Next, a process of implanting the external bumps is performed. First, a continuous outer transition structure layer 310 is coated by sputtering, and then overlaid. A photoresist layer 312 is formed through a photolithography process to form a plurality of openings 3M ′, and then a conductive material 316 is inserted into the opening 314. Please refer to FIGS. 7 and 8, and then remove the photoresist 312 'Then remove the outer transition structure layer 310 that is not covered by the conductive material 316 to form a plurality of outer transition structures 296. Next, a re-welding process is performed to level the conductive material 316 to form a plurality of outer transition structures. The outer bump 294 is shown in Fig. 8. The outer transition structure 296 is in electrical communication with the ii * body conductor structure 288, and the outer transition structure 296 is also in electrical communication with the outer bump 294. Please Refer to Figure 8 and Figure 9 for a process of removing the scored area. The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ------------ Ί Install -------- order --------- line- (Please read the notes on the back f to fill out this page) / ί 4. 6 6 7 2 5 6631twf.doc / 008 _____B7_____l V. Description of the invention ((~) Remove the wafer scribed area 302 and the conductor structure scribed area 298 'The structure is as shown in Fig. 9, which is like a flip chip Structure. Due to the multi-chip mounting system of the present invention _Li Yu stacked on top of each other 'and connected electrically through the internal bumps, so. Compared with the conventional art,' may_ ···· * '—. · _,-, — ·· — ··· I · ι I. Reduce the volume of the integrated circuit package. And the path of current conduction between the chips is long. · · ·:-...... short degree Therefore, reducing noise can improve the performance of the wafer. The process of wafer assembly is well understood that if the wafer is cut before the process, it can reduce costs. Please refer to FIG. 10, which is a schematic cross-sectional view of a multi-chip fabrication process according to a second preferred embodiment of the present invention. In the foregoing embodiment, the shape of the internal convex block is / spherical. However, the present invention is not limited to the above-mentioned method. The internal convex block 558 may also be vertebral. The manufacturing method is to first make the internal convex block The block is made on the second active surface 256 of the second wafer 250, and then the internal bumps 558 are made into a vertebral structure by ion bombardment with argon. 'Please refer to FIG. Π, which is a schematic cross-sectional view of a multi-chip structure according to a third preferred embodiment of the present invention. In the foregoing embodiment, the multi-chip configuration is in the form of a flip chip. However, the configuration of the multi-chip configuration is not limited to the above-mentioned method, and the multi-chip configuration can also be wrapped into a BGA (Ball Grid Array) form. At this time, a substrate 350 is provided. The substrate 350 includes a substrate wire structure 352, a plurality of first contacts 354, and a plurality of second contacts 356. In addition, the substrate 350 also has a first surface 358 and a corresponding first surface 358. Two surfaces 360, and the first surface 358 of the substrate 350 and the second surface 360 of the substrate 350 are located on opposite sides of the substrate 350, and 14 paper sizes are applicable to the Chinese National Standard (CNS) A4 specification (210x297). Economy Printed by the Consumer Cooperatives of the Ministry of Intellectual Property Bureau 66 725 663 1twf.doc / 008 A7 _ B7___ V. Description of the Invention (丨,) The first contact 354 exposes the first surface 358 of the substrate 350 and the second contact 356 The second surface 360 of the substrate 350 is exposed, and both the first contact 354 of the substrate 350 and the second contact 3S6 of the substrate 350 are in electrical communication with the substrate lead structure 352. In addition, the second contact 3S6 of the substrate 350 is in electrical communication with the outer bump 294, and the first contact 354 of the substrate 350 is electrically connected to the plurality of solder balls 362. The other 2 is a second rubber material 364. Between the second surface 360 of the substrate 350 and the second surface 292 of the wire structure 280, the second adhesive material 364 covers the outer bump 294. Please refer to FIG. 12, which is a schematic cross-sectional view of a multi-chip structure according to a fourth preferred embodiment of the present invention. In the foregoing embodiment, there is only one second wafer in electrical communication with the first wafer. However, the configuration of the multi-wafer configuration is not limited to the manner described above, and a first wafer 400 and a plurality of second wafers 450a, 450b is electrically connected, and the functions and internal structures of the second wafers 450a and 450b may be different. As described above, the present invention has at least the following advantages: / The multi-wafer configuration of the present invention is to place two wafers up and down. Overlapping and electrically connecting by connecting the inner bumps can reduce the volume of the integrated circuit package, and the path length of the current conduction path between the chips is shorter, thus reducing noise and improving the performance of the chip. 2. The multi-wafer fabrication process of the present invention is completed before the wafer dicing process, so that the process cost can be reduced. Although the present invention has been disclosed above in a preferred embodiment, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention.发明 15 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 Gongchu) ^ -------I. --- ------ II --- _------ ----1 1 ^^^ (Please read the notes on the back of Rami + fill in this page) (A7 B7 4 66 725 663 ltwf.doc / 008 V. Description of the invention ((4) The scope of protection shall be attached as the appendix. As defined by the scope of patent application, please read the intent matters first, ί will be bound. Page order
I 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）I Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper is sized to the Chinese National Standard (CNS) A4 (210 X 297 mm)