經濟部智慧財產局員工消費合作社印製 A7 B7___ 五、發明說明（） 發明背景： (1) 發明範疇 本發明與一般非揮發性半導體記憶元件（non-volatile s e m i c ο n d u c t 〇 r d e v i c e s)有關，特別是學特1¾密度及高速分問 式非揮發性半導體記憶元件有關。 (2) 習知技藝之描述 非揮發性半導體記憶元件是利用富勒-諾得漢穿透 (Fowler-Nordheim tunneling)或熱載子注入方法將電荷由半 導體基板穿或跨越薄介電層至隔絕閘（俗稱漂浮閘）並儲存於 內，並利用富勒-諾得漢穿透或紫外線將儲存於隔絕閘內之電 荷穿或跨越薄介電層至半導體基板或另一電極（俗稱控制閘 或擦洗閘）來加予去除（俗稱擦洗）。除了電程式僅讀記億元件 (EPROM)利用紫外線擦洗外，幾乎所有的非揮性半導體記憶 元件均爲電可擦式。通常”快閃"（Flash)代表利用電壓脈波使 儲存的電荷以富勒-諾得漢穿透方法快速加以擦洗。基本上， 記憶細胞元的尺寸是高密度大量儲存所關切的主要重點，且 發展的元件結構需朝向高效率的寫、擦洗及讀，同時兼具高 可靠度。寫、擦洗及讀的效率主要以所使用的電壓、電流及 所費時間來決定，其値愈小愈有效率。高可靠性代表高的耐 用度（endurance)及續存度（retention):高耐用度代表寫及洗 的次數高（通常需大於1 〇5次），高續存度代表在干擾下具低 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） .Γ— IT ϋ — ίι I i· I I ί l I - n-- (請先闓讀背面之注意事項再填寫本頁) 訂.. 經濟部智慧財產局員工消費合作社印製 .:G 7 1 2 A7 __B7___ 五、發明說明（） 的電荷漏跑。 根據元件的結構，過去習知的技藝基本上可以區分成兩 類：疊堆閘式（stack-gate)結構及分閘式< split-gate)結構。圖 一顯示傳統疊堆式非揮發性半導體記億元件的一個典型結 構=圖二顯示傳統分閘式非揮發性半導體記億元件的一個典 型結構。圖一所示的疊堆式非揮發性記憶元件包括一 P型基 板100及在P型基板內之n +型源極擴散區101，及一個n + 型洩極擴散區置放於一個η·型洩極擴散區102的雙擴散 浅極（double-diffused drain)。一個具有約1〇〇埃厚度的薄穿 透氧化層104置於P型基板1〇〇之表面上。一個複晶矽層105 置於薄穿透氧化層之上，作爲漂浮閘（floating gate)。一 個夾在閘間的二氧化矽-氮化矽-二氧化矽（0N0)結構介電層 1 06將漂浮閘1 05及矽化複晶砂控制閘〔control gate) 1 07隔 開。 圖一所示之疊堆閘式#揮發性記憶元件的寫（程式）動作 是在控制閘加上一相對高的正電壓，大約12伏左右，及在 細胞元之源極加上一中庸的正電壓，大約9伏左右，洩極則 接地。通常，元件是操作在飽和區|接近源極之通道調變 (channel modulation)區內之高電場用來產生熱載子，其中能 量高於薄穿透氧化層與半導體基板傳導帶間之接面能障的 熱電子會注入到漂浮閘並儲存其中，產生的熱電洞形成基片 電流。因爲大部份的通道電荷均由正電壓的源極所吸收，注 入效率很差。同時，源極與通道間之摻雜質分佈需要最佳 化，來增加寫的效率，但不能產生可靠性問題》 4 本紙張尺度適用ΐ國國家標準（CNS)A4規格（210 X 297公釐） i 裝--------訂---------综 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 4 66 71 2 A7 ____B7___ 五、發明說明（） 圖一所示之疊堆式非揮性記憶元件的擦洗動作是在洩極 加上一相對高的正電壓，大約1 2伏左右，而控制閫極接地， 源極通常浮接。儲存於漂浮閘的電子，經由跨於薄穿透氧化 層的高電場，穿透到洩極。上述的擦洗法可以稍加修改，將 洩極與基板間的電壓由1 2伏降爲5伏或以下，控制閘極的 電壓由接地改爲負9伏。洩極與基板間電壓的降低主要在於 消除拽極與基板間產生的帶對帶穿透效應（band-to-band tunneling)，以避免不必要的熱電洞注入到漂浮閘或深陷於薄 穿透氧化層內。很顯然地，擦洗效率與跨於薄穿透氧化層的 電場及擦洗面積有關。通常|高的電場需要大的電壓；大的 擦洗面積需要加大薄穿透氧化層與洩極擴散的重疊區或將 基板及源極擴散區列入擦洗的面積。然而，由於漂浮閘對洩 極/基片/源極的擦洗動作不能夠自動限制，因此超擦洗 (over-erase)就不可避免。爲了避免超擦洗的發生，相當複雜 的電路設計及軟體以產生適應控制是必要的，以不斷的小擦 洗及驗証來避免細胞元的超擦洗。 圖二所示之分閘式非揮發性記憶元件包括一 P型基板Π 0 及置於P型基板110內之n +型源極和洩極擴散區118和 117。一層大約100埃厚度的穿透氧化層111置於一部份P 型基板11 〇上及在複晶矽漂浮閘Π 3之下的一部份n +型源極 擴散區11 8。漂浮閘11 3重疊一部份的n +型源極擴散區1 1 8 及通道。利用傳統局部氧化矽（LOCOS)的技術，一個特殊形 狀的複晶矽氧化層H4置於複晶矽漂浮閘1Π之上。一薄介 電層1 1 5將控制閘Π 6與複晶矽漂浮閘1 1 3之邊牆隔開，一 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 11 --------訂·-------- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印 66 7 1 2 A7 ______B7_____ 五、發明說明（） 部份的複晶矽漂浮閘疊在稍厚一點的氧化層11 2上。控制閘 Π 6經由稍厚一點的氧化層π 2重疊一部份的洩極擴散區1【7 及一部份通道。圖二所示之分閘式非揮發性記憶元件可以視 爲二個元件的串接：一個元件是漂浮閘所控制的非揮發性電 晶體及另一元件爲控制閘所控制之串接加強型 (enhancement-mode)電晶體。基於光独刻觀點，此元件被視 爲1.5個電晶體元件，若以每一位元的成本考量，則不太適 合高密度大量儲存的應用。再者，此結構受到控制閘之光蝕 刻對準容忍度的限制，形成元件進一步微縮的另一障礙。 圖二所示之分閘式非揮發性記憶元件的寫動作是在控制 閘上加一相對低的正電壓，大約2伏（控制閘電晶體的臨界電 壓），源極加上相對高的正電壓，大約1 2伏，洩極則接地。 控制間下之通道電子經由控制閘與漂浮閘間之空隙下面所 產生的橫向高電場來加速|以產生熱載子。凡能量超過薄氧 化層與基板傳導帶之介面能障的熱電子可以注入到漂浮閘 並儲存於其中，熱電洞則形成基板電流。此種寫入動作與疊 堆式非揮發性元件的寫入動作很相似。然而，控制閘所加之 正電壓小，通道電流比疊堆式結構小，此爲分閘式非揮發性 記憶兀件之優點。另外，分閘式非揮發性記憶元件需要相對 高的源極正電壓，與疊堆式比較是一個缺點，此缺點根源於 分閘式是1 . 5個電晶體。 圖二所示之分閘式非揮發性記憶元件的擦洗是在控制閘 加一相對高的正電壓，大約1 4伏左右，而源及拽極均接地。 擦洗的動作是由漂浮閘邊牆的尖端以富勒-諾得漢穿透方式 6 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） —--------------------訂·-------- (請先閱讀背面之;i意事項再填寫本頁) 4 6 6 71 A7 B7 五、發明說明（） 將漂浮閘所儲存的電子穿透到控制閘·，分閘式的擦洗法會在 漂浮閘的尖端累積正電荷來降低尖端的電場，擦洗會自動限 制’因此不會造成超擦洗的問題，擦洗的電路較爲簡單，此 爲分閘式的優點。然而，分閘式的擦洗需要相對高的控制閘 正電壓’形成此結構的另一缺點。另外.複晶矽漂浮閘之邊 牆需氧化，以致形成控制閘尖端的形成，此尖端會造成逆向 穿透干擾，厚一點的邊牆氧化層雖可降低逆向穿透機率，但 擦洗電壓變大是不可避免。 根據以上的解說，疊堆式結構能利用光飩刻技術加以微 縮，以達到高密度的要求，但寫的效率差，大部份的源極電 流均浪費掉，且超擦洗問題需複雜的電路來瀰補。分閘式結 構的尺寸大，不易微縮，寫的效率高，源極電流小，擦洗能 自動.限制，無需複雜的擦洗電路，但寫、洗的電壓較大。 基於此，本發明主要針對高密度及高速大量儲存的應用 提供可以微縮化分閘式非揮發性記憶元件來克服傳統分閘 式非揮發性記億元件的缺點。 發明槪述： -------------裝--------訂· <請先閱讀背面之注意事項再填寫本頁) 轉 經濟部智慧財產局員工消費合作社印製 本發明分成二部份。第一部份揭示一種同時製造場氧化 物隔離及非揮發性記憶元件之具有高耦合比與配備雙邊擦 洗之漂浮閘。本發明之場隔離技術不但能消除場離子佈植侵 入及鳥嘴延伸入原擬製造非揮發性記憶元件列陣之最小線 寬（minimum feature size)的工作區，同時亦降低隔離區所佔 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 Λ P 6 7 1， Α7 ______B7_______ 五、發明說明（） 之面積，達到高密度非揮發性記憶系統製造的第.一步要求。 同時，本發明將配備有雙邊擦洗電極和高耦合比的漂浮閘配 合場_離氧化罩結構合倂製造，光触刻之罩幕步驟亦因而減 少，以致製造的產率可以增加。 本發明的第二部份揭示在第一部份發明的結構上製造可 微縮化非揮發性記億元件的方法》此一可微縮化分閘式非揮 發性記億元件藉特殊墊層（spacer)形成技術加以製造，而不 受傳統光蝕刻技術的限制，其中漂浮閘電晶體和控制閘電晶 體之通道長度可以分別加以增減，使其個別長度甚小於所使 用技術的最小線寬。因此，製造完成之分閘式非揮發性記億 •. 元件的整合通道長度可以小於所使用技術的最小線寬，因而 解除傳統分閘式非揮發性記憶元件的主要缺點。另外，自動 對準·砍化（self-aligned silicidation)技術亦運用於分閘式非 揮發性記憶元件之控制閘、源極/共同埋層源極及洩極/共同 埋層洩極及週邊電晶體之閘、源及洩極的製作，以降低接觸 點及連線的電阻，進而提昇工作速度。同時1在元件邊牆上 使用氮化砂墊層技術，自動對準的接觸（self-aligned contact) 亦運用於記憶元件的製作，使本發明之分閘式非揮發性記憶 細胞元之面積減少，以達高密度的要求5總而言之，本發明 之可微縮化分閘式非揮發性記憶元件及所揭示的整合技術 應可運用於高密度及高速的大量儲存系統上。 圖示的簡要說明： 8 本紙張尺度適用令國國家標準（CNS)A4規格（210 X 297公釐） I.------------裝--------訂---------Μ (請先閱讀背面之注意事項再填寫本頁) B7 五、發明說明（） 圖一揭示傳統疊堆式非揮發性記憶元件之部份剖面結 構； 圖二揭不傳統分閘式非揮發性記憶元件之部份剖面結 構； 圖三至八揭示本發明同時製造場氧化物隔離和高耦合比 與配備雙邊擦洗電極漂浮閘之結構和製程的剖面圖； 圖九至二十一揭示本發明同時製造可微縮化分閘式非揮 發性記憶元件及周邊元件結構和製程的剖面圖。 圖號·對照說明 20單晶矽基板 21墊性（pad)氧化層 22 P井的深離子佈植雜質區22a P井 23光蛆罩幕 24 η井的深離子佈植雜質區 24an井 25光阻罩幕 26第一氧化砂層 28 ΟΝΟ複合層 -------------- --- (請先閱讀背面之注意事項再填寫本頁) 訂 绪 經濟部智慧財產局員工消費合作社印制衣 30第一 氧化砂層 27第一複晶矽層 29第一罩幕氮化矽層 3 1光阻罩幕 3 2第一良好覆蓋性氮化矽層32a第一氮化矽墊層 3 3第二氧化砂層 34a第二氮化砂墊層 34第二良好覆蓋性氮化矽層 35通道禁通帶 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 五、發明說明（) 36場氧化物層 38光阻罩幕 40 N通道離子佈植區 42a第三氧化矽層 43第二複晶矽層 44第三複晶矽層 44b第二複晶矽墊層 45a第三複晶矽上之氮化矽層46 47光阻罩幕 49淡摻雜質N-源擴散區 50b第三複晶矽二氧化矽層 52淡摻雜質N-洩極擴散區 5 3 b第一複晶矽二氧化矽層 55高濃度P +洩和源擴散區 57光阻罩幕 59光阻罩幕 60b高濃度洩擴散區 62氮化鈦 64介電材料 66鎢金屬層 37第二罩幕氮化矽層 39光阻罩幕 41 P通道離子佈植區 42b第一複晶矽邊牆氧化矽層 43a第·一複晶砂墊層 44a第二複晶矽墊層 45第三良好覆蓋性氮化矽層 光阻罩幕 48淡摻雜質P_源和洩擴散區 50a第三複晶矽二氧化矽層 5 1光阻罩幕 53a第三複晶矽二氧化矽層 54第三氮化矽墊層 56光阻罩幕 5 8 二氧化砂層 60a高濃度源/共同源擴散區 61矽化鈦 63光阻罩幕 6 5氮化鈦層 67 Ml金屬層 —------------ --------訂--------轉 {請先閱讀背面之浼意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印制农 發明之詳細說明： 10 本紙張尺度適用中國國家標準（CNS)A4規格（210* 297公釐） 4 6 6 7 1 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（） 參考圖三至八，這些圖揭示本發明第一部份的內涵採 用一個p型摻雜且晶面方向爲（100)之單晶矽基板20，基板 20先經溶劑之淸洗後，在85(TC之氧和水氣的環境下熱成長 一層約200至3 00埃之間厚度的墊性（pad)氧化層21。利用 光阻罩幕23的覆蓋，深離子佈植22來形成P并22a，如圖 三所示，再利用逆向調（reverse tone)光阻罩幕25的覆蓋，深 離子佈植24來形成η井24a，如圖四所示。去除覆蓋的光阻 罩幕25後，墊性氧化層2 1利用緩衝氫氟酸洗掉。然後，在 S50°C乾氧的環境下熱成長一層厚度約85至110埃之間的第 一氧化矽層26，再利用低壓化學氣相沉積法（LPCVD)，在溫 度約55(TC至63(TC之間將矽烷（silane)熱分解，堆積一層厚 度約1000至2000埃之間的第一複晶矽層27。在第一複晶矽 層27之上置放一個由二氧化砂-氮化砂-二氧化砂(ΌΝΟ)組成 的複合層28，其等效二氧化矽厚度約150至220埃之間。此 複合層的製造法均爲習知|是將第一複晶矽層27之表面氧 化，成長一層複晶矽二氧化矽層，再利用LPCVD堆積一層 氮化矽，然後再將氮化矽層於高溫下氧化。在ΟΝΟ層28之 上，利用低壓化學氣相沉積法，在溫度720°C左右將雙氯矽 院（dicholorosilane)與氨氣反應，堆積—-層約500至1 000埃 之間厚度的第一罩幕氮化矽層29。在第一罩幕氮化矽層29 之上，利用低壓化學氣相沉積法，在溫度約7 5 0 °C左右將四 乙嫌氧砂焼（tetraethoxysilane)熱分解反應，堆積一層約500 至1000埃厚度的第一罩幕二氧化矽層30。完成的複層氧化 罩結構如圖五所示。 11 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公；Ϊ ) —^------------裝--------訂---------緯 (請先閱讀背面之泫意事項再填罵本頁) 經濟部智慧財產局員工消費合作社印製 66 7 1 2 A7 ___B7 五、發明說明（） 複層氧化罩結構經由傳統光阻罩幕3 1來定義元件之工作 區，如圖五所示，並利用非等向性（anistropically)蝕刻將第 一罩幕二氧化矽層3 0及第一罩幕氮化矽層2 9去除·。將光阻 罩幕3 1去除後，利用低壓化學氣相沉積法，在溫度75(TC左 右下將四乙烯氧矽烷與氨氣反應，堆積一層厚度約1 000至 2 000埃之間之第一良好覆蓋性(^〇1^〇1'11^[)4)氮化矽薄膜，並 利用非等向蝕刻來形成第一氮化矽墊層32a，再以自動對準 方式非等向地蝕刻0N0層28及部份第一複晶矽層27 »蝕刻 的第一複晶矽層厚度約500至1 000埃之間，是用來形成配 備式電極，以作爲非揮發性記憶元件背面擦洗之用1並且同 時用來形成延伸的複晶矽區，以作爲防止場摻雜質侵入或降 低鳥嘴延伸入半導體元件及非揮發性記憶元件工作區之 用。·接著在85 0°C左右之乾氧或水氣的環境下，在複晶矽表 面成長厚度約150至220埃之間的第二氧化矽層33,此複晶 矽氧化層將作爲配備式複晶矽電極的穿透氧化層。然後，再 利用低壓化學氣相沉積法，在溫度約750t左右將四乙烯氧 矽烷與氨氣反應，堆積厚度約200至400埃之間第二良好覆 蓋性氮化矽層34，並藉非等向性蝕刻，在氧化後的複晶矽邊 牆形成第二氮化矽墊層34a。此時，硼雜質可以經由自動對 準植入半導體基板內，以形成通道禁通帶（channel st〇P)3 5， 離子佈植的劑量約1〇13至l〇14/cm2之間。圖六揭示完成的 複層氧化罩結構。 將圖六的結構置放於溫度約95〇t至1050°C之間的含氧 及水氣的環境中執行場氧化，以形成場氧化物層36，並以簡 11 本紙張尺度適用令國國家標準（CNS)A4規格（210 X 297公爱） -------------裝--------訂---------靖 <請先5?讀背面之;-*意事項再填寫本頁) 4 6 6 7 1 2 經濟部智慧財產局員工消費合作社印製 A7 ___B7___ 五、發明說明（） 寫F Ο X標示，場氧化隔離製程的最後結構如圖七所示上述 場氧化罩結構所得的結果是，不僅高耦合比及配備的雙邊擦 洗電極能由延伸第一複晶矽層的製造獲得，而且場雜質侵入 及鳥嘴延伸入元件工作區亦能由延伸第一複晶矽層的製造 來降低。 圖七所示之氧化罩結構所殘留的第一罩幕氮化矽層及第 二和第三良好覆蓋性氮化矽墊層可以利用熱磷酸去除：而覆 蓋在殘留第一罩幕氮化矽層之上的第一罩幕二氧化矽層亦 可自動脫落。此時，利用低壓化學氣相沉積法，在溫度約720 °C左右下將雙氯矽烷與氨氣反應，堆積厚度約10 00至20 00 埃之間的第二罩幕氮化矽層37。圖八揭示通道寬度方向的剖 面結構；圖九揭示通道長度方向的剖面結構。 現在參考圖九至圖二十一，其中揭示本發明第二部份的 內涵。首先利用傳統光蝕刻技術來定義一個非揮發性記憶元 件的虛擬長度，如圖九所示，其中虛擬長度等於二個記憶元 件通道長度加上一個共用源擴散寬度。利用光阻3 8作爲罩 幕，非等向地蝕刻第二罩幕氮化矽層37、ΟΝΟ層28及第一 複晶矽層27，然後去除光阻罩幕38。注意：此步驟可以將 預定製造其他半導體元件之半導體區24a上的氮化矽層 /ΟΝΟ層/複晶矽層所組成的疊堆結構完全去除，只保留一薄 的第一氧化砂層26 a 利用光阻罩幕39, P型雜質跨過第一氧化矽層26佈植入 P井22a內的半導體區40，以調整所有N-通道金氧半（MOS) 場效電晶體及非揮發性半導體記憶元件之控制閘元件的臨 13 本紙張尺度適用中國國家標準（CN'S)A4規格（210 X 297公_笼_) 裝--------訂---------緯 (請先閒讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 4 6 6 7 1 2 A7 ____B7_ 五、發明說明（） 界電壓（threshold voltage)及抵穿電壓（punch-through V ο 11 a g e) ’如圖十所不；再利用逆向調光阻罩幕（圖示省略）， 將P型及N型雜質跨過第一氧化砂層26佈植入N井24a內 的半導體區4 1，以調整所有P-通道MOS電晶體的臨界電壓 和抵穿電壓。將逆向調光阻去除後，利用稀釋氫氟酸或緩衝 氫氟酸等濕式化學品內瞬間泡洗，以去除元件外的第一氧化 石夕層2 6。 在溫度約85〇r至1 050°c之間的乾氧或水氣環境下，將 暴露的半導體表面區及暴露的複晶矽邊牆加以氧化，彤成厚 度約200至300埃之間的二氧化矽層42a和42b。然後利用 低壓化學氣相沉積法，在約600°C至650t間之溫度將矽烷 分解，堆積約500至1 500埃之間厚度的良好覆蓋性且自然 摻雜‘(m-shu doped)的第二複晶矽層43，如圖十一所示。此 良好覆蓋性複晶矽經非等向性蝕刻來形成邊牆第一複晶矽 墊層43a，如圖十二所示。然後，第二罩幕氮化矽層37利用 熱磷酸去除。再利用低壓化學氣相沉積法，在600°C至650 °C之間的溫度將矽烷分解，堆積厚度約500至2000埃之間 良好覆蓋性且摻雜的第三複晶矽層44。然後，利用低壓化學 氣相沉積法1在溫度約720°C左右將雙氯矽烷與氨氣反應， 堆積厚度約500至1000埃之間的第三良好覆蓋性氮化矽層 45。利用光阻罩幕46來定義N·通道及P·通道M0S元件的 通道長度，如圖十三所示，然後利用乾式蝕刻第三良好覆蓋 性氮化矽層45及非等向性蝕刻第三良好覆蓋性複晶矽層 44，在非揮發性記億元件之兩側邊形成第二複晶矽墊層44a 14* 本紙張尺度適用t國國家標準（CNS)A4規格（210 X 297公釐） ------------J 裝'-------訂--------- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 4 6 6 7 1 2 A7 ___B7__ 五、發明說明（） 和44b，如圖1 4所示。値得注意的是，複晶矽墊層之寬度主 要是由堆積之良好覆蓋性複晶矽層的厚度來決定。因此1漂 浮閘元件的通道長度及控制閘元件的長度均可以經由堆積 之良好覆蓋性複晶矽層厚度的控制來分別加予微縮化。 經由光阻罩幕（圖示省略），淡摻雜（1 ighί 1 y-d〇ped)P-通道 之源和洩擴散區48可以自動對準地將硼雜質跨過第三氧化 矽層42a植入，然後去掉光阻。利用900°C至1 〇5(TC之間的 溫度，在乾氧或水氣的環境下將暴露的第三複晶矽氧化，成 長厚度約200至300埃之間的複晶矽二氧化矽層50a和50b， 如圖十四所示。然後利用光阻47作罩幕，將ΟΝΟ層28和 第一複晶矽層27逐次利用活性離子蝕刻，如圖十四所示， 再將光阻47去除。利用光阻罩幕51，Ν·通道MOS元件及非 揮發·性記憶元件之淡摻雜質源極擴散區49及洩極擴散區52 經由磷雜質之植入形成，如圖十五所示，佈植的劑量約1〇13 至lCMVctn2之間，然後將光阻51去除。利用乾式蝕刻法將 N·及P-通道MOS元件之第三複晶矽閘44上的氮化矽層45a 去除，然後在乾氧的環境下加予氧化，在暴露的複晶矽上成 長約100至150埃之間的複晶矽二氧化矽層53a和53b，成 長的溫度約850°C至I05(TC之間。 利用低壓化學氣相沉積法，在溫度約750t左右將四乙烯 氧矽烷與氨氣反應，堆積厚度約500至1 000埃之間的第三 良好覆蓋性氮化矽層，並利用非等向性蝕刻，在N-和P·通 道MOS元件及非揮發性記億元件的邊牆形成第三氮化矽墊 層54。然後，利用光阻罩幕56，進行P-通道MOS元件高濃 15 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -------------裝--------訂---------镑 (請先間讀背面之主意事項再填寫本頁) Λ. 經濟部智慧財產局員工消費合作社印製 B 6 7 1 2 A7 —_______B7 五、發明說明（） 度洩和源擴散區55的硼離子佈植，如圖十六所示，佈植劑 量約1〇15至5xl〇H/cm2之間。 利用光阻罩幕5 7，非揮發性記憶元件之場氧化層及其淡 摻雜質源極擴散區上之二氧化矽層可以利用緩衝氫氟酸自 動對準地蝕刻，然後去除光阻5 7。接著在乾氧的環境及溫度 約850°C至105 (TC之間，將暴露的半導體表面加以氧化，成 長厚度約100至150埃之間的二氧化矽層58。利用光阻罩幕 59，進行N·通道MOS元件高濃度源和洩擴散區及非揮發性 半導體記憶元件之高濃度源/共同源與洩擴散區60a和60b的 砷離子植入，如圖十八所示，砷離子佈植的劑量約101 5至5 X 1 〇l5/cm2之間，然後將光阻59去除。利用普通爐管或快速 退火系統，在氮氣環境及溫度約90(TC至lOOtTC之間進行退 火1將離子佈植的摻雜質活性化或離子佈植所產生的瑕疵去 除。 此時，所有MOS元件及非揮發性半導體記憶元件之高濃 度源和洩擴散區表面及複晶矽閘與複晶矽控制閘上之薄氧 化層可以經由稀釋氫氟酸或緩衝氫氟酸化學溶液加予濕式 瞬間泡洗來去除或用非等向性乾式蝕刻去除。然後，將厚度 約5 00至1 000埃之間的鈦金屬薄膜濺鍍在結構上，並在氮 氣的環境下進行溫度約600°C左右的快速退火，使複晶矽及 基板上單晶矽的表面形成矽化鈦（TiSl2)膜61和與其上的氮 化鈦（TiN)膜62及所有介電層上形成氮化鈦膜62，如圖十九 所示。接著利用光阻罩幕63，將氮化鈦膜62加以選擇式去 除，蝕刻溶液爲氨水：雙氧水：純水的體積比爲1 : 1 : 5， 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） I , 裝--------訂---------，-f (請先閱讀背面之注意事項再填寫本頁) ：,,671 ^ ：,,671 ^ 經濟部智慧財產局員工消費合作社印*1^ A7 ____B7______ 五、發明說明（） 然後將光阻6 3去除，完成的結構再經氬氣環境下退火，以 降低矽化鈦及氮化鈦的電阻係數，如圖二十所示。 利用電漿增強式化學氣相沉積（PECVD)或其他低溫化學 氣相沉積法，在完成的結構上堆積一層厚的介電材料64，如 硼磷摻雜的二氧化矽（BPSG)，並利用化學-機械磨平（CMP) 法將整個結構加以平坦化。然後，利用光阻罩幕，將接觸洞 口的介電材料（如BPSG)挖走，再將光阻去除。接著在8503C 下使介電材料流動，將洞口圓形化3以下的製程均屬多層連 線，重覆製程部份將予省略。 利用濺鍍或化學氣相沉積法，將挖好的接觸洞堆積一層 薄的氮化鈦膜65，其厚度約100至200埃之間，以作爲上下 金屬連線或接觸所需的障礙金屬（barrier metal)，同時對氧化 矽或·其他覆蓋其下的材料具有良好的貼著性。接著利用低壓 化學氣相沉積法，在洞口堆積鎢金屬層66，以作塡滿洞口的 栓子（plugs)。金屬鎢可以利用約2501至500°C之間的溫度， 將氟化鎢（WF6)在氫氣中還原來獲得鎢。然後，利用化學-機 械磨平法去除鎢及氮化鈦，接著濺鍍一層厚度約5000至 1 0 000埃的Ml金屬膜67，並利用光阻罩幕將不要的金屬膜 去除，以完成元件間Ml的金屬連線67，如圖二十一所示。 多層金屬連線可以經由堆積中間介電層（intermediate dielectric layer)、化學-機械磨平、控洞 '塡障礙金屬層、塡 鎢栓、化學-機械磨平、連線金屬堆積及微影蝕刻，及重複上 述步驟得到。最後，堆積保護（p a s s i v a t i ο η)層將外部連線的 接觸墊（bonding pad)加以蝕刻，晶圓製造於焉完成。這裡値 本紙張尺度適用中國國家標準（CNS>A4说格（210 X 297公釐） ------------*裝--------訂---------曾 <請先閱讀背面之浼意事項再填寫本頁) 4. 6 6 7 1 A7 B7 五、發明說明（） 得注意的是，上述的鈦金屬可以利闬其他折光金屬 (refractory metal)取代，如鉅，钻，鉬等：上述所指的中間 介電層材料可以是化學氣相沉積的二氧化矽或其他低介電 常數的介電層；連線金屬可以是鋁、鋁合金或銅金屬》 由圖十二至圖二十一所揭示的內涵顯示，可微縮控制間 長度的非揮發性半導體記憶元件可以經由所堆積之良好覆 蓋性複晶矽層的厚度控制來得到，而無需考慮傳統之最小線 寬的限制。另外，本發明亦利用自動對準矽化技術，不但用 來降低非揮發性半導體記憶元件之控制閘的連線電阻|並且 共同埋層源擴散電阻亦因矽化而降低。 圖三至圖二十一所揭示的內涵是利用P型基板及硼摻雜 通道禁通區。但對於習知此種技藝的人亦可瞭解，相反摻雜 質形·態也可以使用於本發明。更進一步，非揮發性半導體記 憶元件亦可利用本發明的特點，將P通道非揮發性半導體記 憶元件製造於N井上。 本發明雖特別以參考所附內涵來圖示及形容，但對於習 知此種技藝的人亦可瞭解，各種不同形式或細節的更動不脫 離本發明的真實精神和範疇均可製作。 n ft n 1 n - - - n ^^1 ^^1 ί ί I n I It -: - n 一 I n m IF n t^i I (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 δ 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐）Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7___ 5. Description of the invention () Background of the invention: (1) The scope of the invention The invention relates to non-volatile semiconductor memory devices (non-volatile semic ο nduct 〇rdevices), especially Learn about 1¾ density and high-speed interrogation non-volatile semiconductor memory elements. (2) Description of conventional techniques Non-volatile semiconductor memory devices use Fowler-Nordheim tunneling or hot carrier injection to pass charges from a semiconductor substrate or across a thin dielectric layer to isolation Gate (commonly known as floating gate) and stored in it, and uses Fuller-Nordheim penetrating or ultraviolet to pass the charge stored in the isolation gate through or across the thin dielectric layer to the semiconductor substrate or another electrode (commonly known as control gate or Scrub the brake) to add to the removal (commonly known as scrub). Except for EPROM, which is scrubbed with ultraviolet rays, almost all nonvolatile semiconductor memory elements are electrically erasable. "Flash" usually refers to the use of voltage pulses to quickly scrub stored charge using the Fuller-Nordheim penetration method. Basically, the size of memory cells is a major concern of high-density mass storage. And the development of the device structure needs to be oriented to efficient writing, scrubbing and reading, and at the same time have high reliability. The efficiency of writing, scrubbing and reading is mainly determined by the voltage, current and time used, the smaller the 値More efficient. High reliability means high endurance and retention: high durability means high number of writes and washings (usually more than 105 times), and high continuity means that there is no interference. Low paper size applies to China National Standard (CNS) A4 (210 X 297 mm). Γ— IT ϋ — ί I i · II ί l I-n-- (Please read the notes on the back before filling in this Page) Order: Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs: G 7 1 2 A7 __B7___ V. The charge leakage of the description of the invention (). According to the structure of the element, the conventionally known skills can be basically divided into two Class: Stacked gate (st ack-gate) structure and split-gate structure. Figure 1 shows a typical structure of a traditional stacked non-volatile semiconductor memory device = Figure 2 shows a traditional non-volatile semiconductor memory device A typical structure of the stack. The stacked non-volatile memory device shown in FIG. 1 includes a P-type substrate 100 and an n + -type source diffusion region 101 in the P-type substrate, and an n + -type drain diffusion region. A double-diffused drain placed in an n-type drain diffusion region 102. A thin penetrating oxide layer 104 having a thickness of about 100 angstroms is placed on the surface of the P-type substrate 100. A polycrystalline silicon layer 105 is placed on top of the thin penetrating oxide layer as a floating gate. A silicon dioxide-silicon nitride-silicon dioxide (0N0) structure dielectric layer sandwiched between the gates 1 06 Separate the floating gate 105 and the silicified composite sand control gate 1 07. The write (program) action of the stacked gate type #volatile memory element shown in Figure 1 is to add a relatively high level to the control gate. Positive voltage of about 12 volts, plus a moderate positive voltage at the source of the cell, It is about 9 volts, and the drain is grounded. Generally, the element is operated in a high electric field in the saturation region | channel modulation region near the source to generate hot carriers, where the energy is higher than that of thin penetration oxidation Barrier hot electrons at the interface between the layer and the conduction band of the semiconductor substrate are injected into the floating gate and stored therein. The generated hot holes form the substrate current. Because most of the channel charges are absorbed by the source of positive voltage, Injection efficiency is poor. At the same time, the dopant distribution between the source and the channel needs to be optimized to increase the writing efficiency, but it cannot cause reliability problems. 4 This paper size applies the national standard (CNS) A4 specification (210 X 297 mm) ) I Pack -------- Order --------- Comprehensive (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 66 71 2 A7 ____B7___ 5. Description of the invention () The scrubbing action of the stacked non-volatile memory element shown in Figure 1 is to add a relatively high positive voltage to the drain electrode, about 12 volts, while the control electrode is grounded, and the source electrode Usually floating. The electrons stored in the floating gate penetrate to the drain electrode through a high electric field across a thin penetrating oxide layer. The above scrubbing method can be slightly modified, reducing the voltage between the drain and the substrate from 12 volts to 5 volts or less, and controlling the gate voltage from ground to negative 9 volts. The reduction of the voltage between the drain electrode and the substrate is mainly to eliminate the band-to-band tunneling effect between the drag electrode and the substrate, so as to avoid unnecessary injection of thermal holes into the floating gate or deep penetration into the thin gate. Within the oxidized layer. Obviously, the scrubbing efficiency is related to the electric field and scrubbing area across the thin penetrating oxide layer. Generally, a high electric field requires a large voltage; a large scrub area needs to increase the overlapping area of the thin penetrating oxide layer and drain diffusion or include the substrate and source diffusion area in the scrub area. However, since the scrubbing action of the floating gate on the drain / substrate / source cannot be automatically limited, over-erase is unavoidable. In order to avoid the occurrence of super scrub, it is necessary to have quite complicated circuit design and software to generate adaptive control. Continuous mini scrub and verification are used to avoid the super scrub of the cell. The split-type non-volatile memory element shown in FIG. 2 includes a P-type substrate Π 0 and n + -type source and drain diffusion regions 118 and 117 disposed in the P-type substrate 110. A layer of penetrating oxide 111 having a thickness of about 100 angstroms is placed on a portion of the P-type substrate 11 0 and a portion of the n + -type source diffusion region 118 under the polycrystalline silicon floating gate Π 3. The floating gate 11 3 overlaps a part of the n + -type source diffusion region 1 1 8 and the channel. Using traditional local silicon oxide (LOCOS) technology, a special shape of the polycrystalline silicon oxide layer H4 is placed on top of the polycrystalline silicon floating gate 1Π. A thin dielectric layer 1 1 5 separates the control gate Π 6 from the side wall of the polycrystalline silicon floating gate 1 1 3. A paper size applies the Chinese National Standard (CNS) A4 (210 X 297 mm) 11- ------- Order · -------- (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 66 7 1 2 A7 ______B7_____ V. Description of the invention ( ) Part of the polycrystalline silicon floating gate is stacked on the slightly thicker oxide layer 112. The control gate Π 6 overlaps a part of the drain diffusion region 1 [7 and a part of the channel through a slightly thicker oxide layer π 2. The split-type non-volatile memory element shown in Figure 2 can be considered as a series connection of two components: one component is a non-volatile transistor controlled by a floating gate and the other is a series-connected enhanced type controlled by a control gate. (enhancement-mode) transistor. From the standpoint of optical engraving, this element is considered as a 1.5 transistor element, which is not suitable for high-density mass storage applications if it is considered at the cost of each bit. Furthermore, this structure is limited by the tolerance of the photolithography alignment of the control gate, which forms another obstacle to further shrinking of the device. The write action of the split-type non-volatile memory element shown in Figure 2 is to apply a relatively low positive voltage to the control gate, about 2 volts (the threshold voltage of the control transistor), plus a relatively high positive voltage at the source. The voltage is approximately 12 volts and the drain is grounded. Channel electrons under the control gate are accelerated by the high lateral electric field generated under the gap between the control gate and the floating gate to generate hot carriers. Hot electrons whose energy exceeds the interface barrier between the thin oxide layer and the conduction band of the substrate can be injected into the floating gate and stored therein, and the thermal holes form the substrate current. This writing operation is similar to that of a stack type non-volatile device. However, the positive voltage applied by the control gate is small, and the channel current is smaller than that of the stacked structure, which is the advantage of the non-volatile memory element of the split-gate type. In addition, the switching-type non-volatile memory element requires a relatively high positive source voltage, which is a disadvantage compared with the stacked type, which is rooted in the switching-type is 1.5 transistors. The scrubbing of the non-volatile memory element shown in Figure 2 is to apply a relatively high positive voltage to the control gate, which is about 14 volts, and the source and terminal are grounded. The scrubbing action is performed by the tip of the side wall of the floating gate in a Fuller-Nordheim penetration method. 6 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm). ------------- Order · -------- (Please read the back of the page; I will fill in this page before the matter) 4 6 6 71 A7 B7 V. Description of the invention () Pass the electrons stored in the floating gate to the control gate. The split-gate scrubbing method will accumulate a positive charge at the tip of the floating gate to reduce the electric field at the tip. The scrubbing will be automatically limited, so it will not cause the problem of super scrubbing. The circuit is relatively simple, which is the advantage of the opening type. However, the gate-type scrubbing requires a relatively high control gate positive voltage 'to form another disadvantage of this structure. In addition, the side wall of the polycrystalline silicon floating gate needs to be oxidized to form the control gate tip. This tip will cause reverse penetration interference. Although a thicker side wall oxide layer can reduce the probability of reverse penetration, the scrubbing voltage becomes larger. Is inevitable. According to the above explanation, the stacked structure can be scaled down using photolithography technology to achieve high density requirements, but the writing efficiency is poor, most of the source current is wasted, and the super scrub problem requires complex circuits To make up. The size of the switching structure is large, it is not easy to be scaled down, the writing efficiency is high, the source current is small, and the scrubbing can be automatic. Limitation, no complicated scrubbing circuit is required, but the voltage for writing and scrubbing is large. Based on this, the present invention mainly provides high-density and high-speed mass storage applications to provide a non-volatile memory element that can be miniaturized to overcome the shortcomings of the traditional non-volatile memory device. Description of the invention: ------------- Installation -------- Order < Please read the notes on the back before filling this page) Transfer to the Intellectual Property Bureau of the Ministry of Economic Affairs for employee consumption Cooperatives printed this invention into two parts. The first part reveals a floating gate with high coupling ratio and dual-side scrubbing for simultaneous fabrication of field oxide isolation and non-volatile memory elements. The field isolation technology of the present invention can not only eliminate field ion implantation intrusion and bird's beak extending into the working area of minimum feature size of the original non-volatile memory element array, but also reduce the cost of the isolation area. Paper size applies to Chinese National Standard (CNS) A4 (210 X 297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Λ P 6 7 1, Α7 ______B7_______ 5. The area of the invention () is high density non-volatile The first step in the manufacture of sexual memory systems. At the same time, the present invention manufactures a floating gate compound field-ion oxide cover structure equipped with a double-side scrubbing electrode and a high coupling ratio, and the photo-etching mask step is also reduced, so that the manufacturing yield can be increased. The second part of the present invention discloses a method for manufacturing a micronizable non-volatile billion-counting element on the structure of the first part of the invention. ) Formation technology to manufacture, without being limited by the traditional photo-etching technology, in which the channel length of the floating gate transistor and the control gate transistor can be increased or decreased separately, so that their individual lengths are much smaller than the minimum line width of the technology used. As a result, the manufactured non-volatile non-volatile memory is worth hundreds of millions. • The integrated channel length of the device can be shorter than the minimum line width of the technology used, thus eliminating the main disadvantages of traditional non-volatile memory devices. In addition, the self-aligned silicidation technology is also applied to the control gate, source / common buried layer source and drain / common buried layer drain and peripheral power of the non-volatile memory element. The gate, source and drain of the crystal are made to reduce the resistance of the contact point and the connection, thereby increasing the working speed. At the same time, using nitrided sand cushion technology on the side walls of the device, self-aligned contacts are also used in the fabrication of memory devices, which reduces the area of the gated non-volatile memory cell of the present invention. In order to meet the requirement of high density, 5 in summary, the miniaturizable open-type non-volatile memory element of the present invention and the disclosed integrated technology should be applicable to high-density and high-speed mass storage systems. Brief description of the diagram: 8 This paper size applies the national standard (CNS) A4 specification (210 X 297 mm) I .------------ installation -------- Order --------- M (Please read the notes on the back before filling out this page) B7 V. Description of the invention () Figure 1 reveals the partial cross-sectional structure of a traditional stacked non-volatile memory element; Figure Secondly, a partial cross-sectional structure of a non-conventional split-gate non-volatile memory element is shown; FIGS. FIGS. 9 to 21 show cross-sectional views of the present invention for simultaneously manufacturing a structure and a manufacturing process of a micronizable and switchable non-volatile memory element and peripheral elements. Figure No. · Comparison description 20 Monocrystalline silicon substrate 21 Pad oxide layer 22 Deep ion implanted impurity region in P well 22a P well 23 Optical mask 24 24 Deep ion implanted impurity region in η well 24an Well 25 Barrier curtain 26 First oxide sand layer 28 ΟΝΟ composite layer -------------- --- (Please read the precautions on the back before filling this page) Staff of the Intellectual Property Bureau of the Ministry of Economic Affairs Consumer cooperative printing 30 first oxide sand layer 27 first polycrystalline silicon layer 29 first mask silicon nitride layer 3 1 photoresist mask 3 2 first good coverage silicon nitride layer 32a first silicon nitride pad Layer 3 3 Second oxide sand layer 34a Second nitride sand pad layer 34 Second good coverage silicon nitride layer 35 Channel forbidden band This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 5 Description of the invention () 36 field oxide layer 38 photoresist mask 40 N-channel ion implantation area 42a third silicon oxide layer 43 second polycrystalline silicon layer 44 third polycrystalline silicon layer 44b second polycrystalline silicon pad layer 45a Silicon nitride layer on third polycrystalline silicon 46 47 Photoresist mask 49 Lightly doped N-source diffusion region 50b Third polysilicon silicon dioxide layer 52 Lightly doped N-drain diffusion region 53 b first polycrystalline silicon dioxide layer 55 high concentration P + drain and source diffusion region 57 photoresist mask 59 photoresist mask 60b high concentration diffusion region 62 titanium nitride 64 dielectric material 66 tungsten metal layer 37 Second mask silicon nitride layer 39 Photoresist mask 41 P channel ion implantation area 42b First polycrystalline silicon sidewall oxide layer 43a First polycrystalline sand cushion layer 44a Second polycrystalline silicon cushion layer 45th Three good coverage silicon nitride layer photoresist mask 48 lightly doped P_ source and drain diffusion region 50a third polycrystalline silicon dioxide layer 5 1 photoresist mask 53a third polycrystalline silicon dioxide layer 54 Third silicon nitride pad layer 56 Photoresist mask 5 8 Sand dioxide layer 60a High concentration source / common source diffusion region 61 Titanium silicide 63 Photoresist mask 6 5 Titanium nitride layer 67 Ml metal layer ------ -------- -------- Order -------- Go to {Please read the notice on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Detailed descriptions of agricultural inventions: 10 This paper size applies Chinese National Standard (CNS) A4 specifications (210 * 297 mm) 4 6 6 7 1 Printed by the Consumers ’Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of invention () Reference Figures three to eight These figures reveal the connotation of the first part of the present invention. A p-type doped single crystal silicon substrate 20 with a crystal plane direction of (100) is used. After the substrate 20 is washed with a solvent, Under a water vapor environment, a pad oxide layer 21 having a thickness of about 200 to 300 angstroms is thermally grown. Utilizing the covering of the photoresist mask 23, the deep ion implantation 22 forms P and 22a, as shown in FIG. 3, and then using the reverse tone covering of the photoresist mask 25, the deep ion implantation 24 forms η Well 24a, as shown in Figure 4. After the covered photoresist mask 25 is removed, the pad oxide layer 21 is washed away with buffered hydrofluoric acid. Then, a first silicon oxide layer 26 having a thickness of about 85 to 110 angstroms is thermally grown under a dry oxygen environment at S50 ° C, and then a low pressure chemical vapor deposition (LPCVD) method is used, and the temperature is about 55 (TC to 63). (The silane is thermally decomposed between the TCs, and a first polycrystalline silicon layer 27 having a thickness of about 1000 to 2000 angstroms is deposited. On top of the first polycrystalline silicon layer 27, a sand dioxide-nitrogen layer is placed. The composite layer 28 composed of chemical sand-sand dioxide (ΌΝΟ) has an equivalent silicon dioxide thickness of about 150 to 220 angstroms. The manufacturing method of this composite layer is all known | is the first polycrystalline silicon layer 27 The surface is oxidized, a layer of polycrystalline silicon dioxide is grown, and a layer of silicon nitride is deposited by LPCVD, and then the silicon nitride layer is oxidized at a high temperature. On top of the ONO layer 28, a low pressure chemical vapor deposition method is used, At a temperature of about 720 ° C, dicholorosilane is reacted with ammonia gas, and a layer of silicon nitride layer 29 with a thickness of about 500 to 1,000 angstroms is deposited. Nitriding is performed on the first mask. On the silicon layer 29, tetraethoxy sand tetroxide (tetraethoxy) was prepared by a low pressure chemical vapor deposition method at a temperature of about 750 ° C. silane) thermal decomposition reaction, a layer of the first mask silicon dioxide layer 30 with a thickness of about 500 to 1000 angstroms is stacked. The structure of the completed multi-layered oxide mask is shown in Figure 5. 11 This paper size applies to Chinese National Standard (CNS) A4 Specifications (210 X 297 male; Ϊ) — ^ ------------ install -------- order --------- weft (please read 泫 on the back first) Please fill in this page and reprint this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 66 7 1 2 A7 ___B7 V. Description of the invention () The multi-layered oxide cover structure defines the working area of the component through the traditional photoresist cover 31. As shown in FIG. 5, the first mask silicon dioxide layer 30 and the first mask silicon nitride layer 2 9 are removed by anisotropically etching. After removing the photoresist mask 3 1 The low-pressure chemical vapor deposition method was used to react tetravinyloxysilane with ammonia gas at a temperature of about 75 ° C to deposit a layer of the first good coverage between about 1,000 and 2,000 angstroms (^ 〇1 ^ 〇 1'11 ^ [) 4) a silicon nitride film, and anisotropic etching is used to form a first silicon nitride pad layer 32a, and then the 0N0 layer 28 and a portion of the first compound are anisotropically etched in an automatic alignment manner. crystal Layer 27 »The etched first polycrystalline silicon layer has a thickness of between about 500 and 1,000 angstroms and is used to form equipped electrodes for back scrubbing of nonvolatile memory elements1 and at the same time to form extended polycrystalline silicon The silicon region is used to prevent field dopants from invading or reducing bird's beak from extending into the working area of semiconductor elements and non-volatile memory elements. · Then in a dry oxygen or water vapor environment at about 85 0 ° C, A second silicon oxide layer 33 having a thickness of about 150 to 220 angstroms is grown on the surface of the crystalline silicon. This polycrystalline silicon oxide layer will serve as a penetrating oxide layer for the equipped polycrystalline silicon electrode. Then, the low-pressure chemical vapor deposition method is used to react the tetravinyloxysilane with ammonia gas at a temperature of about 750t to deposit a second silicon silicon nitride layer 34 with a good coverage between about 200 and 400 angstroms. The second silicon nitride pad layer 34a is formed on the oxidized polycrystalline silicon sidewall by directional etching. At this time, boron impurities can be implanted into the semiconductor substrate through automatic alignment to form a channel forbidden band (channel stop) 35, and the ion implantation dose is about 1013 to 1014 / cm2. Figure 6 reveals the structure of the completed multilayer oxide hood. The structure of Fig. 6 is placed in an oxygen-containing and moisture-containing environment at a temperature of about 95 ° to 1050 ° C to perform field oxidation to form a field oxide layer 36. National Standard (CNS) A4 Specification (210 X 297 Public Love) ------------- Installation -------- Order --------- Jing & Please First read 5? On the back; fill in this page with * -intentions) 4 6 6 7 1 2 Printed by A7 ___B7___ of the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Description of the invention () Write F 〇 X mark, field oxidation isolation process The final structure is shown in Fig. 7. The result obtained from the above field oxide cover structure is that not only the high coupling ratio and the equipped double-side scrubbing electrode can be obtained by extending the production of the first polycrystalline silicon layer, but also the field impurity intrusion and bird's beak extension into The device working area can also be reduced by fabricating the first polycrystalline silicon layer. The first mask silicon nitride layer and the second and third good coverage silicon nitride pad layers remaining in the oxide mask structure shown in FIG. 7 can be removed using hot phosphoric acid: and the remaining first mask silicon nitride is covered The first silicon dioxide layer on top of the layer can also fall off automatically. At this time, the low-pressure chemical vapor deposition method is used to react the dichlorosilane and ammonia gas at a temperature of about 720 ° C to deposit a second mask silicon nitride layer 37 having a thickness of about 100 to 200 Angstroms. Figure 8 reveals the cross-sectional structure in the channel width direction; Figure 9 reveals the cross-sectional structure in the channel length direction. Reference is now made to Figs. 9 to 21, in which the connotation of the second part of the present invention is disclosed. First, the traditional photolithography technique is used to define the virtual length of a non-volatile memory element, as shown in Figure 9, where the virtual length is equal to the channel length of two memory elements plus a common source diffusion width. Using the photoresist 38 as a mask, the second mask silicon nitride layer 37, the ONO layer 28 and the first polycrystalline silicon layer 27 are anisotropically etched, and then the photoresist mask 38 is removed. Note: This step can completely remove the stack structure composed of the silicon nitride layer / ONO layer / polycrystalline silicon layer on the semiconductor region 24a of the other semiconductor device, and only a thin first oxide sand layer 26 a is used. Photoresist mask 39, P-type impurities across the first silicon oxide layer 26 and implanted into semiconductor region 40 in P well 22a to adjust all N-channel metal-oxide-semiconductor (MOS) field-effect transistors and non-volatile semiconductors Control element of memory element Pro 13 This paper size applies to Chinese National Standard (CN'S) A4 specification (210 X 297 male_cage_) (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 6 6 7 1 2 A7 ____B7_ V. Description of the invention () Threshold voltage and punch voltage -through V ο 11 age) 'As shown in Figure 10; using a reverse dimming mask (not shown), P-type and N-type impurities are implanted across the first oxide sand layer 26 and implanted in the N well 24a. The semiconductor region 41 is used to adjust the threshold voltage and the breakdown voltage of all P-channel MOS transistors. After the reverse photoresist is removed, it is instantaneously bubble-washed in a wet chemical such as diluted hydrofluoric acid or buffered hydrofluoric acid to remove the first oxide layer 26 outside the element. The exposed semiconductor surface area and the exposed polycrystalline silicon side wall are oxidized in a dry oxygen or water gas environment at a temperature between about 85 rpm and 1 050 ° C to a thickness of about 200 to 300 angstroms. The silicon dioxide layers 42a and 42b. Then low pressure chemical vapor deposition is used to decompose the silane at a temperature between about 600 ° C and 650t, and pile up a good coverage and natural doping of the thickness of about 500 to 1,500 angstroms (m-shu doped). The two polycrystalline silicon layer 43 is shown in FIG. This good coverage polycrystalline silicon is anisotropically etched to form the first polycrystalline silicon pad layer 43a of the side wall, as shown in FIG. Then, the second mask silicon nitride layer 37 is removed using hot phosphoric acid. The low-pressure chemical vapor deposition method is then used to decompose the silane at a temperature between 600 ° C and 650 ° C, and deposit a third doped polycrystalline silicon layer 44 with a good coverage between 500 and 2000 angstroms. Then, the low-pressure chemical vapor deposition method 1 is used to react the dichlorosilane and ammonia gas at a temperature of about 720 ° C to deposit a third silicon silicon nitride layer 45 with a good coverage between 500 and 1000 angstroms. The photoresist mask 46 is used to define the channel lengths of the N · channel and P · channel M0S elements, as shown in Fig. 13, and then dry etching is used to form a third silicon nitride layer 45 with good coverage and third is anisotropic. Good coverage of the polycrystalline silicon layer 44, forming a second polycrystalline silicon cushion layer 44a on both sides of the non-volatile memory device. 14 * This paper size is applicable to the national standard (CNS) A4 specification (210 X 297 mm). ) ------------ J Pack '------- Order --------- (Please read the notes on the back before filling this page) Intellectual Property of the Ministry of Economic Affairs Printed by the Bureau's Consumer Cooperatives 4 6 6 7 1 2 A7 ___B7__ 5. Description of the invention () and 44b, as shown in Figure 14 It should be noted that the width of the polycrystalline silicon pad layer is mainly determined by the thickness of the stacked good polycrystalline silicon layer. Therefore, the channel length of the 1-float floating gate element and the length of the control gate element can be individually miniaturized by controlling the thickness of the stacked good polycrystalline silicon layer. Via a photoresist mask (not shown), the source of lightly doped (1 igh 1 y doped) P-channel and drain diffusion region 48 can automatically align the implantation of boron impurities across the third silicon oxide layer 42a. , And then remove the photoresist. Using a temperature between 900 ° C and 105 ° C, the exposed third polycrystalline silicon is oxidized in a dry oxygen or water atmosphere to grow a polycrystalline silicon dioxide with a thickness of about 200 to 300 angstroms. The layers 50a and 50b are shown in Fig. 14. Then, using the photoresist 47 as a mask, the ONO layer 28 and the first polycrystalline silicon layer 27 are sequentially etched with active ions. As shown in Fig. 14, the photoresist 47. The photoresist mask 51, lightly doped source diffusion region 49 and drain diffusion region 52 of the N · channel MOS element and the non-volatile memory element are formed by implantation of phosphorus impurities, as shown in Figure 15 As shown, the implanted dose is about 1013 to 1 CMVctn2, and then the photoresist 51 is removed. The silicon nitride layer on the third polycrystalline silicon gate 44 of the N · and P-channel MOS device is removed by dry etching. 45a is removed, and then pre-oxidized in a dry oxygen environment, and grows about 100 to 150 angstroms of polycrystalline silicon dioxide layers 53a and 53b on the exposed polycrystalline silicon at a growth temperature of about 850 ° C to I05 (Between TC.) Using a low pressure chemical vapor deposition method, the tetraethoxysilane is reacted with ammonia gas at a temperature of about 750t, and the stacking thickness is about 500 to A third silicon nitride layer with a good coverage between 1,000 angstroms, and a third silicon nitride pad is formed on the side walls of the N- and P · channel MOS devices and non-volatile memory devices using anisotropic etching. Layer 54. Then, using a photoresist mask 56, the P-channel MOS element is highly dense. The paper size is in accordance with China National Standard (CNS) A4 (210 X 297 mm) ---------- --- Installation -------- Order --------- Pound (please read the idea on the back before filling out this page) Λ. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs B 6 7 1 2 A7 —_______ B7 V. Description of the invention () The implantation of boron ions in the degree of leakage and source diffusion region 55, as shown in Figure 16, the implantation dose is between about 1015 and 5x10H / cm2. Photoresist mask 5 7. The field oxide layer of the non-volatile memory element and the silicon dioxide layer on the lightly doped source diffusion region can be automatically aligned and aligned using buffered hydrofluoric acid, and then the photoresist is removed 5 7 Then, the exposed semiconductor surface is oxidized in a dry oxygen environment and a temperature of about 850 ° C to 105 ° C to grow a silicon dioxide layer 58 having a thickness of about 100 to 150 angstroms. Using a photoresist mask Screen 59, the arsenic ion implantation of the high-concentration source and drain diffusion region of the N · channel MOS element and the high concentration source / common source of the non-volatile semiconductor memory element and the drain diffusion region 60a and 60b is performed, as shown in FIG. The dose of arsenic ion implantation is about 101 5 to 5 X 105 / cm2, and then the photoresist 59 is removed. Use a common furnace tube or rapid annealing system in a nitrogen environment and a temperature of about 90 (TC to 100 tTC) Annealing 1 activates the dopants of ion implantation or removes the defects caused by ion implantation. At this time, the surface of the high-concentration source and drain diffusion region of all MOS devices and non-volatile semiconductor memory devices and the thin oxide layer on the polysilicon gate and the polysilicon control gate can be diluted by hydrofluoric acid or buffered hydrofluoric acid. The solution is removed by instant wet soaking or by anisotropic dry etching. Then, a titanium metal thin film with a thickness of about 500 to 1,000 angstroms is sputtered on the structure, and a rapid annealing at a temperature of about 600 ° C is performed in a nitrogen atmosphere to make the polycrystalline silicon and the single crystal silicon on the substrate. A titanium silicide (TiSl2) film 61 and a titanium nitride (TiN) film 62 thereon and a titanium nitride film 62 are formed on all dielectric layers, as shown in FIG. 19. Next, the photoresist mask 63 is used to selectively remove the titanium nitride film 62. The etching solution is ammonia water: hydrogen peroxide water: pure water in a volume ratio of 1: 1: 5. The paper size is in accordance with China National Standard (CNS) A4. (210 X 297 public love) I, install -------- order ---------, -f (Please read the precautions on the back before filling this page): ,, 671 ^: ,, 671 ^ Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs * 1 ^ A7 ____B7______ 5. Description of the invention () Then the photoresist 6 3 is removed, and the completed structure is annealed in an argon environment to reduce titanium silicide and nitride The resistivity of titanium is shown in Figure 20. Plasma-enhanced chemical vapor deposition (PECVD) or other low-temperature chemical vapor deposition methods are used to deposit a layer of a thick dielectric material 64 on the completed structure, such as boron-phosphorus-doped silicon dioxide (BPSG), and use The chemical-mechanical smoothing (CMP) method planarizes the entire structure. Then, use a photoresist mask to dig out the dielectric material (such as BPSG) that contacts the opening, and then remove the photoresist. Then, the dielectric material is flowed under 8503C. The process of rounding the opening below 3 is a multilayer connection, and the repeated process part will be omitted. Using sputtering or chemical vapor deposition, a thin layer of titanium nitride film 65 is deposited in the excavated contact hole with a thickness of about 100 to 200 angstroms as a barrier metal for the upper and lower metal connection or contact ( barrier metal), and has good adhesion to silicon oxide or other materials covered by it. Next, a tungsten metal layer 66 is deposited on the opening by a low pressure chemical vapor deposition method to serve as plugs that fill the opening. Tungsten metal can be obtained by reducing tungsten fluoride (WF6) in hydrogen at a temperature between about 2501 and 500 ° C. Then, the chemical-mechanical polishing method is used to remove tungsten and titanium nitride, and then a Ml metal film 67 having a thickness of about 5000 to 10,000 angstroms is sputtered, and the unnecessary metal film is removed by using a photoresist mask to complete the device. The metal connection 67 between M1 is shown in FIG. Multi-layer metal connections can be made by stacking intermediate dielectric layers, chemical-mechanical polishing, hole-controlling 塡 barrier metal layers, thorium tungsten plugs, chemical-mechanical polishing, wiring metal deposition, and lithographic etching. And repeat the above steps to get. Finally, a pavement protection (p a s s i v a t i ο η) layer is used to etch the bonding pads of the external wires, and the wafer manufacturing is completed. Here, the paper size is applicable to the Chinese national standard (CNS > A4) (210 X 297 mm) ------------ * Installation -------- Order ----- ---- Tsang < Please read the notice on the back before filling this page) 4. 6 6 7 1 A7 B7 V. Description of the invention () It should be noted that the above titanium metal can benefit other refracting metals ( refractory metal) instead, such as giant, diamond, molybdenum, etc .: The above-mentioned intermediate dielectric layer material may be chemical vapor deposited silicon dioxide or other low dielectric constant dielectric layers; the connecting metal may be aluminum, Aluminum alloy or copper metal "The connotations disclosed in Figures 12 to 21 show that non-volatile semiconductor memory elements that can be scaled to control the length can be obtained by controlling the thickness of the stacked good polycrystalline silicon layer Without having to consider the traditional minimum line width limitation. In addition, the present invention also uses an auto-aligned silicidation technology, which is not only used to reduce the connection resistance of the control gate of the non-volatile semiconductor memory element, but also the source buried resistance of the common buried layer is reduced due to silicidation. The connotation disclosed in Figures 3 to 21 is the use of a P-type substrate and a boron-doped channel forbidden region. However, those skilled in the art can also understand that the opposite dopant shape and state can also be used in the present invention. Furthermore, non-volatile semiconductor memory devices can also use the features of the present invention to manufacture P-channel non-volatile semiconductor memory devices on N-wells. Although the present invention is particularly illustrated and described with reference to the attached connotation, those skilled in the art can also understand that various modifications in various forms or details can be made without departing from the true spirit and scope of the present invention. n ft n 1 n---n ^^ 1 ^^ 1 ί ί I n I It-:-n-I nm IF nt ^ i I (Please read the notes on the back before filling this page) Intellectual Property of the Ministry of Economic Affairs Printed by the Bureau's Consumer Cooperatives δ This paper size applies to China National Standard (CNS) A4 (210 x 297 mm)