TW466407B - Multiple variable address mapping circuit - Google Patents

Abstract

The multiple variable address mapping circuit of the present invention includes at least one address mapping device for handling transition of the logical address and physical address of some field array in arrays; a mapping device selector for selecting which address mapping device the physical address adapts; and a control and interface circuit for setting contents of base moving register, logical base register, field length register and record length, and controlling actions of the control address mapping device and the mapping device selector.

Description

A7 466407 V. Description of the Invention (Field of the Invention) The present invention relates to a circuit for processing address mapping, especially for processing structural non-continuous address mapping, which can greatly reduce software address operations. [Background of the present invention] At present, the processor uses a single fixed-address-mapped access method for memory or peripheral access. When the hardware circuit is designed, the memory or peripheral access address is fixed. Some circuits use incomplete decoding techniques when decoding addresses, and only decode part of the address lines, so that the same peripheral or memory can correspond to different addresses, but under this technique, the arrangement of data at different addresses is identical. Some embedded processors have an address decoding circuit built into the processor. You can use the program setting method to specify the address of the connected memory or its surroundings, but all accesses are continuous address space. 2. Conventional technologies still use software-based address calculation to handle structural non-continuous address mapping, and a large increase in software-based address calculation. For frequent processing such as array data, it increases the load on the processor. _ [Outline of the present invention] The main purpose of the present invention is to provide a multiple variable address mapping circuit. When processing structural discontinuous data, hardware address mapping circuits replace a large number of software address operations. The secondary object of the present invention is to provide a multiple variable address mapping circuit, which can increase the portability of the program. Since the physical address can be mapped to the logical address, the programmer designs the main system copy Paper size applicable _ ^ 7 ^ ΓΑ4 size ⑵0 x 297 (please read the precautions on the back before filling out this page) · — I — II — Order ----- ii. Printed by the Intellectual Property Bureau Employees Consumer Cooperatives Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economics and Industry 466407 A7 --------------------- V. Description of invention (2) The logical address is used directly, only The mapping function of the address mapping circuit needs to be set during the initial setting, so the program can be quickly ported to different platform devices. Another object of the present invention is to provide a plurality of temporary registers in the address mapping circuit of the multiple variable address mapping circuit, so that the mapping function can be changed by changing the inner valley of the temporary registers. In order to achieve the above object, the multi-variable address mapping circuit of the present invention mainly includes at least one address mapper, which is used to convert the input logical address and the output physical address of a shelf array in the expensive processing array; A mapper selector, which set of address mappers are used to select the physical address of the output; and a control and interface circuit for setting the substrate displacement register, the logical substrate register, and the bit length register. It also records the contents of the length register I and controls the actions of the address mapper and the mapper selector. The address mapper includes a base shift register, a logical base register, a block length register, a record length register, a subtractor, a division / remainder generator, a multiplier, and an adder. Since the present invention does have an enhanced effect, an invention patent is applied for in accordance with the law. [Figure · Simplified description] Figure 1 is a block circle embodiment of the multiple variable address mapping circuit of the present invention. The second figure is § ignorance. The present invention is applied to an example of data access in an array. FIG. 3 is a block diagram embodiment of the address mapper circuit according to the present invention. FIG. 4 is a circuit block diagram embodiment of a mapper selector according to the present invention. FIG. 5 is an embodiment of the ohm gate mask circuit of the present invention. Fig. 6 is a block diagram embodiment of the control and interface circuit of the present invention. This paper size applies to China National Standard (CNS) A4 (2K) X 297 Office M) (Please read the precautions on the back before filling this page > I ------- 1 Order · ------ I— «

466407 -------- V. Description of the invention (3) [Illustration of drawing number] Multiple variable address mapping circuit 10 Base shift register 2 1 Block length register 2 3 Subtractor 2 5 Multiplication 2 7 Mapper selector 30 0 R Gate mask circuit 3 2 Priority encoder 3 4 Control and interface circuit 4 〇 Input logical address 5 1 Memory 9 1 Address bus 9 3 Address mapper 20 Logic Base register 22 record length register 24 division / remainder generator 26 adder 2 8 address group decoder 3 1. Mapped area address mask register 33 multiplexer 35 output / input decoder 4 1 Output entity address 5 2 I / O device 92 Data bus 94 ------- I ------ Install -------- Order. (Please read the 意 Note on the back first Refill this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economics [For detailed description of the preferred embodiment, please refer to FIG. 1 for a block diagram of the multiple variable address mapping circuit i 0 of the present invention. • For the multiple variable address mapping circuit 10, the input logical address 5 1 refers to the address identified by the computer's processor or motherboard address bus 93 (LOGicai Address Bus), and the output physical bit Address 52 (Physical Address) is the multi-variable address mapping circuit 10, which is the address converted from the input logical address 5 1 and the output physical address 5 2 is being sent to the memory 9 1 or the input / output device. 9 2 address signal. The correspondence between the input logical address 51 and the output entity address 5 2 is variable, and it can be continuous or discontinuous. As shown in Figure 丨, there are five sets of address mapping. The paper size is applicable to the Chinese National Standard < CNS) A4 specification (210 X 297 to Edinburgh, ϋ Ό 4 Ο 7

Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (4) The transmitters 20a, 20b, 20c, 20d, 20e (Addr Mpper), each address mapper 20 can set the mapping method individually. , Map the virtual input logical address 5 1 to the output physical address 5 2. For example, if you want to output the physical address 52, such as 4000, 4008, 4016, 4024, 4032, etc., to the logical address 0, 1, 2, 3, 4, 5, etc., you can set the address mapper 2 〇 & is as follows: Address mapper 20a: PA = F1 (LA), Fl (x) = 4000 + (x) * 8 and set the mapper selector 30 (Mapper Selector) to CS0 is to use the address mapper 20a, when the processor is accessing the input logical address 5 1: 0, 1, 2, 3, ... etc., 'the actual access to the output physical address 5 2: 4000, 4008, 40 1 6, ... and so on data. For the memory 91 or the input / output device 92, there can be multiple correspondences between logical addresses (also called virtual addresses) and physical addresses. That is, multiple address functions, and each address can be addressed differently. As shown in FIG. 1, the address bus 9 3 of the external processor (ie, Logical Addr. Bus, LA) can pass through three sets of address mappers 20 a, 20 b, and 20 c of the multi-variable address mapping circuit 10. Use three different mapping methods to convert to physical address (PA) of memory (Memory) and access memory data. The I / O device 92 uses two sets of address mappers 20d, 20e. Address mapper 20a: PA = F1 (LA) Address mapper 20b: PA = F2 (LA)

Address mapper 20c: PA = LA FI, F 2, is a different mapping function, while address mapper 2 0c does not perform any conversion. This paper size applies to China Solid National Standard (CNS) A4 specification (210 X 297 sign cents) (Please read the precautions on the back before filling this page) -14 ^ · ------- Order · ---- ---- Consumption Cooperation by Employees of Intellectual Property Bureau of the Ministry of Economic Affairs, printed by A 〇6 4 0 7 A7 --- B7 V. Description of the Invention (5) Through different mapping function settings, memory 91 can be mapped to output / input The device 92 address range or the I / O device 92 is mapped to the memory 91 range.

The user can use the address area mapping method to map different address spaces to different mappers, such as address 〇00 〇 · 3 fff automatically use the address mapper 20a, 4000-BFFF does not do any mapping, COOO -DFFF uses the address mapper 20b, F000-FFFF uses the address mapper 2 0c. · The conversion of the above logical address and physical address is made by hardware circuit, which can save a lot of software calculation and access time. For example, when dealing with structural discontinuous data, a large number of software address operations are replaced by hardware address mapping circuits. Assume that you want to access the data in the addresses 4000, 4008, 4016, 4024, 4 〇3, _ · _, take the following simple address conversion function as an example: F1 (x) = 4000 + (x) * 8 When the software calculates the address, it needs to do a multiplication or shift operation and an addition operation. The following is the instruction to save and fetch in 80 x 8 6 combination language. The instructions required are as follows: MOV Βχ, χ SHL BX, 3; Multiply 8 ADD BX, 4000 MOV AX, [BX] If the function is more complicated, more operations are required. If it is accessed by this technology, after the setting of Addr Mapper, only the following instructions are needed to complete this paper size. Applicable to China National Standard (CNS) A4 specification (210 X 297 mm) ----- ----- --- ^ \ ^ i I ---- 1 ------- '^ ί {Please read the notes on the back before filling this page) A7 B7 466407 V. Description of the invention (έ >) MOV ΒΧ, χ MOV AX, [BX] If it is more complicated, such as the content data of 20-bit address and 3-bit address, you can also use this circuit to complete access. This will save a lot of time when accessing a large amount of data using the loop (100p). In addition, the present invention can also increase the portability of the program. Since the physical address can be mapped to the logical address, the red type engineer uses the logical address directly when designing the main system program. , Set the mapping function of the address mapper 20, so you can quickly port programs to different platform devices. In order to explain the characteristics of this technology, please refer to FIG. 2 for an example of the present invention applied to data access in an array. For example, the name A (Name A) data of Table A (Table A) is fetched into Table B (Table B). For example, in the column of Customer B (CustomB): At the address 4 00 h, there is a set of multi-block data τ ab 1 ea, and Table A has three sets of fields. The block name and field length are n respectively. 〇a occupies 4 bytes, NameA occupies 16 bytes, and NIDA occupies 8 bytes. In addition, at the address 600Oh, there is another set of multi-column data TableB, TableB has two fields, SIDB occupies 4 bytes, Custo omb B occupies 16 bytes.

NameA starting address: 4000h + 4 + (ICh * i), j = 〇, 1, 2, ... (丨 represents the number of columns), the starting address of each NameA is 4004h, 4020h, 403 ch, 405 Bh,. ...

CustomB starting address: 6000h + 4 + (14h * j), j_〇, 1, 2, ..._ (j represents the number of columns) 'The starting address of each CustomB is the paper standard applicable to the Chinese National Standard (CNS) A4 Specification (210 X 297 1¾) ------------- ^ -Installation --------- Order--III I --- Please read the precautions on the back first Fill out this page} Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy 46640 7 A7 ___B7 V. Invention Description (7) 6004h, 601 8h, 602ch, 6040h, ... The starting address and width of any field in each Table can be expressed by the following formula:

Addr_start = Base + FieldOffset + η * RecordLen = (Base + FieldOffset) + n * RecordLen The parameters are as follows:

Base: The starting address of the table, such as Tableh is 4000h, TableB is 6000h

FieldOffset: the displacement of the block in the data, the displacement of each column of TableA and TableB is as follows:

NoA: 0, Name A: 4, NID A: 14h SIDB: 0, CustomB: 4

RecordLen: the length of each data, in TableA is ICh, TableB is 14h. To access the address of all data in this column as continuous data, the formula is modified and modified as follows: Formula (1): S [x]- (Base + FieldOffset) + INT (x / FieldLen) * RecordLen + (x mod FieldLen), where: x is the displacement 资料 of the data in the logical array S.

FieldLen: Wide. The FieldLen of each block is as follows: NOA: 4, NameA: 10h, NIDA: 8 SIDB: 4, CustomB: 10h This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 I centimeters) — — — — — — — — --- L-Outfit! Order_1 ------- Good (please read the note # on the back before filling this page) A7 466407 _15. Description of the Invention (Name) Now suppose that Tab 1 e A has η records. The traditional software way to copy this field, the program virtual code snippet is as follows char * ptr A, * ptrB; unsigned long tempA, tempB, count, x, η; tempA = Base (TableA) + F ie 1 d O f fs et ( Nam e A); tempB = Base (TableB) +

FieldOffset (CustomB); count = n * FieldLen (NameA); for (x = 0; x <count; x + +) {ptr A = (char * U tempA + (int) (x L FieldLen (NameA)) * RecordLen (TahleA > + (x% FieldLenfNameA))); ptrB = (char * UtempB + fint Π \ /

Field LenfCustomB)) * Record Len (TahleB) Ten fx% FieidLen (CustomB) ^; * ptrB = * ptr A;}. The bottom line of the code in the above program, if it can be calculated in hardware, we can simplify the above for loop program ptrA = VbaseA; // VbaseA is the logical starting address of the NameA field ptrB = VbaseB; // VbaseA is the logical starting address of the CustomB block count = η * F ie 1 d L e η (N am e A); This paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) I ^ — — — — — — — — — — I 111 [1] 1 ^ OJ— — — — — — — (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed 466407 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed A7 B7 V. Invention Description (q) for (x = 0; x <count; x + +) {* ptrB + + = * ptr A ten +} The present invention uses a hardware method to achieve the purpose of this fast operation. 'As the present invention accesses non-continuous array data, Quite useful, to achieve the purpose of the examples given above, address mapping For an example of a block diagram of 0, please refer to FIG. 3. For the fractional formula represented by the block diagram of the address mapper 20, refer to the above formula (1): According to the foregoing formula (1): S [x] = ( Base + FieldOffset) + INT (x / FieldLen) * RecordLen + (x mod FieldLen), where: X is the displacement of the data in a certain logical array s (such as the Tab 1 e A's Name A stop array) 値Therefore, it can be used as an array index; S [x] is the output entity address 52; the input logical address 51 of the logical array S is represented by SBase + X, where S base represents the field of the meta record and the address is delineated to be used for address mapping. The starting logical address' so X can be calculated, that is, the input logical address 5 1 _ Sbase 〇 address misser 2 0 uses the following registers to store related parameters: base displacement register 2 1, record The stop array is the starting physical address of the address mapping, that is, Base + Fieid〇ffset 値 'In the above embodiment, it is 4 00h + 4 = 4 0 4 h; the logic base register 2 2. Record the starting logical address of the field array to be mapped, that is, Sbase, for example, set to cOOh or (Depending on the address line entered is the complete address line C 00h or only this paper size applies Chinese National Standard (CNS) A4 specifications (210 X 297)) " ~ ------ c please Read the notes on the back and then fill in this page) Binding: 466407 A7 _______B7 _ V. Description of the invention () (Please read the notes on the back before filling this page) Low-order address part depends); if the logical address array The starting address starts from 20000 or the effective lower-order address taken is 0 (for example, the starting address of the logical address array is C000h, but because only the lower-order 12 address lines are used, the address passed in 〇〇〇〇), the circuit does not need the logic base register 22 and subtractor 25; field length register 23, record the length of the array, that is, FieldLen 値, in the above embodiment is 1〇 h: the record length register 24, which records the length of the array, that is, Rec 0rd Le e η 値, in the above embodiment] ch; the address mapper 20 is completed by the following mathematical operator: The subtractor 25 subtracts the input logical address 51 and the logical base address stored in the logical base register 22 The calculation of the method is to find the array index X = input logical address 5 1 _ sbase. For example, if the input logical address 51 is c〇04h, then χ = C004h — C〇〇〇h = 4 ° Intellectual Property Bureau of the Ministry of Economic Affairs The employee consumer cooperative prints the division / remainder generator 26, and divides / remainders the output of the subtractor 25 and the length of the field stored in the field length register 2 3, so that INT ( x / FieldLen) 値 of the quotient 1 and (X mod FieldLen) of the remainder. For example, X = Uh 'then find the quotient 値 = 1 and the remainder 値 = 2 multiplier 2 7 and the length of the array stored by the record length register 2 4 and the quotient of the division / remainder generator 2 6 The output is multiplied, that is, the 値 of INT (x / FieldLen) * RecordLen is obtained, for example, x = i2h and quotient 値 = 1 'multiplier output = ICh. This paper size applies to China National Standard (CNS) A4 (210 x 297) printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 6 640 7 A7 B7 V. Description of the invention (II) Adder 2 8 to temporarily store the base displacement The starting entity address stored by the generator 21 is divided by the remainder output of the division / remainder generator 2 6 and the output of the multiplier 27 is added to obtain the output entity address 5 2, that is, S is obtained. [X], for example, the input logical address 5! Is C012h, and the output entity address 52 is 4022h. From the above, as long as a logical address is passed in, the circuit can output the corresponding physical address. Within this logical address range, ‘processors can access data continuously or randomly. No need to do complicated software address calculation. And as long as the contents of the base displacement register 21, the logical base register 22, the field length register 23 and the record length register 24 are changed, the mapping function can be changed. In the embodiment of FIG. 2 above, since it is required to obtain the physical address of the NameA field of τ ab 1 e a and the physical address of the CustomB block of TableB, it is better to use two address mappers 20. FIG. 4 is a circuit block diagram of the mapper selector 30. The main function is to decode the block address Bank Address (that is, the high-order address line of the input logical address 51) through the address group decoder 31, and according to the decoding result and the mapping area address mask register 33 (Bank The contents of the Mask Register) determine the selected address mapper 2 0. The circuit description is as follows. The block address is decoded by the Address Group Decoder 31 (Address Bank Decode). X 〇 to X m represent different decoding ranges. For example, decoding to 〇 〇 _ 0 f ff will make X. For 1 ′ XjjXm it is 0. 1000-1 f f f will make X ^ 1 and others 0, and so on. These pins will be sent to multiple sets of OR gate mask circuit 32 (MASK OR). This circuit is the bit corresponding to the output of the address mask register 3 3 of the mapping area and the output of the address group decoder 31 1 The yuan first performs a logical AND operation, and then performs an OR operation on the outputs together. This is used to control the size of this paper to Chinese National Standard (CNS) A4 (210 X 297) (please read the precautions on the back before filling this page)

C 466407 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (12) Which B a n k decoding addresses can be sent to the output of z. For example, set the address YG, Y] and I of the mask register 33 in the mapping area! , Set to 0, which means that the three address decoding ranges of X0, Xι, and X2 are valid, and the rest are invalid. Once the address range falls within any of X ^ XhX2, the z output becomes i, otherwise it is 0, and the OR gate circuit 32 is shown in Figure 5. Each address mapper 20 will have a mapping area address mask register 33 and an OR closing circuit 32. If there are three address mappers 20, there will be three mapping area address mask temporary storages. Mang 33 and three OR gate mask circuits 32. The output of each OR gate mask circuit 32 will be sent to a priority encoder 34 (Priority Encode), which will be encoded in a priority manner. For example, if the output of Z2 is 1, the remaining inputs are 0, then the priority encoding The output of the device 34 is two. If more than two sets of inputs are 丨 at the same time, the outputs are coded according to the priority order. The multiplexer 35 determines the selected address mapper 20 according to the output of the priority encoder 34, and outputs the physical mapping address of the set of mappers. When the output of the priority encoder 34 is 0, the output address is the input address, and the circuit does not perform address mapping conversion. FIG. 6 is a block diagram embodiment of a control and interface circuit 40 ((: 〇ntr〇1 & Forward) in the present invention. The control and interface circuit * 〇 is used to set and access the address mapper 20 And the data of the internal register of the mapper selector 30 'output / input decoder 41 (10 Decoder) is used to decode the address of each register for access. The data buffer 42 (Data Buffer) The data of the data bus 94 (Data Bus) is stored in the temporary register, or the register data is sent to the external data bus 94. This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 meal) (谙 Please read the notes on the back before filling in this page). '· Nn I n ϋ n A7 466407 V. Description of the invention (8) It should be noted that the above is only an example, not a limitation. Those who do not depart from the basic structure of the present invention should all be the scope of rights claimed by this patent, but should be based on the scope of the patent application. ------------ 1 ' --- Order —------- ^ (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper uses the Chinese National Standard (CNS) A4 size (210 X 297 centimeters)

Claims (1)

AS BS C8 D8 466407 6. Scope of patent application 1. A multi-variable address mapping circuit that receives the input logical address of a field array in the array data and processes it as an output physical address. The multiple variable address mapping circuit includes: at least one address mapper, which is responsible for processing the conversion of the input logical address and the output physical address of a field array in the array, wherein the at least one address mapper includes: Base displacement register, which records the starting physical address of the field array for address mapping; Logical base register, records the starting logical address of the field array for address mapping; Block length Register, the length of the array of redundant bits; δ recorded length register, which records the length of the array; subtracter, which subtracts the input logical address from the logical address stored in the logical base register Operation: Divider / residual generator, divide / remainder output and the length of the field stored in the bit length register to divide / remainder;. Multiplier, record the length register The length of the stored array and the quotient output of the division / remainder generator 乘 multiply; the adder 'will store the starting physical address stored in the base shift register, the remainder output of the division / remainder generator, and The output of the multiplier is added to obtain the output entity address; the mapper selector, which set of address mappers are used to select the physical address of the output; and the paper standard is applicable to the Chinese National Standard (CNS) A4 specifications (210 X 297 ¢ 6¾) -------------- install --- < tf.Tt Read the notes on the back and fill out this page) Order. Line _ Intellectual Property Bureau of the Ministry of Economic Affairs ABCD 466407 printed by the employee's consumer cooperative. 6. The patent scope control and interface circuit are applied to set the base displacement register, logical base register, field length register, and record length register. Address mapper and mapper selector. 2. The multiple variable address mapping circuit described in item 1 of the scope of patent application, wherein the number of address mappers is plural. '' 3. The multiple variable address mapping circuit described in item 丨 of the patent application scope, wherein the control and interface circuit includes an output / input decoder for decoding a substrate displacement register, a logic substrate register, and a stop The length register uses ^ and the address of the brother record length register for access. 4 types of multiple variable address mapping circuits, which receive an array of fields in the array data (input logical addresses and process them as output physical addresses. The multiple variable address mapping circuits in its address mapper include: at least one An address mapper is responsible for processing the conversion of the input logical address and the output physical address of a certain array in the array. The at least two address mappers include: a base shift register to record the block The array is the starting physical address of the address mapping; the field length register, records the length of the block array; the 'record length register' records the length of the array · division / remainder generator, will subtract Divide / remainder operation with the output of the register and the length of the field stored in the block length register; a multiplier that divides the length of the array stored by the C record length register with the quotient of the division / remainder generator The output is multiplied; this paper size is applicable to China National Standard (CNS) A4 (210 X 297 1¾) ------------ install --- (Please read the precautions on the back before (Fill in this page), A8 B8 C8 D8 466407 printed by the Employees' Cooperative of the Intellectual Property Bureau of the Ministry of Finance The operation of addition to get the round: the mapper selector, the physical address of the negative output is the address mapper using =, and the control and interface circuit to set the substrate displacement register, the logical substrate temporary storage Register, block length register and record length register two, and control the action of the address mapper and mapper selector. 5. Multiple variable address mapping circuit as described in item 4 of the scope of patent application Among them, the number of address mappers is plural. 6. The multiple variable address mapping circuit as described in item 4 of the patent application park, wherein the control and interface circuit includes a round-out / entry decoder for decoding the base. The address of the displacement register, the logic base register, the block length register, and the C green length register for access. ----- I ------ 农 --- ( Please read the notes on the back first (Fill in this page again) Order · _, line. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, paper towels, household products. (3nS) A4 Na⑵. X 297 ~ ^ y