TW465127B - Semiconductor light emitting device - Google Patents
Semiconductor light emitting device Download PDFInfo
- Publication number
- TW465127B TW465127B TW089119840A TW89119840A TW465127B TW 465127 B TW465127 B TW 465127B TW 089119840 A TW089119840 A TW 089119840A TW 89119840 A TW89119840 A TW 89119840A TW 465127 B TW465127 B TW 465127B
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- buffer layer
- emitting device
- semiconductor light
- patent application
- Prior art date
Links
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- OZTVKGRKOWIYRK-UHFFFAOYSA-N gallium palladium Chemical compound [Ga].[Pd] OZTVKGRKOWIYRK-UHFFFAOYSA-N 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910021478 group 5 element Inorganic materials 0.000 description 1
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- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
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- UJXZVRRCKFUQKG-UHFFFAOYSA-K indium(3+);phosphate Chemical compound [In+3].[O-]P([O-])([O-])=O UJXZVRRCKFUQKG-UHFFFAOYSA-K 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/16—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/30—Structure or shape of the active region; Materials used for the active region
- H01S5/34—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers
- H01S5/343—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser
- H01S5/34326—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser with a well layer based on InGa(Al)P, e.g. red laser
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S2301/00—Functional characteristics
- H01S2301/17—Semiconductor lasers comprising special layers
- H01S2301/173—The laser chip comprising special buffer layers, e.g. dislocation prevention or reduction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/30—Structure or shape of the active region; Materials used for the active region
- H01S5/32—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures
- H01S5/3202—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures grown on specifically orientated substrates, or using orientation dependent growth
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Optics & Photonics (AREA)
- Led Devices (AREA)
- Semiconductor Lasers (AREA)
Abstract
Description
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發明背景 1 發明镇域： 本發明係關於一種半導體發光裝置，例如一發光二極體 、一半導體雷射裝置、或類此者。較特別的是，本發明係 關於一種半導體發光裝置，其中由—铭鎵麵鱗型半導體材 料製成之發光段係製成於一鎵砰基材上。 2.相關技藝説明： 使用一館鎵銦磷型半導體材料做爲可見範園内之發光裝 置I半導體裝置優點在於例如可取得一鎵砷基材與鋁鎵銦 磷型半導體材料之間之晶格匹配，及在族出々化合物半導 體材料之間具有最大之直接轉變，使用此一材料之習知半 導體裝置包括發光二極體、半導體雷射裝置、及類此者。 雖然一链鎵銦磷型半導體層係利用_M0Cvd (有機金屬 化學氣體沉積）方法或一 MBE (分子束磊晶）方法以磊晶式生 長於一鎵砷基材上，但是其必須取得一要求之結晶度，即 —雜質例如氧係未導送入及取得一要求之二維式生長。 由此以觀’第6-57149號曰本先前公告案揭露一種如圖9所 示之習知德鎵銦磷型半導體雷射裝置，其中一鋁鎵銦磷層 生長於一鎵砰基材81之一平面上，基材之主平面係自（1〇〇) 平面傾向[011]方位。 在此方法中，首先一 η-鎵銦磷或η-銘鎵銦嶙緩衝層§2、— η-铭鎵鋼磷鍍層μ、一鎵銦磷主動層S4、鋁鎵銦磷緩層 85、及一ρ-鎵砷帽蓋層86係利用一MOCVD方法依此順序生 長於η-鎵砷基材81上，基材_之主平面係自（丨〇ρ)平面傾向 -4 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） C請先閱請背面之注意事項再填寫本頁} 裝 i ---· II — 訂_ !'·^^; · -.、 一 tt:J* 465 12 7 A7 -—--- -B7_____五、發明說明（2 ) [oil]方位。随後，一二氧化矽（Sl〇2)膜87製成於严鎵砷帽蓋 層86上，且二氧化矽之中央部分係蝕刻成長條狀。—電^ 811製成於二氧化矽膜S7上，及一電極81〇製成於&鎵砷基 材8 1之相反側。 在製造一半導體雷射裝置之此習知方法中，一鎵銦磷或 銘鎵銦磷緩衝層係生長於一鎵砷基材之主平面上，主平面 係自（100)平面傾向[Oli]方位，隨後以一 MOCVD方法生長 一鋁鎵銦磷型發光段。 惟’基於以下理由，在此方法中將鎵坤基材之主平面自 \ (100)平面傾向[〇H]方位之效果並不足夠。第一，鎵銦磷或 链鎵銦磷緩衝層並非直接生長於鎵砷基材上、第二，緩衝 層僅用單一组合物。 發明概述 依本發明之一内容所示，其提供一種半導體發光裝置， 至少包括：一鎵砰基材，其主平面係自一（1{)0)平面傾向一 [oil]方位；一 AlxGaHAsfOgxSl)第一缓衝層，係提供於 鎵砰基材之主平面上；一 AlyGa2lni_yjP 第二缓衝層，係提供於第一緩衝層上；—AlsGatIni stP (〇s SS1且Ostgl)第一鍍層，係提供於第二緩衝層上；—主動 層，係提供於第一鍍層上；及一第二鍵層，係提供於主動 層上’其中第一鍍層之一鋁含量S係高於第二緩衝層之一銘 含量y。 在本發明之一實梅例中，鎵砷基材之主平面係以一等於 或大於大約2。之角度？而自（100)平面傾向[011]方位。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐〉 4 65 1 2 7 A? __________B7___________ 五、發明說明（3 ) 在本發明之—實施例中，第二缓衝層之鲜^量y係等於或 大於大約〇·3，且小於或等於大約0.8。 在本發明之一實施例中，第二缓衝層之生長溫度係不同 於第一緩層者。 在本發明之一實施例中，第二緩衝層之生長溫度係等於 第一鐵層者。 在本發明之一實施例中，第一缓衝層之生長溫度係等於 第二緩衝層者。 在本發明之一實施例中，第二緩衝層係在以一階級方式 或連續性方式改變—生長溫度時生長。 在本發明之一貫施例中，第一鍍層係在以一階級方式或 連續性方式改變一生長溫度時生長。 在本發明之一實施例中，半導體發光裝置進一步包含— 電流擴散層於第二鍍層上。 .在本發明之一實施例中，半導體發光裝置進一步包含— 電流阻斷層於第二鍍層與電流擴散層之間。 在本發明之一實施例中，電流阻斷層係提供於半導體發 光裝置之一.中央部分。 在本發明之一實施例中，電流阻斷層係提供於半導體發 光裝置之一_周邊部分= 在本發明之一實施例中，主動層係藉由交錯型式沉積多 數量子井層及多數障壁層而取得之一量子井主動層。 在本發明之一實施例中，半導體發光裝置進—步包含— 電流阻斷層於第二鍍層上，及包含一帽蓋層於電流阻斷層 -----------裝.！ (蹐先閲讀背面之注意事項'月填窝本頁) 訂 • 6 - A7 B7 465 12 五、發明說明（， 上。 在本發明之—余 光反射層，其心 體發光裝置造一步包含一 依太、、’、目關於第一鏟層而提供較接近於鎵神基材。 法以製-止一束另—内谷所不，其提供一種透過一氣態沉積 切體發衫置於―料基材主平面上之方法 ' :基材〈主平面係自_(1〇〇)平面傾向一[_方位，該 万法包含以下毋膙 „ a 步驟，（a)生長—A1xGai.xAs (osxsi)第一缓 衝層於鎵砷基材 < 1 〇 王千面上，（b)生長一 AlyGaJr^^P (Ogy :〇Szsi)第二缓衝層於第一緩衝層上；及（〇依序生長 s (〇SsS丨且“以〇第—鍍層於第二緩衝層 上、生長一主動層於第一鍍層上、及生長一第二鍍層於主 動層上’其中第-鍍層之-鋁含量s係高於第二缓衝層之一 無含量y。 在本發明之一實施例中，步驟（a)係以大約6〇〇至7〇〇。〇之 間之生長溫度進行；步驟（b)進行時並自大約600至700。〇 义間心生長溫度昇高至大約700至85(rc之間之—溫度；及 步驟（C)係以大約700至850。〇之間之一生長溫度進行。 在本發明I 一實施例中，氣態沉積法係—有機金屬化學 氣體沉積（MOCVD)方法。 在本發明之一實施例中’氣態沉積法係一分子束磊晶 (MBE)方法。 在本發明之一實施例中，鎵砷基材之主平面係以一等於 或大於大約2。之角度，而自（1〇〇)平面傾向[〇11]方位。 在本發明之一實施例中，第二緩衝層之鋁含量y係等於或 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公爱） (請先閲讀背面之注意事炎月填寫本頁) r-裝 --II 訂·!---·Ι·^Τ . 4 651a 7 A7 -- -- -S7 _ ------------ 五、發明說明（5 ) 大於大約0.3，且小於或等於大約0.8。 在本發明之一實施例中，步驟（b)之一生長溫度係不同於 步驟（c)者。 ' 在本發明之一實施例中’步驟（b)之一生長溫度係等於步 驟（c)中之第一鍍層者。 在本發明之一實施例中，步驟（a)之一生長溫度係等於步 驟(b)者。 在本發明之一實施例中，步驟（b)係在以一階級方式或連 續性方式改變一生長溫度時進行。 在本發明之一實施例中，步驟（C)中之第一鍍層係在以〆 階級方式或連續性方式改變一生長溫度時生長。 在本發明之一實施例中，一電流擴散層係提供於第二鍍 層上。 在本發明之一實施例中，一電流阻斷層係提供於第二鍍 層與電流擴散層之間。 在本發明之一實施例中，電流阻斷層係提供於半導體發 光裝置之一中央部分。 在本發明之一實施例中，電流阻斷層係提供於半導體發 光裝置之一周邊部分。 在本發明之一實施例中，主動層係藉由交錯型式沉積多 數量子井層及多數障壁層而取得之一量子井主動層。 在本發明之一實施例中，一電流阻斷層係提供於第二鍍 層上，及一帽蓋層係提供於電流阻斷層上。 在本發明之一實施例中，一光反射層係相關於第一鍍層 本紐尺度適財國國家標準（c"NS)A4規格（21G X 297公楚） ^ 465 12 7 a? _ B7 五、發明說明（6 ) 而提供較接近於嫁神基材。 在本發明之一實施例中，一生長溫度係在步騍（b)後昇高 ，及隨後進行步驟（c)。 本發明之功能將説明於後β 鎵砰基材之主平面係自（1〇〇)平面傾向[〇11]方位，因此氧 較不易進入欲生長於其上之鋁鎵銦磷型半導體層，藉此取 得一要求之結晶度。爲了充_含嶺^此效果，較佳爲主平面 係以一等於或大於大嚓2。冬角—度。在此一傾斜之主平 面上製成AlxGakAs (0 s X s 1)第—缓衝層，因此，雜質自 基材萆發、光扈之擴散IP啓到抑制，且基材表面之平坦度改 善’吒凹凸不平減少。當然，傾斜平面之方位不變。不同 於習知鎵銦磷-或鋁鎵銦磷缓衝層的是，本發明之鎵砷或鋁 鎵珅皐Θ緩衝層其有相同於基材者之.组合J逾，因此，凹凸 不平不會導送至其間之結舍养，且其可生長一具有少量瑕 疵<緩衝層於其上，且一要求之結晶度與傾斜平面之方位 不變》再者，鋁鎵銦磷第一鍍層係經由鋁鎵銦磷（或鎵銦磷） 第二緩衝層而提供於鋁鎵砷（或鎵砷）第一緩衝層上，.結果， 發光段特別是主動層者之結晶度可大幅改善，藉以改善放 士效率另者，一包括一或多層之鋁鎵銦磷（或鎵銦磚）缓衝 層結構可提供於鋁鎵砷（或鎵砷）第一緩衝層上。 依本發明所示，第二緩衝層之鋁—含量v係高於第一鍍層之 鋁含量S，結果其可取得一半導體發先奘署，其中發光上特 別是f動層者之結晶度太幅改善，藉以改基放射效，。例 如，畲-具有高銘含量之艘層直接生長於_嫁坤（或銘嫁 (請先閱讀背面之注意事項再貧寫本頁) :* 裝 ----!|訂"！-----. ΛΙ--. -9- ”4 65 1 2 7 A7 --— _ B7 五、發明說明（7 ) 緩衝層上時，則無法取得一要求之結晶度。惟，在本發明 中，當具有低鋁含量之第二緩衝層先生長於鎵砷（或鋁鎵砷） 缓衝層上時，隨後具有高鋁含量之第—鍍層生長於第二緩 衝層上，即可取得一改善之結晶度。另者第二緩衝層及/或 第一鍍層之組合物可逐漸改變，組合物之改變可爲階級式 或連續式。 第二缓衝層之鋁含量y係等於或大於夭約〇 3，，且小於或等 於大约'0.8。在此一例予中，其可取得一丰導體發光裝置， 其中發光段特別是主動層者.之結晶度大幅改善，藉以改善 放射效率。 第二緩衝層之生長溫度可不同於第—鍍層者，例如具有 一高链含量之鍍層（即第一鍍層）可以較高生長溫度生長，而 具有一低铭含量之缓衝層（即第二緩衝層）可以較低生長溫度 生長’因爲具有一高鋁含量之鋁鎵銦磷層理想生長溫度較高。 第一缓衝層之生長溫度可逐漸改變，例如第二緩衝層可 在生長期間自鎵砷（或鋁鎵砷）第—缓衝層之理想生長溫度昇 鬲生長溫度至鋁鎵銦磷（或鎵銦磷）第二緩衝層之理想生長溫 度，在此一例子中，結晶度可進一步改善，同樣地，第一 鍍層之生長溫度可逐漸改變。 ' 二电流擴.散i可提供於第二鏡層上，在此例子中，注入 之電流可擴散通過電流擴散層，以利有效地使用整個主動 層發光，藉以大幅改善放射效率ώ 一電流阻斷層可提供於第二鍍層與電流擴散層之間，在 -10- (請先閱讀背面之注意事項再填寓本頁) 厂-裝！-----tr— I—丨· 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公変） 4 651 2 7 A7 -B7 經濟部智慧財產局員工消費合作江印製 五、發明說明（8 ) . 此例子中，’/王入之電流可擴散通過電流擴散層，以利有效 地使用整個主動層發光，藉以進一步改善放射效率。 電流阻斷層可提供於半導體發光裝置之一中央部分，在 此例子中，其可將注入之電流擴散趨向裝置之周邊部分且 有效地將所生之電流抽離裝置，藉以大幅改善放射效率。 另者，電流阻斷層可提供於半導體發光裝置之一周邊部分 ’在此例子中，其可定位電流於裝置之中央部分，藉以二 大電流密度且有效地將所生之電流抽離裝置，藉以大幅改 善放射效率。 一光反射層係相關於第一鍍層而提供較接近於鎵砷基材 ，在此例子中，由基材吸收之一部分所生光線可由光2射 .層反射，因此其可自裝置抽離，藉以大幅改善所生光線之 使用效率。 本發明.可藉由提供一電流阻斷層及—帽蓋層於第二鍍層 上，而提供一半導體雷射裝置。 因此，文内揭述之本發明優點爲提供—半導體發光裝置 ’其包括一鎵砷基材，基材之主平面係自（100)平面傾向 .[011]方位且具有所需結晶度之銘録銦鱗型半導體層生 長於此主平面上，藉以大幅改善放射效率。 本發明之.上述及其他優點將可由習於此技者審讀與瞭解 以下詳細説明及參考相關圖式後得知。 圖式簡單説明 圖1A至1D係截面圖，説明依本發明實施例叉製成—半導體 發光裝置之方法； 寸 -11 - (請先閱讀背面之注意事項#/^.寫本頁)BACKGROUND OF THE INVENTION 1 Town of Invention: The present invention relates to a semiconductor light emitting device, such as a light emitting diode, a semiconductor laser device, or the like. More specifically, the present invention relates to a semiconductor light-emitting device, in which a light-emitting segment made of a gallium-faced scale-type semiconductor material is made on a gallium substrate. 2. Relevant technical description: The use of a Gallium Indium Phosphorus semiconductor material as the light emitting device in the visible range. The semiconductor device has the advantage that, for example, a lattice match between a gallium arsenic substrate and an aluminum gallium indium phosphorus semiconductor material can be obtained. And has the largest direct transition between the family of compound semiconductor materials. Conventional semiconductor devices using this material include light emitting diodes, semiconductor laser devices, and the like. Although a chain of gallium indium phosphorus type semiconductor layer is epitaxially grown on a gallium arsenic substrate using the _M0Cvd (Organic Metal Chemical Gas Deposition) method or a MBE (Molecular Beam Epitaxial) method, it must obtain a requirement The degree of crystallinity, that is, impurities such as oxygen are not introduced into and obtain a required two-dimensional growth. Therefore, according to the previous announcement of No. 6-57149, a conventional Germanium gallium indium phosphorous semiconductor laser device as shown in FIG. 9 is disclosed, in which an aluminum gallium indium phosphorus layer is grown on a gallium pop substrate 81 On one of the planes, the main plane of the substrate is oriented toward the [011] direction from the (100) plane. In this method, first an n-gallium-indium-phosphonium or n-gallium-indium-phosphonium buffer layer§2, an n-gallium-steel-phosphorus plating layer μ, a gallium-indium-phosphorus active layer S4, an aluminum-gallium-indium-phosphorus buffer layer 85, And a ρ-gallium arsenic cap layer 86 is grown on the η-gallium arsenic substrate 81 in this order using a MOCVD method. The main plane of the substrate_ is inclined from the (丨 〇ρ) plane-4-paper size Applicable to China National Standard (CNS) A4 (210 X 297 mm) C Please read the notes on the back before filling out this page} 装 i --- · II — Order _! '· ^^; ·-. 、 One tt: J * 465 12 7 A7 -------B7_____ 5. Description of the invention (2) [oil] orientation. Subsequently, a silicon dioxide (S102) film 87 is formed on the gallium arsenic cap layer 86, and the central portion of the silicon dioxide is etched into a stripe shape. -Electrically, 811 is formed on the silicon dioxide film S7, and an electrode 810 is formed on the opposite side of the < gallium arsenic substrate 81. In this conventional method for manufacturing a semiconductor laser device, a gallium indium phosphorus or indium gallium indium phosphate buffer layer is grown on a main plane of a gallium arsenic substrate, and the main plane is inclined from the (100) plane [Oli] Orientation, an AlGaInP phosphor type light-emitting segment was subsequently grown by a MOCVD method. However, for the following reasons, the effect of aligning the main plane of the gallium substrate to the [0H] orientation from the (100) plane in this method is not sufficient. First, the gallium indium phosphorus or chain gallium indium phosphorus buffer layer is not directly grown on the gallium arsenic substrate, and second, the buffer layer uses only a single composition. SUMMARY OF THE INVENTION According to one aspect of the present invention, a semiconductor light emitting device is provided. The semiconductor light emitting device includes at least: a gallium substrate, the main plane of which is oriented from a (1 {) 0) plane to an [oil] orientation; an AlxGaHAsfOgxSl) The first buffer layer is provided on the main plane of the gallium substrate; an AlyGa2lni_yjP second buffer layer is provided on the first buffer layer; -AlsGatIni stP (0s SS1 and Ostgl) first plating layer, Provided on the second buffer layer;-an active layer provided on the first plating layer; and a second bond layer provided on the active layer 'wherein the aluminum content S of one of the first plating layers is higher than that of the second buffer layer One Ming content y. In one embodiment of the present invention, the main plane of the gallium arsenic substrate is equal to or greater than about two. Angle? From the (100) plane, the [011] orientation is inclined. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm> 4 65 1 2 7 A? __________B7___________ V. Description of the invention (3) In the embodiment of the present invention, the freshness of the second buffer layer The amount y is equal to or greater than approximately 0.3 and less than or equal to approximately 0.8. In one embodiment of the present invention, the growth temperature of the second buffer layer is different from that of the first retardation layer. In an embodiment, the growth temperature of the second buffer layer is equal to the first iron layer. In one embodiment of the present invention, the growth temperature of the first buffer layer is equal to the second buffer layer. For example, the second buffer layer is grown when the growth temperature is changed in a first-order manner or in a continuous manner. In one embodiment of the present invention, the first plating layer is changed in a first-order manner or in a continuous manner when a growth temperature is changed. In one embodiment of the present invention, the semiconductor light emitting device further includes a current diffusion layer on the second plating layer. In one embodiment of the present invention, the semiconductor light emitting device further includes a current blocking layer on the second Between the plating layer and the current diffusion layer. In one embodiment of the present invention, the current blocking layer is provided in one of the semiconductor light emitting devices. The central portion. In one embodiment of the present invention, the current blocking layer is provided in the semiconductor One of the light-emitting devices_peripheral part = In one embodiment of the present invention, the active layer is a quantum well active layer obtained by depositing most quantum well layers and most barrier layers in a staggered pattern. In one embodiment of the present invention The semiconductor light-emitting device further includes a current blocking layer on the second plating layer, and a capping layer on the current blocking layer ------------ installed. (蹐 Read the first Note 'Month Filling this page') • 6-A7 B7 465 12 V. Description of the invention (, above. In the present invention-afterglow reflective layer, the heart-body light-emitting device manufacturing step includes an ether ,, ', The objective is to provide a substrate closer to the gallium god substrate with respect to the first shovel layer. The method is to stop-stop a bunch of other-Neigu not only, it provides a haircut through a gaseous deposition cut on the main plane of the material substrate Method ': the substrate <the main plane is from the (_ (〇〇〇) plane inclination one [_ This method includes the following steps: (a) growth—A1xGai.xAs (osxsi) a first buffer layer on a gallium arsenic substrate < 10 Wang Qian; (b) growing an AlyGaJr ^ ^ P (Ogy: 〇Szsi) a second buffer layer on the first buffer layer; and (〇 sequential growth s (〇SsS 丨 and "with a 0th-plating layer on the second buffer layer, an active layer is grown on A first plating layer and a second plating layer are grown on the active layer, wherein the aluminum content s of the first plating layer is higher than that of one of the second buffer layer without content y. In one embodiment of the present invention, the step ( a) is performed at a growth temperature between about 600 and 70.000; step (b) is performed and from about 600 to 700. 〇 The heart growth temperature is raised to a temperature between about 700 and 85 (rc); and step (C) is performed at a growth temperature between about 700 and 850 °. In one embodiment of the present invention Gaseous deposition method-organic metal chemical gas deposition (MOCVD) method. In one embodiment of the present invention, the 'gaseous deposition method is a molecular beam epitaxy (MBE) method. In one embodiment of the present invention, gallium arsenic The main plane of the substrate is at an angle equal to or greater than about 2. However, the main plane of the substrate is oriented toward [011] from the (100) plane. In one embodiment of the present invention, the aluminum content y of the second buffer layer is Equal to or the size of this paper applies the Chinese National Standard (CNS) A4 specification (21〇X 297 public love) (Please read the precautions on the back and fill in this page first) r-pack--II order ·! --- · Ι · ^ Τ. 4 651a 7 A7---S7 _ ------------ 5. Description of the invention (5) is greater than about 0.3 and less than or equal to about 0.8. One of the inventions In the embodiment, the growth temperature of one of the steps (b) is different from that of the step (c). In one embodiment of the present invention, the one of the growth temperatures of the step (b) is equal to The first coating layer in step (c). In one embodiment of the present invention, one of the growth temperatures in step (a) is equal to the one in step (b). In one embodiment of the present invention, step (b) is It is performed when a growth temperature is changed in a one-stage manner or in a continuous manner. In an embodiment of the present invention, the first plating layer in step (C) is grown when a growth temperature is changed in a one-stage manner or in a continuous manner. In one embodiment of the present invention, a current diffusion layer is provided on the second plating layer. In one embodiment of the present invention, a current blocking layer is provided between the second plating layer and the current diffusion layer. In one embodiment of the present invention, a current blocking layer is provided in a central portion of a semiconductor light emitting device. In an embodiment of the present invention, a current blocking layer is provided in a peripheral portion of a semiconductor light emitting device. In the present invention In one embodiment, the active layer is a quantum well active layer obtained by depositing most quantum well layers and most barrier layers in a staggered pattern. In one embodiment of the present invention, a current blocking layer is provided in the second On the coating And a capping layer is provided on the current blocking layer. In one embodiment of the present invention, a light reflecting layer is related to the first coating layer ’s national standard (c " NS) A4 specification ( 21G X 297) ^ 465 12 7 a? _ B7 V. Description of the invention (6) to provide a substrate closer to the marrying god. In one embodiment of the present invention, a growth temperature is at step (b). And then proceed to step (c). The function of the present invention will be explained in that the main plane of the posterior β gallium substrate is inclined from the (100) plane to the [〇11] direction, so that oxygen is less likely to enter the desired growth. An aluminum gallium indium phosphorus type semiconductor layer is formed thereon, thereby obtaining a required crystallinity. In order to fill this effect, it is preferred that the main plane is equal to or greater than 2. Winter angle-degrees. An AlxGakAs (0 s X s 1) first buffer layer is made on this inclined main plane. Therefore, the diffusion of impurities from the substrate and the diffusion of light can be suppressed, and the flatness of the substrate surface is improved. '吒 Unevenness is reduced. Of course, the orientation of the inclined plane does not change. Different from the conventional gallium-indium-phosphorus or aluminum-gallium-indium-phosphorus buffer layer, the gallium-arsenic or aluminum-gallium-allium-theta buffer layer of the present invention is the same as that of the substrate. The combination J exceeds, and therefore, the unevenness is uneven. It will be guided to the intervening houses, and it can grow a buffer layer with a small number of defects < and a required crystallinity and the orientation of the inclined plane are not changed. Furthermore, the first coating of aluminum gallium indium phosphorus It is provided on the first buffer layer of aluminum gallium arsenide (or gallium arsenic) through the second buffer layer of aluminum gallium indium phosphorus (or gallium indium phosphorus). As a result, the crystallinity of the light emitting segment, especially the active layer can be greatly improved. In order to improve the efficiency of letting go, in addition, an aluminum gallium indium phosphorus (or gallium indium brick) buffer layer structure including one or more layers may be provided on the first aluminum gallium arsenic (or gallium arsenic) buffer layer. According to the present invention, the aluminum content v of the second buffer layer is higher than the aluminum content S of the first plating layer. As a result, it is possible to obtain a semiconductor development signature, in which the crystallinity of the light emitting layer, especially the f-moving layer, is too high. To improve the radiation efficiency. For example, 畲-a ship layer with a high Ming content grows directly in _ 婚 坤 (or Ming Jia (please read the precautions on the back before writing this page): * 装 ----! | 订 "!- ---. ΛΙ--. -9- "4 65 1 2 7 A7 --- _ B7 V. Description of the invention (7) When the buffer layer is on, a required crystallinity cannot be obtained. However, in the present invention When the second buffer layer with a low aluminum content is longer than the gallium arsenic (or aluminum gallium arsenic) buffer layer, then a first coating layer with a high aluminum content is grown on the second buffer layer, and an improvement can be achieved. Crystallinity. In addition, the composition of the second buffer layer and / or the first plating layer may be gradually changed, and the composition may be changed in a class or continuous manner. The aluminum content y of the second buffer layer is equal to or greater than about 夭. 3, and is less than or equal to about '0.8. In this example, it can obtain a rich conductor light-emitting device, in which the light-emitting segment, especially the active layer, has a significantly improved crystallinity, thereby improving the radiation efficiency. The second buffer layer The growth temperature may be different from that of the first coating, for example, a coating having a high chain content (ie, the first coating) may Grow at a higher growth temperature, and a buffer layer with a low content (ie, a second buffer layer) can grow at a lower growth temperature because the ideal growth temperature of an aluminum gallium indium phosphorus layer with a high aluminum content is higher. The growth temperature of the buffer layer can be gradually changed. For example, the second buffer layer can be raised from the ideal growth temperature of the gallium arsenic (or aluminum gallium arsenide) during the growth. The growth temperature is increased to aluminum gallium indium phosphorus (or gallium indium). Phosphorus) The ideal growth temperature of the second buffer layer. In this example, the crystallinity can be further improved. Similarly, the growth temperature of the first plating layer can be gradually changed. 'Two current spreading and scattering i can be provided in the second mirror layer. Above, in this example, the injected current can diffuse through the current diffusion layer, so as to effectively use the entire active layer to emit light, thereby greatly improving the radiation efficiency. A current blocking layer can be provided between the second plating layer and the current diffusion layer. , At -10- (Please read the notes on the back before filling in this page) Factory-installed! ----- tr— I— 丨 · This paper size applies to China National Standard (CNS) A4 (210 X 297) Male) 4 651 2 7 A7 -B7 Warp Printed by the Intellectual Property Bureau of the Ministry of Intellectual Property, Printed by Jiang V. Invention Description (8). In this example, the current of '/ Wang Ru's can be diffused through the current diffusion layer in order to effectively use the entire active layer to emit light, thereby further improving the radiation efficiency. The current blocking layer can be provided in a central part of a semiconductor light emitting device. In this example, it can diffuse the injected current to the peripheral part of the device and effectively draw the generated current away from the device, thereby greatly improving the radiation efficiency. In addition, the current blocking layer can be provided on a peripheral portion of the semiconductor light emitting device. In this example, it can locate the current in the central portion of the device, thereby effectively drawing the generated current away from the device with two large current densities. To greatly improve radiation efficiency. A light-reflecting layer is related to the first plating layer to provide a substrate closer to gallium arsenic. In this example, a portion of the light generated by the substrate can be reflected by light 2. The layer is reflected, so it can be extracted from the device. This greatly improves the efficiency of the use of the generated light. According to the present invention, a semiconductor laser device can be provided by providing a current blocking layer and a capping layer on the second plating layer. Therefore, the advantages of the present invention disclosed in the text are to provide-a semiconductor light-emitting device including a gallium arsenic substrate, the main plane of the substrate is inclined from the (100) plane. [011] orientation and the inscription of the required crystallinity The indium scale semiconductor layer is grown on this main plane, thereby greatly improving the radiation efficiency. The above and other advantages of the present invention will be apparent to those skilled in the art after reviewing and understanding the following detailed description and reference to related drawings. Brief description of the drawings Figures 1A to 1D are cross-sectional views illustrating a method for making a semiconductor light-emitting device according to an embodiment of the present invention; inch -11-(Please read the precautions on the back # / ^. Write this page first)
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L 本紙張尺度適用令國國家標準（CNS)A4規格（210 X 297公笼） 4 6512 7 A7 B7 五、發明說明（L The paper size is applicable to the national standard (CNS) A4 specification (210 X 297 male cage) 4 6512 7 A7 B7 V. Description of the invention (
圖M、戰明一族聊半導體基材之結晶表面之模型· 圖3係—簡示截面圖，説明本發明實施例2之 ’ 光裝置結構； 千^姐發 圖4係—簡示截面圖’説明本發明触 發光裝置結構； 半導體 圖5係一簡示截面圖，説明本 光裝置結構； ^施例3(—半導體發 圖6係-簡示截面圖’説明本發明實施例*之一 光裝置結構； ^ 圖7係—簡示截面圖，説明本發明實施例5之-半導體發 光裝置結構；_ ^ 圖8係-簡示截面圖.，説明本發明實施例此一半導 光裝置結構； 及 ί.----------Mi {請先閱讀背面之注意事填寫本頁) -tr· ilFigure M. Zhanming family talks about the model of the crystalline surface of the semiconductor substrate. Figure 3 is a schematic cross-sectional view illustrating the structure of the optical device in Embodiment 2 of the present invention. Figure 4 is a schematic cross-sectional view. Illustrate the structure of the trigger light device of the present invention; Semiconductor Figure 5 is a schematic cross-sectional view illustrating the structure of the optical device; ^ Example 3 (—Semiconductor Figure 6 Series-Schematic cross-section view 'illustrates one embodiment of the present invention * Device structure; ^ Figure 7 is a schematic cross-sectional view illustrating the structure of a semiconductor light emitting device according to Embodiment 5 of the present invention; ^ Figure 8 is a schematic cross-sectional view illustrating the structure of a half of the light guide device according to the embodiment of the present invention; And ί .---------- Mi (Please read the notes on the back first and fill out this page) -tr · il
經濟部智慧时轰奇| L t r. —L 圖H)説明基材主平面傾斜角上之域銦磷層表面令之四 凸不平深度（角度）之依存性。 較佳實施例説明 本發明之多項實施例現在將參考相關圖式説明之’在本 發明實施例.之以下説明中…MC)C：VD方法係用於生長半導 體層’惟，其生長方法並不限於此，其另可爲其他生長方 法，例如一MBE方法、—氣體沉積法、或類此者。本發明 l效果可在各半導體層組合物由以下説明中適度調整時充 分取得，再者，裝置之結構亦可由以下説明中適度調整。 • 12- 本紙張尺度巾關家標準（CNS)A4規格f2i〇 X 297公愛） riN4 65l27 A7 ______B7 _ 五、發明說明（1° ) 本發明可應用於任意半導體發光裝置，例如一半導體雷射 装置、一發光二極體、或類此者。 (實施例1) 如本發明半導體發光裝置之一實施例者，一鋁鎵銦磷型 發光二运體將説明之。 圖1D係一簡示截面圖’説明本實施例之發光二極體結構 ’發光二極體包括一n_鎵砷基材1，其主平面係自（100)平面 .傾向[oil]方位。發光二極體進一步包括一n_AlxGai xAs (〇笤 x^l)第一緩衝層2、一n-AlyGaJiii.y.zP (OsySl 且 OszSl) 第二緩衝層 3、.一 n-AlsGatInLtP (Ogs 笤 1且 OStSl)第一鍍 層 4、一 AUGabliih-bP (〇SaSl 且 Osb 萏 1)主動層 5' - p-AlcGaJnLdP (Og.csi 且 〇gciSl)第二鍍層 6、及一 InfAlgGa^P (0<f< 1且0<g< 〇電流擴散層7，其皆沉積 於η-鎵砷基材1上。一電極丨丨係提供於層狀結構之頂表面中 央部分’及另一電極1 〇提供於η_鎵坤基材〖之相反側上。 發光二極體例如可製造如下。 首先，主平面自（100)平面傾向[〇]11]方位大約15。之η_鎵坤 基材1係提供如圖1Α所示，隨後如圖1Β ’第一緩衝層2及第 二缓衝層3利用一 M0CVD*法而生長於;心鎵砷基材，第 —缓衝層2真有大約〇.5微米厚度及一 n_AlxGai xAs組合物（〇 运1 ;在此例子中x=〇且矽濃度例如大約5xl017厘米·3)， 第二緩衝層3則具有大約0 〇5微米厚度及一 η_Α1#^Ιηι_pP 組合物（0 g y S 1且〇 S z含1 ;在此例子中y=〇.6，ζ=0·5且石夕濃； 度例如大約5χ1〇17厘米·3)^首先，第一緩衝層2在大約6〇〇至 • 13- 本紙張尺度適用中國國豕標準（CNS)A4規格（210 X 297公釐） illmmlt ^ ill — — — -- --J C請先閱讀背面之注意事叹再填寫本頁) A7 4651 2 7 ____B7__ 五、發明說明（11 ) 700X：之生長溫度中生長，隨後生長第二緩衝層3且生長溫 度自大約600至700X昇高至大約700至850°C。 隨後如圖1C所示’第一.鍍層4、主動層5、第二鍍層6、及 電流擴散層7係以大約700至850°C生長溫度依此順序沉積。 第一鍍層4具有大約1.0微米厚度及一n-AisGatIni.s_tI>組合物 (OSsSl且OSt^l ;在此例子中s=〇.5，t=0.0且妙滚度例如 大約5xl017厘米·3)，主動層5具有大約〇·5微米厚度及一 AlaGaf)lD 1-a-ijP组合物（0运a έ 1且〇运b含1 ;在此例子中例如 a=0.4，b=0.5)，第二鍍層6具有大约1.〇微米厚度及一 p_ AUGadliiK-dP 组合物（〇 s c S 1且 〇 s d S 1 ;在此例子中 c = 〇.5 ，d=0.5且鋅濃度例如大約5x 1017厘米-3)，電流擴散層7具有 大約5微米厚度及一p-rrifAlgGaagP组合物（〇 < f < 1且〇 < g < 1 ;在此例子中卜0.01，g=〇.〇l且鋅濃度例如大約5xl〇ls厘 米-3)。 随後如圖1D所示’電極1〇、u製成而完成發光二極體。 如上所述，依本發明所示，n_鎵坤基材1之主平面係自 (100)平面倾向[〇Π]方位大約15。，緩衝層採用雙層結構， 即包括η-銘録砷（或鎵砷）第一緩衝層2及鋁鎵銦磷（或鎵銦 磷）第二緩衝層3 ’第一鍍層4之鋁含量s (在本實施例中 s=1.0)大於第二緩衝層3之銘含量y (在本實施例中6)。 結果’發光段特別是主動層5之結晶度係大幅改善，藉以大 幅改善放射效率，這些效應將進一步探討如下。 首先’將鎵砷基材1之主平面自（1〇〇)平面傾向[〇u]方位 之效應將説明如下。 -14- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公龙） -裝--- (請先閲讀背面之注意事項再^寫本頁) .1:· β 465127 a7 ---- B7_______ 五、發明說明（12 ) 圖2A説明沿著（100)平面之族ΙΠ-ν晶體之表面模型，及圖 2Β説明自（1〇〇)平面傾向[〇u]*位之族ΠΙ-ν晶體之表面模型 ，此處之族III元素可爲鎵.、鋁、銦或類此者，及族V元素可 爲砷、磷或類此者。如圖2Α所示，沿著（1〇〇)平面之族111_乂 晶體之主平面係覆以族V原予’各原子具有雙键。反之，如 圖2Β所示，主平面傾向[011]方位之族ΠI_V晶體之表面係包 括（U1)平面’其沿著族晶體之表面而以一規律間隔發 生，（111)平面係一結晶平面，其覆以族ΙΠ原子，各原子具 有雙鍵。在圖2Β所示之模型中，族ΠΙ_ν晶體之表面係包括 沿者·結漏表面每數十微米而設一（π 1)階級（即族πι 晶體之 主平面中之一階級部，其對應於（lu)平面）’且族ϊπ_ν晶體 I主平面即據此而自（1〇〇)平面傾斜。由於（1Η)平面係覆以 族III.原子’各原子具有單键，因此，供給至此之族V原子 (在此例子中爲磷原子）即結合於族ΠΙ原子。惟，鍵容易斷 .裂_，因爲該鍵係一單鍵，因此族V原子將沿著此平面移動。 文内會降低AlaGabIni_a-bp (0驾as υ主動層5内放 射效率之一可能因素爲導入〇(氧）原子至主動層5内。當〇 (乳）原子導入一銘録銦鱗晶體内時，〇(氧）原子即構成—非 輕射層，’藉此使非輻射之再组合發生於載體注入晶體内時 。由於0(氧）係一族VI元素，因此0(氧）原子可以輕易地佔 用族V處之晶格位置，惟，〇(氧）原子無法沿著自（1〇〇)平面 傾向[011]方位之主平面而輕易地佔用族V處之晶格位置， 因爲族V原子係沿著主平面移動，如上所述，因此大量族v 原子即沿著結晶表面而存在。據此，可減少導入n_ -15- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐〉 -----------裝.丨丨丨 (請先閲讀背面之注意事項寫本頁) 钉-------- A7 465彳 2 7 -------B7_;_ 一 五、發明說明（13 )The wisdom of the Ministry of Economic Affairs | L t r. —L Figure H) illustrates the dependence of the surface of the indium-phosphorus layer on the inclination angle of the main plane of the substrate on the depth (angle) of the four irregularities. DESCRIPTION OF THE PREFERRED EMBODIMENTS A number of embodiments of the present invention will now be described with reference to the related drawings, "in the following description of the embodiments of the present invention ... MC) C: VD method is used to grow a semiconductor layer. Not limited to this, it may be another growth method, such as a MBE method, a gas deposition method, or the like. The effects of the present invention can be fully obtained when each semiconductor layer composition is moderately adjusted in the following description. Furthermore, the structure of the device can also be appropriately adjusted in the following description. • 12- The paper size towel family standard (CNS) A4 specification f2i〇X 297 public love) riN4 65l27 A7 ______B7 _ 5. Description of the invention (1 °) The invention can be applied to any semiconductor light emitting device, such as a semiconductor laser Device, a light emitting diode, or the like. (Embodiment 1) As one embodiment of the semiconductor light-emitting device of the present invention, an aluminum-gallium-indium-phosphorus-type light-emitting diode will be described. FIG. 1D is a schematic cross-sectional view illustrating the light-emitting diode structure of this embodiment. The light-emitting diode includes an n-gallium arsenic substrate 1 whose main plane is from the (100) plane. The light-emitting diode further includes an n_AlxGai xAs (〇 笤 x ^ l) first buffer layer 2, an n-AlyGaJiii.y.zP (OsySl and OszSl) second buffer layer 3,. An n-AlsGatInLtP (Ogs 笤 1 And OStSl) first plating layer 4, an AUGabliih-bP (〇SaSl and Osb 萏 1) active layer 5 '-p-AlcGaJnLdP (Og.csi and 〇gciSl) second plating layer 6, and an InfAlgGa ^ P (0 < f & lt 1 and 0 < g < 〇 current diffusion layer 7, which are all deposited on the η-gallium arsenic substrate 1. An electrode 丨 is provided in the central portion of the top surface of the layered structure and another electrode 〇 is provided on The η_Ga Kun substrate is on the opposite side. The light-emitting diode can be manufactured, for example, as follows. First, the principal plane is oriented toward [0] 11] from the (100) plane of about 15. The η_Ga Kun substrate 1 is provided As shown in FIG. 1A, as shown in FIG. 1B, the first buffer layer 2 and the second buffer layer 3 are grown using a MOCVD * method; the core gallium arsenic substrate, the first buffer layer 2 is really about 0.5 microns. Thickness and an n_AlxGai xAs composition (〇trans 1; in this example, x = 〇 and the silicon concentration is, for example, about 5 × 1017 cm · 3), the second buffer layer 3 has a thickness of about 0.05 μm and 1 η_Α1 # ^ Ιηι_pP Composition (0 gy S 1 and 〇S z contains 1; in this example y = 0.6, ζ = 0.5 and Shi Xinong; degree, for example, about 5 x 1017 cm · 3) ^ First , The first buffer layer 2 is about 600 to • 13- This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) illmmlt ^ ill — — — — --JC Please read the back (Notes and sighs and fill in this page) A7 4651 2 7 ____B7__ V. Description of the invention (11) 700X: Growth at a growth temperature, and then the second buffer layer 3 is grown and the growth temperature is increased from about 600 to 700X to about 700 to 850 ° C. Subsequently, as shown in FIG. 1C, the 'first. Plating layer 4, the active layer 5, the second plating layer 6, and the current diffusion layer 7 are deposited in this order at a growth temperature of about 700 to 850 ° C. The first plating layer 4 has a thickness of about 1.0 micrometer and an n-AisGatIni.s_tI> composition (OSsSl and OSt ^ l; in this example, s = 0.5, t = 0.0 and a wonderful roll, for example, about 5 × 1017 cm · 3) , The active layer 5 has a thickness of about 0.5 micrometers and an AlaGaf) 1D-a-ijP composition (0 to a 1 and 0 to b contains 1; in this example, a = 0.4, b = 0.5), The second plating layer 6 has a thickness of about 1.0 micron and a p_AUGadliiK-dP composition (0sc S 1 and 0sd S 1; in this example, c = 0.5, d = 0.5, and a zinc concentration, for example, about 5x 1017 Cm-3), the current diffusion layer 7 has a thickness of about 5 microns and a p-rrifAlgGaagP composition (0 < f < 1 and 〇 < g <1; in this example, 0.01, g = 0.0. l and the zinc concentration is, for example, about 5 × 10 l cm−3). Subsequently, as shown in FIG. 1D, the 'electrodes 10 and u are made to complete a light emitting diode. As described above, according to the present invention, the principal plane of the n-Ga Kun substrate 1 is about 15 from the (100) plane. The buffer layer adopts a double-layer structure, that is, it includes an η-inscribed arsenic (or gallium arsenic) first buffer layer 2 and an aluminum gallium indium phosphorus (or gallium indium phosphorus) second buffer layer 3 ′ aluminum content of the first plating layer 4 (S = 1.0 in the present embodiment) is larger than the content y of the second buffer layer 3 (6 in the present embodiment). As a result, the crystallinity of the light-emitting segment, especially the active layer 5, is greatly improved, and the radiation efficiency is greatly improved. These effects will be further discussed below. First, the effect of tilting the main plane of the gallium arsenic substrate 1 from the (100) plane to the [〇u] orientation will be explained as follows. -14- This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 male dragon) -Packing --- (Please read the precautions on the back before writing this page) .1: · β 465127 a7- -B7_______ V. Description of the invention (12) Figure 2A illustrates the surface model of the family ΙΠ-ν crystals along the (100) plane, and Figure 2B illustrates the tendency of the family ΠΙ from the (100) plane. a surface model of a ν crystal, where the Group III element may be gallium, aluminum, indium, or the like, and the group V element may be arsenic, phosphorus, or the like. As shown in FIG. 2A, the principal plane of the family 111_ 乂 crystal along the (100) plane is covered with a group V atom and each atom has a double bond. In contrast, as shown in FIG. 2B, the surface of the family ΠI_V crystal with a principal plane orientation of [011] includes the (U1) plane, which occurs at regular intervals along the surface of the family crystal, and the (111) plane is a crystal plane , Which is covered by a group II atom, each atom has a double bond. In the model shown in FIG. 2B, the surface of the family III_v crystal includes a (π 1) class per dozens of micrometers along the junction-drain surface (that is, a class part in the main plane of the family μm crystal, which corresponds to ((Lu) plane) 'and the main plane of the family ϊπ_ν crystal I is tilted from the (100) plane accordingly. Since the (1Η) plane is covered with a group III. Atom 'and each atom has a single bond, the group V atom (phosphorus atom in this example) supplied thereto is bound to the group III atom. However, the bond is easily broken. Because the bond is a single bond, the group V atom will move along this plane. In this article, AlaGabIni_a-bp (0 driving as υ one of the possible radiation factors in the active layer 5 is the introduction of 0 (oxygen) atoms into the active layer 5. When 0 (milk) atoms are introduced into an indium scale crystal 〇 (oxygen) atoms constitute a non-light emitting layer, so that the non-radiation recombination occurs when the carrier is injected into the crystal. Since 0 (oxygen) is a group VI element, 0 (oxygen) atoms can be easily Occupy the lattice position at family V. However, the 0 (oxygen) atom cannot easily occupy the lattice position at family V along the main plane oriented from the (100) plane to the [011] orientation, because the family V atom The system moves along the main plane, as described above, so a large number of family v atoms exist along the crystal surface. According to this, the introduction of n_ -15 can be reduced. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297). Mm> ----------- install. 丨 丨 丨 (Please read the precautions on the back first to write this page) Nail -------- A7 465 彳 2 7 ----- --B7 _; _ One, five, description of the invention (13)
(〇 含 y s 1 且 〇 g z g 1)第二緩衝層 3、n-AlsGatIni.s-tp (0gsS !且 第—鍍層 4、AlaGaiJni a.bP (OSagl且OsbSl)主動層 5及p-AlGaJiirc-dP (〇gcg 1且〇岌 dsiy第二鍍層6，藉以大幅改善放射效率。再者，如上所述 ’（U ο階級係以規則間隔製成，在諸階級上，一疊層狀生 長（其生成所需之結晶度）即易於發生，結果，晶體表面中之 凹凸不平深度係大幅減少，由此以改善晶體之平坦度與結 晶度。 圖10揭示製成於各n_鎵砷基材上且其主平面自（1〇〇)平面 傾向[011]方位大約 〇。至 20。之一 AljGajJn^.kP (j=0.5且 k=0.0) 層表面中之凹凸不平深度測量結果，由圖1〇中可知，當主 平面未自（100)平面傾斜時（即當傾斜角爲0。時），.即發生深 度超過1000埃之凹凸不平。反之，當主平面傾斜角等於或 大於2°時，凹凸不平之深度即大爲減低。傾斜角較佳爲在 大約5°至20°範圍内（傾斜角超過20。會造成生產成本不必要 地增加）’特別是當傾斜角等於15。以上時，凹凸不平之深度 可減低至大約100埃以下，藉以取得一要求之結晶度。 第二，針對緩衝層而採用一包括n-鋁鎵砷（或鎵砷）第一缓 衝層2與鋁鎵銦磷（或鎵銦磷）第二缓衝層3之雙層結構之效果 將説明於後。 由於提供η-鋁鎵砷第一缓衝層2於心鎵砷基材丨上，自基材 擴散入發光段之雜質即受到抑制，且基材表面之平坦度改 善’即凹凸不平減少。當然，傾斜平面之方位不變。當一 n-AlxGat-xAs (0当X S 1)弟一缓衝層提供於鎵坤基材1上時 -16' 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ，請先閲讀背面之注意事項再饔寫本頁) -I . ^1 _ϋ ϋ n VI. I n 一 δ、 n n I I n 1 n I » 經濟部智慧財產局員工消費合作社印製 ^ 4 6512 7 A7 ---- R7 五、發明說明（ 14(0 contains ys 1 and 0 gzg 1) second buffer layer 3, n-AlsGatIni.s-tp (0gsS! And first plating layer 4, AlaGaiJni a.bP (OSagl and OsbSl) active layer 5 and p-AlGaJiirc-dP (〇gcg 1 and 0 岌 dsiy second plating layer 6 to greatly improve the radiation efficiency. Moreover, as described above, the (U ο class is made at regular intervals, on the various classes, a stack-like growth (which generates The required degree of crystallinity) is easy to occur. As a result, the depth of unevenness in the crystal surface is greatly reduced, thereby improving the flatness and crystallinity of the crystal. Its principal plane is inclined from [100] plane to a [011] azimuth of about 0 ° to 20. It is one of AljGajJn ^ .kP (j = 0.5 and k = 0.0) layer surface roughness measurement results, from Figure 1〇 It can be seen that when the main plane is not inclined from the (100) plane (that is, when the inclination angle is 0 °), unevenness with a depth exceeding 1000 angstroms occurs. On the contrary, when the main plane inclination angle is equal to or greater than 2 °, The depth of the unevenness is greatly reduced. The tilt angle is preferably in the range of about 5 ° to 20 ° (the tilt angle exceeds 20) It will cause unnecessary increase in production cost) 'Especially when the inclination angle is equal to or more than 15, the depth of the unevenness can be reduced to about 100 angstroms or less in order to obtain a required crystallinity. Second, it is adopted for the buffer layer. The effect of a two-layer structure including an n-aluminum gallium arsenide (or gallium arsenic) first buffer layer 2 and an aluminum gallium indium phosphorus (or gallium indium phosphorus) second buffer layer 3 will be described later. The aluminum gallium arsenic first buffer layer 2 is on the core gallium arsenic substrate. The impurities diffused from the substrate into the light emitting section are suppressed, and the flatness of the surface of the substrate is improved, that is, the unevenness is reduced. Of course, the inclined plane Orientation does not change. When an n-AlxGat-xAs (0 when XS 1) and a buffer layer are provided on the gallium substrate 1-16 'This paper size applies to China National Standard (CNS) A4 (210 X 297) (Mm), please read the notes on the back before writing this page) -I. ^ 1 _ϋ ϋ n VI. I n a δ, nn II n 1 n I »Printed by the Consumers’ Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs ^ 4 6512 7 A7 ---- R7 V. Description of the invention (14
Fr I- - J ’這些效果亦同樣可取得，丘夕 S —鎵銦_或鋁鎵銦磷 缓衝層提供如先前技藝中者眛，德施a ' a 石呀，緩衝層之组合物即不同於 基材者，藉以導送凹凸不平至其間之結合處或導送瑕斑至 緩衝層内。 第三，設定第一鍍層4之銘含量3高於第二緩衝廣3之銘含 量”同時改變不同層之生長溫度之效果將説明於後。 當具有高鋁含量之—鋁鎵銦磷第一鍍層係直接生長於鎵 砰第-緩衝層上時，生長介面並不陡崎，且_要求之結晶 度會因爲諸廣之間顯著之組合物差異而無法取得。由此以 觀，依據本實施例所示，具有鋁含量低於η·Α1θΜηΐΜΡ (〇 “Si且ΟέΒΙ)第一鍍層4者之AlyGaJni y』（〇容y g 1且〇 运ZS1)第二緩衝層3係唑長於鎵砷第—緩衝層2上，因此， 其可取得一要，求之生長介面，並且取得具有一要求結晶度 之第一鍍層4。當鋁鎵銦磷緩衝層3之鋁含量高於銦鎵磷者 時，铝鎵銦磷緩衝層3之組合物類型係相同於上鍍層者，其 即可取得一要求之生長介面。當鋁鎵銦磷緩衝層3之鋁含量 低於鍍層4者時，結晶度可改善，特別是眾佳爲第二緩衝層 之銘含量y等於或大於大約0.3 ’且小於或等於大約〇 8。 嫁砷第一緩衝層2之最佳生長溫度大約650至720X，銘緣 銦鱗層之生‘長溫度較佳爲等於或大於大约7〇〇Τ，特別是一 具有高鋁含量之層例如鋁鎵銦磷層係較佳爲以高溫生長。由 此以觀’依據本實施例所示，結晶度可藉由生長AlyGazIii4 J (OgySl且OSzSl)第二緩衝層3 (於鎵坤第一緩衝層2與 ALGatli^-wP (〇 g s έ 1且0 S t S 1)第一艘層4之間）而大幅改善 -17 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 κ 297公釐） (請先閱讀背面之注意事項^-#寫本頁)Fr I--J 'These effects can also be obtained. Qiu Xi S —Gallium Indium— or AlGaInP buffer layer provides as in the previous art, De Shi a' a stone, the composition of the buffer layer is Different from the base material, it can guide the unevenness to the junction between them or the flaws into the buffer layer. Third, the effect of setting the content 3 of the first plating layer 4 higher than the content of the second buffer layer 3 "while changing the growth temperature of different layers will be explained later. When the aluminum content is high-aluminum gallium indium phosphorus first When the plating layer is directly grown on the gallium palladium-buffer layer, the growth interface is not steep, and the required crystallinity cannot be obtained due to the significant composition difference between the various regions. Therefore, according to this implementation, As shown in the example, AlyGaJni y (〇 容 yg 1 and 〇〇ZS1) having a aluminum content lower than η · A1θΜηΐΜΡ (〇 "Si and 〇ΒΒΙ) the first plating layer 3 (〇 容 yg 1 and 〇 运 ZS1) the second buffer layer 3 azole is longer than gallium arsenic — Therefore, the buffer layer 2 can obtain a desired growth interface and a first plating layer 4 having a required crystallinity. When the aluminum gallium indium phosphorus buffer layer 3 has a higher aluminum content than the indium gallium phosphorus, the composition type of the aluminum gallium indium phosphorus buffer layer 3 is the same as that of the upper plating layer, which can obtain a required growth interface. When the aluminum content of the aluminum gallium indium phosphorus buffer layer 3 is lower than that of the plating layer 4, the crystallinity can be improved, and in particular, the excellent content of the second buffer layer y is equal to or greater than about 0.3 'and less than or equal to about 0.8. The optimal growth temperature of the first arsenic buffer layer 2 is about 650 to 720X, and the growth temperature of the indium scale layer is preferably equal to or greater than about 700T, especially a layer having a high aluminum content such as aluminum. The gallium indium phosphorus layer is preferably grown at a high temperature. Therefore, according to this embodiment, the crystallinity can be increased by growing AlyGazIii4 J (OgySl and OSzSl), a second buffer layer 3 (in the first buffer layer 2 and ALGatli ^ -wP (〇gs 1 and 0 S t S 1) Between the first ship and layer 4) and greatly improved -17-This paper size applies the Chinese National Standard (CNS) A4 specification (210 κ 297 mm) (Please read the precautions on the back first ^-# (Write this page)
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'465127 五、發明說明（15 ) ，同時自鎵坤第一緩衝層2之最佳生長溫度昇高生長溫度至 (具有南铭含量之）AlsGatIni.s.tP (OssSl且OStsi)第一鍍層 4之最佳生長溫度。當提供一 n-ALGaixAs (〇 gx骂〇第一缓 衝層時，這些效果同樣可取得。 在本實施例中’ AlyGazInt.y.zP⑺^^且^^”第二緩 衝層3係生長且同時昇高其生長溫度，惟，基於上述理由， 當第二緩衝層3以相同於η-鎵砷第一缓衝層2之最佳生長溫 度、AlsGaJiih.tP 第一鍍層4之最佳生長 溫度、或其間之另一溫度生長時，亦可取得相似效果。 (實施例2) 如本發明半導體發光裝置之另—實施例者，—鋁鎵銦磷 型半導體雷射裝置將説明之。 圖3係一簡示截面圖，説明本實施例之半導體雷射裝置結 構’半導體雷射裝置包括一η-鎵砷基材21，其主平面係以 一太約10。角自（100)平面傾向[〇 11 ]方位。半導體雷射裝置 進一步包括一第一緩衝層22、一第二缓衝層28、一第一艘 層23、一量子丼主動層24、一第二鍍層25、及一帽蓋層26 ’其皆沉積於η-鎵坤基材21上。第一缓衝層22具有大約0.5 微米厚度及一n-ALGauAs組合物（〇gxg 1 ;在此例子中χ=〇 2矽濃度例如大約5x1017厘米_3)，第二缓衝層28具有大約 0.5微米厚度及一n-AlyGazInt-y^ta合物（〇gys 1且〇gzg ! ;在此例子中y=0.3，ζ=0·0且矽濃度例如大約5χΐ〇17厘米-3) ，第一鍍層23具有大約1.0微米厚度及一 n-AlsGailnuAtiL合 物（0运sS 1且Ostg 1 ;在此例子中s=0.5，t=0.0且矽濃度例 -18- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再赛寫本頁) r-裳 —1 —4 IB1 n 一^ n n n n n I - A7 f ;H4 6512 7 _B7 ___ 五、發明說明（16 ) 如大約5x1017厘米·3)。量子井主動層24具有一交錯之多層結 構，包括五層AhGablnutP量子井（OgaSl且〇Sb运1 ;在此 例子中例如a=0，b=0.5)JL各層具有大約10毫微米厚度，及 六層AUGabln^.bP障壁(〇 s as 1且〇 sb S 1 ;在此例子中例如 a=0,3，b=0.5)。第二鍍層25具有大約1.〇微米厚度及一 p_ AlGadlni.aP组合物（〇舍c运1且〇gdSl :在此例子中c=0.5 ，d=0.5且鋅濃度例如大約5xl〇17厘米·3)，帽蓋層26具有大 約1微米厚度及一 ρ-鎵砰組合物（此處之鋅濃度大約〗xl〇is厘 米*3)。一由二氧化矽（Si〇2)或類此者製成之絕緣膜27係提供 於帽蓋層26上，且絕綠膜27之中央部分蝕刻成一長條狀， 藉以提供一電流路徑。一電極211係提供於絕緣膜27上，及 另一電極210提供於基材之相反側上。 如實施例1者，本實施例之半導體雷射裝置中，將n_鎵碎 基材21之主平面自（100)平面傾向[011]方位之效果十分顯著 ’其針對缓衝層而採用—雙層結構，包括n_AlxGaixAs (〇s xs 1)第一緩衝層 22 及 n_AlyGajn 卜 y—p (〇Syg 1且 J)第 二緩衝層28，且設定基材側鍍層（即第—鍍層23)之鋁含量高 於第二緩衝層28者。 圖4説明本發明實施例2之另一半導體雷射裝置結構，半 導體雷射裝置包括一.電流阻斷層29及帽蓋層26，在此例子 中’其可定位電流於主動層之中央部分，藉以增大電流密 度。 & (實施例3) 如本發明半導體發光裝置之又一實施例者，一鋁鎵銦嗜 -19 - 本紙張尺度適用中固國家標準（CNs)a4说格卿χ挪公愛） (請先閱讀背面之注意事項一ί填寫本頁) Γ1裂！1訂-丨丨丨丨1!.-線' 聲 Sr ·? έ 才 I，3 ί .'465127 V. Description of the invention (15), at the same time, the growth temperature is increased from the optimal growth temperature of the first buffer layer 2 of Gallium Kun to (with Nanming content) AlsGatIni.s.tP (OssSl and OStsi) first plating layer 4 The best growth temperature. When an n-ALGaixAs (0gx) is provided as the first buffer layer, these effects can also be obtained. In this embodiment, 'AlyGazInt.y.zP⑺ ^^ and ^^ "The second buffer layer 3 is grown and simultaneously Increase its growth temperature. However, based on the above reasons, when the second buffer layer 3 is the same as the optimal growth temperature of the η-GaAs first buffer layer 2, the optimal growth temperature of the AlsGaJiih.tP first plating layer 4, A similar effect can be obtained when growing at another temperature in between. (Embodiment 2) As another embodiment of the semiconductor light-emitting device of the present invention, an aluminum-gallium-indium-phosphorus semiconductor laser device will be described. Figure 3 Series A schematic cross-sectional view illustrating the structure of the semiconductor laser device of the present embodiment. The semiconductor laser device includes a η-gallium arsenic substrate 21, the main plane of which is too large. [11]. The semiconductor laser device further includes a first buffer layer 22, a second buffer layer 28, a first boat layer 23, a quantum erbium active layer 24, a second plating layer 25, and a capping layer. 26 'They are all deposited on the η-Ga Kun substrate 21. The first buffer layer 22 has about 0.5 micrometers Thickness and an n-ALGauAs composition (0 gxg 1; in this example, χ = 〇2 silicon concentration such as about 5x1017 cm_3), the second buffer layer 28 has a thickness of about 0.5 microns and an n-AlyGazInt-y ^ ta compound (〇gys 1 and 〇gzg !; in this example y = 0.3, ζ = 0 · 0 and silicon concentration, for example, about 5 × 1717 cm-3), the first plating layer 23 has a thickness of about 1.0 micrometer and a n -AlsGailnuAtiL compound (0 to sS 1 and Ostg 1; in this example, s = 0.5, t = 0.0, and silicon concentration Example -18- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before writing this page) r-Sang—1 —4 IB1 n a ^ nnnnn I-A7 f; H4 6512 7 _B7 ___ V. Description of the invention (16) Such as about 5x1017 cm · 3) The quantum well active layer 24 has a staggered multilayer structure including five layers of AhGablnutP quantum wells (OgaS1 and 0Sb; 1 in this example, for example, a = 0, b = 0.5), each layer of the JL has a thickness of about 10 nm, and Six-layer AUGabln ^ .bP barrier (0s as 1 and 0sb S 1; in this example, a = 0,3, b = 0.5). The second plating layer 25 has a thickness of about 1.0 micron and a p_AlGadl ni.aP composition (0 c, 1 and 0 gdSl: in this example, c = 0.5, d = 0.5, and zinc concentration, for example, about 5 × 1017 cm · 3), the cap layer 26 has a thickness of about 1 micrometer and a The p-gallium ping composition (the zinc concentration here is approximately x10is cm * 3). An insulating film 27 made of silicon dioxide (SiO2) or the like is provided on the capping layer 26, and a central portion of the green insulating film 27 is etched into a long shape to provide a current path. One electrode 211 is provided on the insulating film 27, and the other electrode 210 is provided on the opposite side of the substrate. As in Example 1, in the semiconductor laser device of this embodiment, the effect of tilting the main plane of the n_gallium chip substrate 21 from the (100) plane to the [011] orientation is very significant. 'It is adopted for the buffer layer— The double-layer structure includes n_AlxGaixAs (0s xs 1) first buffer layer 22 and n_AlyGajn buy-p (〇Syg 1 and J) second buffer layer 28, and the substrate-side plating layer (that is, the first-plating layer 23) is set. The aluminum content is higher than that of the second buffer layer 28. FIG. 4 illustrates another structure of a semiconductor laser device according to Embodiment 2 of the present invention. The semiconductor laser device includes a current blocking layer 29 and a capping layer 26. In this example, it can locate the current in the central portion of the active layer. To increase the current density. & (Embodiment 3) As another embodiment of the semiconductor light-emitting device of the present invention, an aluminum gallium indium enthalpy-19-this paper standard is applicable to the National Solid State Standards (CNs) a4 said Ge Qing χNuo Gongai) (Please First read the precautions on the back (I fill out this page) Γ1 crack! 1 order- 丨 丨 丨 丨 1! .- line 'sound Sr ·? 着 才 I, 3 ί.
46512 7 五、發明說明（17 ) 型半導體發光二極體將説明之。實施例3相同於實施例ι， 例外的是⑴基材之主平面傾斜角設定於大約5。，（⑴第二緩 衝層之生長溫度等於第一鍍層者，及（ill)提供一光反射層。 圖5.係-簡示截面圖，説明本實施例之發光二極體結構， 發光二極體包括一n•鎵砷基材31，其主平面係以—大約5。角 自（100)平面傾向[011]方位。發光二極體進—步包括 AlxGai.xAs (0SxS1)第—缓衝層 38、_n_AlyGazu (〇s y-1且Oszgl)第一缓衝層32、一 n-麵砰/鎵坤光反射層39、 —n'AlsGatIni.tP (0 S s S 1 且 〇 s t S 1)第一鍍層 33、一 AlaGabIn“a_bP (OsaSl且Osbsi)主動層 34、一p-AlcGaJiii.cd P (OScSl 且 Osdgl)第二鍍層 35 ' 及一lnt.AlgGau.gP (〇< f <1且0<g<l)電流擴散層36，其皆沉積於心鎵神基材3 1上 。.電極3 Π係提供於電流擴散層3 6上，及另一電極3 1 〇提 供於η，鎵砰基材31之相反侧上。 發光二極體例如可製造如下a 首先，提供主平面自（1〇〇)平面傾向[011]方位大約5。之n_ 鎵砷基材31，隨後，具有大約0.5微米厚度之卜AlxGai.xAs (0 S X s 1 ;在此例子中x=〇且矽濃度例如大約5xl0p厘米-3) 第一缓衝層38係利用一 MOCVD方法，以大約600至700°C之 生長溫度生長於η-鎵碎基材31上。 隨後’弟一說_衝層32.、光反射層39、第一艘層33、主動 層34、第二鍍層35、及電流擴散層3.6係以大約700至850°C 生長溫度依此順序沉積於第一缓衝層3 8上。第二緩衝層3 2 具有大約〇.〇5微米厚度及一.11_八1/冱2111卜^?组合物（〇57含1 -20- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） {請先閱讀背面之注意事項故#寫本頁) 裝.！ — 1!— 訂 i — — i _ ：M4 65 1 2 7 A7 B7 五、發明說明（ 'if 齊 ϊΡ 且0 g z S 1 ;在此例子中y=〇 3，z=0 〇且矽濃度例如大約 5叉1017厘米·3),光反射層39具有一 n_鋁砷/鎵砷組合物及包 括十對η-鋁砷/鎵砷層，各對則具有例如I 〇〇埃厚度。第一鍍 層·^具有大約1.0微米厚度及一 n-AisGatIni s tP組合物（〇 g 1且0 g t S 1 ;在此例子中s=〇_5，t=〇 〇且矽濃度例如大約 5xl017厘米-3)，主動層34具有大約〇 5微米厚度及一 AlaGabIn!_a.bP組合物（〇 g a s 1且0 S. b S 1 ;.在此例子中例如 a=〇.4，b=0.5)，第二鍍層35具有大約1.0微米厚度及一p_ AlcGadllikdP組合物（〇 g。$ 1且〇 g d运1 ;在此例子中c=〇.5 ，d=0,5且鋅濃度例如大約5xl017厘米·3)，電流擴散層36具 有太約5微米厚度及一 infAigGau-gP組合物（0<f< 1且〇<g < 1 ;在此例子中f=〇.〇.i ’ g=0.01且鋅濃度例如大约5xl〇ls厘 米·3)。隨後製成電極311、310而完成發光二極體。 如實施例1者，本實施例之發光二極體中，將卜鎵砷基材 31之主平面自（1〇〇)平面傾向[〇11]方位之效果十分顯著，其 針對緩衝層而採用一雙層結構，包括n_AlxGaixAs 第一緩衝層38及n-AlyGa2In〖个ZP (OSySl且OSzSl)第二缓 衝層32，且設定基材侧鍍層（即第一鍍層33)之鋁含量高於第 二緩衝層3 2者。結果，發光段特別是主動層3 4者之結晶度 大幅改善，藉此大幅改善放射效率。在本實施例中，光反 射層39係提供於第二緩衝層32與第一鍍層33之間，在本實 施例中可取得相似於實施例1者之效果。 若第二緩衝層之生長溫度等於本實施例中之第一鍍層者 ’則可取得一較陡之生長介面，因此，藉由適度設定第二 -21 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ------------裝 i — ./、 (請先閲讀背面之注意事現再«'窝本買) 'tr: 4 651 2 7 a7___ ___B7______五、發明說明（19 ) 緩衝層之组合物不同於第一鍍層者，可取得比第一鍍層直 接生長於第一緩衝層上時爲佳之結晶度。再者，在本實施 例中’基材之主平面係以.一大約5。角自（1〇〇)平面傾向[011] 方位.，因此，基材之製造成本可低於實施例1之傾斜角大約 15°基材者。 在本實施例中提供光反射層3 9，結果由基材3 1吸收之一 部分所生光線可由光反射層39反射，因此其可自裝置抽離 ’藉以改善所生光線之使用效率。 (實施例4) 如本發明半導體發光裝置之再一實施例者，一鋁鎵銦磷 型發光二極體將説明之。實施例4相同於實施例1，例外的 是⑴製成第二緩衝層後异高生長溫度，及（ii)隨後生長第一 鏡層β 圖6係一簡示截面圖，説明本實施例之發光二極體結構， 發光一極體包括一 η-鎵坤基材41，其主平面係以一太約2。角 自（100)平面傾向[〇Η]方位。發光二極體進一步包括—η_ AlxGai_xAs (0SxS1#—缓衝層 48、—n_AlyGaJniyzP (〇 忘 ysi且oszsi)第二緩衝層42、—n_AlsGatInistP Ostsi)第一鍍層 43、一 AlaGabIniabp (0gasl 且Osbsi) 主動層 44、一p-AlcGaJiik.dP (Ogcgl 且 OSdgl)第二鍍層 45、及一1nfA1sGaw、sP (〇<f<l 且 〇<g<l)電流擴散層 46, 其皆沉積於η-鎵砷基材4〗上。一電極4丨〗係提供於電流擴散 層46上’及另一電極41〇提供於n_鎵砷基材41之相反側上。 發光二極體例如可製造如下。 -22- (請先閱讀背面之注意事項再'填寫本頁) _ 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公楚） A7 B7 20 4.651 2 五、發明說明（ 首先，提供主平面自（100)平_面傾向[011]方位大約2。之.n-鎵砷基材41 ’随後，第一緩衝層48及第二緩衝層42係利用 一 MQCVD方法，以太約600至7〇〇°C之生長溫度生長於η-鎵 砷基材41上。第一緩衝層48具有大約0,5微米厚度及一 η-ALGakAs組合物（OSxSl ;在此例子中χ=〇且矽濃度例如大 約5x10”厘米_3) ’第二緩衝層42具有大約〇.〇5微米厚度及一 n-AlyGaJi^uP組合物（0 S y s 1且0 g z g 1 ;在此例子中 y=0.3，z=0.〇且矽.濃度例如大約5x10"厘米’。 接著，生長溫度昇高至大.約700至850°C，隨後第一鍍層 43、主動層44 .、第二鍍層45、及電流擴散層46依此順序沉 積於第二緩衝層42上。第一鍍層43具有大約1,〇微米厚度及 一 n-AlsGatIn卜s-tP组合物（0 S s S 1且0 s t g 1 ;在此例子中 s=0.5，t=0‘0且發濃度例如大約5χ1017厘米'3) ’主動層44具 有大約0.5微米厚度及一 AlaGabInUa-bP组合物（〇荃asi且 含1 ;在此例子中例如a=0‘4，b=0.:5)，第二嫂層45具有大约 1.0微米厚度及一 p-AlcGaJundP组合物（〇Scgl且OgdSl ;在此例子中c=0.5 ’ d=0.5且鋅濃度例如大約5xi〇,7厘米-3) ，電流擴散層46具有大約.5微米厚度及一 InfAlgGai fgp纽合 物（0 < f < I且0 < g < 1 ;在此例子中f=〇 〇 1，g=〇.〇 1且鋅濃 度例如大約‘5x1018厘米'3)。隨後製成電極411、410而完成發 光二極體。 如實施例1者，本實施例之發光二極體中，將心鎵砰基材 41之主平面自（1〇〇)平面傾向[(31.1]方位之效果十分顯著，其 針對缓衝層而採用一雙層結構，包括n，AlxGai_xAs iOSxSl：) -23- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項一^填.寫本頁) 厂1 裝！！ 1 訂_!": — _ _· * '^4 65 12 ^ A7 ~ --:---- 五、發明說明（） 第一緩衝層 48 及 n-AlyGazIn].y-zP (osysi 且 〇gzgl)第二緩 衝層42 ’且設定基材侧鍍層（即第—鍍層43)之鋁含量高於第 二緩衝層42者。結果，發光段特別是主動層44者之結晶度 大幅改善，即大幅改善放射效率。 (實施例5) 如本發明半導體發光裝置之又再—實施例者，一鋁鎵鋼 蹲型發光二極體將説明之。實施例5相同於實施例1 ,例外 的疋一電流阻斷層58提供於裝置之中央部分，且在—第二 鍍層55及一電流擴散層56之間。 圖7係一簡示截面圖，説明本實施例之發光二極體結構， 發光二極體包括一 η-鎵砷基材51，其主平面係以一大約j 5。 角自（100)平面傾向[0Π]方位。發光二極體進一步包括一第 —緩衝層59、一第二緩衝層52、一第一鍍層53、一主釦層 54及第二鍍層55。第一緩衝層59具有大約〇· 5微米厚度及一 n-AlxGauAs组合物（〇gxSl ;在此例子中X=0JL矽濃度例如 大約5x10”厘米_3) ’第二緩衝層52具有大約〇〇5微米厚度及 一 n-AlyGazIni_y.JP 组合物（Osygi 且 0SzSi ;在此例子中 y=0‘3，z=〇,〇且矽濃度例如大約5χ1〇”厘米弋。第一鍍層53 具有大約1.0微米厚度及一 n-AlsGatli^.^P組合物（〇 g s各1且0 含^1;在此例子中3=〇.5，1=0.0且矽濃度例如大約5乂1017厘 米-3) ’主動層54具有大約0.5微米厚度及一 AUGabInLbP组 合物（0 S a S 1且〇 s b έ 1 ;在此例子中例如a=〇.4，b=0.5)， 第二鍍層55具有大約1·〇微米厚度及一 p-AleGadIni+dP組合 物（OScSl且OsdSl ;在此例子中c = 0.5，d=0.5且鋅濃度例 -24- 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） ------------裝 f諝先閱讀背面之注意事項再炎寫本頁) ί κ ·ϋ IK J .'费 n VI n n f— n 1 « t ' 4 65127 A7 -—____ B7 瘦资Sr Ami才t 五、發明說明（22) 如大約5xl017厘米-3)。—電流阻斷層58提供於第二鍍層55頂 表面之中央部分’電流阻斷層58具有大約〇 5微米厚度及一 η-鎵嶙组合物（此處之鋅濃度大约1χ1〇19厘米，，電流擴散 層56沉積於電流阻斷層58與第二鍍層55曝露表面上，電流 擴散層56具有大約5微米厚度及— infAigGat_f_gP組合物（0< f < 1且0< g< 1 ;在此例子中f=0 〇卜g=〇 〇1且鋅濃度例如大 約5xl〇iS厘米-3)。一電極511係提供於電流擴散層56上，及 另一電極510提供於n-鎵砷基材51之相反側上。 • 在本實施例之發光二極體中，電流阻斷層^8提供於裝置 之中央部分，且在第二鍍層55及電流擴散層56之間。結果 ，自電極511射出之電流係進一步擴散通過電流擴散層56， 藉此可進一步改善光線抽離效率。 (實施例6) 如本發明半導體發光裝置之另一實施例者，一銘鎵銦磷 型發光二極體將説明之。實施例6相同於實施例5，例外的 是一電流阻斷層68提供於裝置之周邊部分，且在一第二鍍 層65及一電流擴散層66之間。 圖8係一簡示截面圖，説明本實施例之發光二極體結構， 發光二極體包括一 η-鎵神基材61，其主平面係以一大約15。 角自（100)平面傾向[0.11]方位。發光二極體進一步包括—第 一缓衝層69、一第二緩衝層62、一第一鍍層63、一主動層 64及第二鍍層65。第一緩衝層69具有大约〇.5微米厚度及一 η-ALGanAs组合物（0含xSl ;在此例子中χ=〇且矽濃度例如 大約5x10"厘米·3)，第二缓衝層62具有大約〇.〇5微米厚度及 -25 - (請先閱讀背面之注意事項再淇寫本頁) .裝 !訂--------:f' 0 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐〉 4 Ss A7 B7 23 五、發明說明（） —n-AlyGaJnbyuP组合物（〇 g y g 1且〇 s z S 1 ;在此例予中 y=0.3 ’ z=〇.〇且矽濃度例如大約5x10”厘米。第一鍍層63 具有大約1‘0微米厚度及一n-AlsGatln^tP組合物（〇妄且〇 Sig 1 ;在此例子中s=〇.5，t=0.0且石夕濃度例如大約5χ1〇17厘 米·3) ’主動層64具有太約〇.5微米厚度及一 合物（0 έ a g 1且0 s b g 1 ;在此例子中例如a=〇 4，b=0.5)， 第二鍍層65具有大约1.0微米厚度及一p_A丨。GadInicdP组合 物（OScSl且Osdgl ;在此例子中c=0,5，d=0.5 JL鋅濃度例 如大約5x10 口厘米·3)。一電流阻斷層68提供於第二鍍層65頂 表面之周邊部分，電流阻斷層68具有大約〇.5微米厚度及一 η-鎵濟組合物（此處之鋅濃度大約ιχι〇!9厘米·3)，電流擴散 層66沉積於電流阻.斷層68與第二鍍層65曝露表面上，電流 擴散層66具有大約5微米厚度及一infAlgGai，f_sP組合物（〇 < f <1且0<g< 1 ;在此例子中f=0.01，g=〇 〇1且鋅濃度例如大 約5x1018厘米3)。一電極611係提供於電流擴散層66上，及 另一電極610提供於η-鎵砷基材61之相反侧上。 在本實施例之發光二極體中，電流阻斷層6S提供於裝置 t周邊部分’且在第二鍍層65及電流擴散層66之間。結果 ，自電極61 1射出之電流係進—步擴散適過電流擴散層& , 藉此可進一步改善光線抽離效率β 依本發明上述所示，將鎵砷基材之主平面自（1〇〇)平面傾 向[011]方位之效果十分顯著，其針對緩衝層而採用一雙層 結構，包括AlxGa丨-xAs (0SXS1)第—緩衝層及AlyGa」ni^zP (OSySlJLOSzSl)第二缓衝層。結果，其可取得一半導體 -26- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) Λ^^ i.— ιι 丨—丨訂 ί 丨！-7· - _ _ 46512 746512 7 V. Description of Invention (17) Semiconductor light-emitting diodes will be described. Example 3 is the same as Example 1 except that the inclination angle of the main plane of the base material is set to about 5. ((2) The growth temperature of the second buffer layer is equal to the first plating layer, and (ill) provides a light reflecting layer. Figure 5. System-a schematic cross-sectional view illustrating the light-emitting diode structure of this embodiment, the light-emitting diode The body includes an n • gallium arsenic substrate 31, the main plane of which is-approximately 5. The angle is inclined toward the [011] direction from the (100) plane. The light-emitting diode further includes AlxGai.xAs (0SxS1) first buffer Layer 38, _n_AlyGazu (Os y-1 and Oszgl) first buffer layer 32, an n-plane pop / gallium light reflective layer 39, --n'AlsGatIni.tP (0 S s S 1 and 0st S 1 ) A first plating layer 33, an AlaGabIn "a_bP (OsaSl and Osbsi) active layer 34, a p-AlcGaJiii.cd P (OScSl and Osdgl) second plating layer 35 ', and an lnt.AlgGau.gP (〇 < f < 1 and 0 < g < l) a current diffusion layer 36, which are all deposited on the core gallium substrate 31. The electrode 3 is provided on the current diffusion layer 36, and the other electrode 3 1 is provided on η On the opposite side of the gallium base material 31. For example, a light-emitting diode can be manufactured as follows: a First, the main plane is provided with a (011) orientation of about [011] about 5. The n_ gallium arsenic substrate 31, and then, With about 0.5 micro Thickness AlxGai.xAs (0 SX s 1; in this example, x = 0 and silicon concentration, for example, about 5x10p cm -3) The first buffer layer 38 is grown by a MOCVD method at about 600 to 700 ° C. The temperature is grown on the η-gallium chip substrate 31. Subsequently, the brother said that the punching layer 32, the light reflecting layer 39, the first boat layer 33, the active layer 34, the second plating layer 35, and the current diffusion layer 3.6 are based on A growth temperature of about 700 to 850 ° C is deposited in this order on the first buffer layer 38. The second buffer layer 3 2 has a thickness of about 0.05 micrometers and a combination of .11_eight 1 / 冱 2111 and ^? (〇57including 1 -20- This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 mm) {Please read the precautions on the back first so write this page)) i — — i _: M4 65 1 2 7 A7 B7 V. Description of the invention ('if ϊΡ and 0 gz S 1; in this example y = 〇3, z = 0 〇 and the silicon concentration is, for example, about 5 forks 1017 cm 3), the light reflecting layer 39 has an n_aluminum arsenic / gallium arsenic composition and includes ten pairs of n-aluminum arsenic / gallium arsenic layers, each pair having a thickness of, for example, 100 angstroms. The first plating layer has approximately 1.0 micron thickness and a n -AisGatIni s tP composition (0 g 1 and 0 gt S 1; in this example s = 0-5, t = 0 0 and silicon concentration, for example, about 5 x 1017 cm -3), the active layer 34 has a thickness of about 0 5 microns And an AlaGabIn! _A.bP composition (0 gas 1 and 0 S. b S 1;. In this example, a = 0.4, b = 0.5), the second plating layer 35 has a thickness of about 1.0 micrometer and a p_ AlcGadllikdP composition (0 g. $ 1 and 0 gd and 1; in this example, c = 0.5, d = 0,5 and zinc concentration, for example, about 5 × 1017 cm · 3), the current diffusion layer 36 has a thickness of about 5 micrometers and an infAigGau-gP combination (0 < f < 1 and 0 < g <1; in this example f = 0.00.i 'g = 0.01 and zinc concentration, for example, about 5 x 10 ls cm · 3). The electrodes 311 and 310 are then fabricated to complete the light emitting diode. As in Example 1, in the light-emitting diode of this embodiment, the effect of aligning the main plane of the pallium arsenic substrate 31 from the (100) plane to the [〇11] direction is very significant, and it is adopted for the buffer layer. A two-layer structure including a first buffer layer n_AlxGaixAs 38 and a second buffer layer 32 of n-AlyGa2In ZP (OSySl and OSzSl), and the aluminum content of the substrate-side plating layer (that is, the first plating layer 33) is set to be higher than that of the first Two buffer layers 3 2 of them. As a result, the crystallinity of the light emitting segment, especially the active layer 34, is greatly improved, thereby greatly improving the radiation efficiency. In this embodiment, the light reflection layer 39 is provided between the second buffer layer 32 and the first plating layer 33. In this embodiment, an effect similar to that of the first embodiment can be obtained. If the growth temperature of the second buffer layer is equal to that of the first plating layer in this embodiment, a steeper growth interface can be obtained. Therefore, by appropriately setting the second -21-this paper size applies the Chinese National Standard (CNS) A4 size (210 X 297 mm) ------------ install i — ./, (please read the precautions on the back before «'woben buy)' tr: 4 651 2 7 a7___ ___B7______ V. Description of the Invention (19) The composition of the buffer layer is different from that of the first plating layer, and can obtain better crystallinity than when the first plating layer is directly grown on the first buffer layer. Furthermore, in this embodiment, the main plane of the 'substrate is about -5. The angle tends to the [011] orientation from the (100) plane. Therefore, the manufacturing cost of the substrate can be lower than that of the substrate with an inclination angle of about 15 ° in Example 1. In this embodiment, a light reflection layer 39 is provided. As a result, a part of the light generated by the substrate 31 can be reflected by the light reflection layer 39, so it can be extracted from the device to improve the efficiency of the generated light. (Embodiment 4) As another embodiment of the semiconductor light emitting device of the present invention, an aluminum gallium indium phosphorus type light emitting diode will be described. Embodiment 4 is the same as Embodiment 1, except that the growth temperature is very high after the second buffer layer is made, and (ii) the first mirror layer β is subsequently grown. FIG. 6 is a schematic cross-sectional view illustrating this embodiment. A light-emitting diode structure. The light-emitting diode includes a η-gallium substrate 41, and its main plane is about 2 to about 2. The angle is inclined towards the [〇Η] direction from the (100) plane. The light-emitting diode further includes -η_AlxGai_xAs (0SxS1 # -buffer layer 48, -n_AlyGaJniyzP (〇 forgetysi and oszsi) second buffer layer 42, -n_AlsGatInistP Ostsi) first plating layer 43, an AlaGabIniabp (0gasl and Osbsi) active Layer 44, a p-AlcGaJiik.dP (Ogcgl and OSdgl) second plating layer 45, and a 1nfA1sGaw, sP (0 < f < l and 〇 < g < l) current diffusion layer 46, which are all deposited on η- Gallium arsenic substrate 4}. One electrode 4 丨 is provided on the current diffusion layer 46 'and the other electrode 410 is provided on the opposite side of the n-GaAs substrate 41. The light emitting diode can be manufactured, for example, as follows. -22- (Please read the notes on the back before you fill out this page) _ This paper size is applicable to China National Standard (CNS) A4 (210 X 297 Gongchu) A7 B7 20 4.651 2 5. Description of the invention (First, provide The main plane has a [011] orientation about (100) from the plane. The n-gallium arsenic substrate 41 ′ is followed by the first buffer layer 48 and the second buffer layer 42 using an MQCVD method, and the ether is about 600. Grow to a growth temperature of 700 ° C. on the η-gallium arsenic substrate 41. The first buffer layer 48 has a thickness of approximately 0,5 micrometers and a η-ALGakAs composition (OSxSl; in this example, χ = 0 and The silicon concentration is, for example, about 5 × 10 ”cm_3). The second buffer layer 42 has a thickness of about 0.05 μm and an n-AlyGaJi ^ uP composition (0 S ys 1 and 0 gzg 1; in this example, y = 0.3 , Z = 0.〇 and the silicon concentration is, for example, about 5x10 " cm '. Then, the growth temperature is increased to about 700 to 850 ° C, and then the first plating layer 43, the active layer 44, the second plating layer 45, and The current diffusion layer 46 is deposited on the second buffer layer 42 in this order. The first plating layer 43 has a thickness of about 1.0 micron and an n-AlsGatIn s-tP composition (0 S s S 1 and 0 stg 1; in this example, s = 0.5, t = 0′0, and hair concentration, for example, about 5 × 1017 cm’3) The active layer 44 has a thickness of about 0.5 micrometers and an AlaGabInUa-bP composition (〇 asiasi And contains 1; in this example, a = 0'4, b = 0.: 5), the second hafnium layer 45 has a thickness of about 1.0 micrometer and a p-AlcGaJundP composition (0Scgl and OgdSl; in this example) c = 0.5 'd = 0.5 and zinc concentration, for example, about 5 × 0.7 cm-3), the current diffusion layer 46 has a thickness of about .5 microns and an InfAlgGai fgp conjugate (0 < f < I and 0 < g <1; in this example, f = 〇〇1, g = 〇1 and the zinc concentration is, for example, about '5x1018 cm'3). The electrodes 411, 410 are then made to complete the light-emitting diode. One, in the light-emitting diode of this embodiment, the effect of aligning the main plane of the heart gallium substrate 41 from the (100) plane to the [(31.1] orientation] is very significant, and it uses a double for the buffer layer. Layer structure, including n, AlxGai_xAs iOSxSl :) -23- This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back first to fill in. Write this Page) Factory 1 installed !!! 1 order _! &Quot;: — _ _ · * '^ 4 65 12 ^ A7 ~-: ---- 5. Description of the invention () First buffer layer 48 and n-AlyGazIn] .y-zP (osysi and Ogzgl) the second buffer layer 42 ′ and the aluminum content of the substrate-side plating layer (ie, the first plating layer 43) is set higher than that of the second buffer layer 42. As a result, the crystallinity of the light emitting segment, especially the active layer 44, is greatly improved, that is, the radiation efficiency is greatly improved. (Embodiment 5) As another embodiment of the semiconductor light emitting device of the present invention, an aluminum gallium steel squatting type light emitting diode will be described. Embodiment 5 is the same as Embodiment 1, except that the first current blocking layer 58 is provided in the center of the device and is between the second plating layer 55 and a current diffusion layer 56. FIG. 7 is a schematic cross-sectional view illustrating the light-emitting diode structure of this embodiment. The light-emitting diode includes a η-gallium arsenic substrate 51, and its main plane is approximately j 5. The angle is inclined to the [0Π] azimuth from the (100) plane. The light emitting diode further includes a first buffer layer 59, a second buffer layer 52, a first plating layer 53, a main buckle layer 54 and a second plating layer 55. The first buffer layer 59 has a thickness of about 0.5 micrometers and an n-AlxGauAs composition (0 gxS1; in this example, X = 0JL silicon concentration, for example, about 5x10 "cm_3) 'The second buffer layer 52 has about 0. 5 micron thickness and an n-AlyGazIni_y.JP composition (Osygi and OSzSi; in this example, y = 0'3, z = 0, 〇, and the silicon concentration is, for example, about 5 x 10 "cm 弋. The first plating layer 53 has about 1.0 Micron thickness and an n-AlsGatli ^. ^ P composition (0gs each 1 and 0 containing ^ 1; in this example 3 = 0.5, 1 = 0.0 and silicon concentration, for example, about 5 乂 1017 cm -3) ' The active layer 54 has a thickness of about 0.5 μm and an AUGabInLbP composition (0 S a 1 and 0 1; in this example, for example, a = 0.4, b = 0.5), and the second plating layer 55 has about 1 ·. Micron thickness and a p-AleGadIni + dP composition (OScSl and OsdSl; in this example, c = 0.5, d = 0.5, and zinc concentration Example -24- This paper size applies to the Chinese National Standard (CNS) A4 specification (210 x 297 (Mm) ------------ Install f 注意 first read the notes on the back and then write this page) ί κ · ϋ IK J. '费 n VI nnf— n 1 «t' 4 65127 A7 -—____ B7 thin Sr Ami only five t, description of the invention (22), such as about 5xl017 cm -3). -The current blocking layer 58 is provided in the center portion of the top surface of the second plating layer 55. The current blocking layer 58 has a thickness of about 0.05 micrometers and a η-gallium rhenium composition (the zinc concentration here is about 1 x 1019 cm, A current diffusion layer 56 is deposited on the exposed surfaces of the current blocking layer 58 and the second plating layer 55. The current diffusion layer 56 has a thickness of about 5 micrometers and an infAigGat_f_gP composition (0 < f < 1 and 0 < g <1; here In the example, f = 0 〇 g g = 0 〇1 and the zinc concentration is, for example, about 5 × 10 μs cm-3). One electrode 511 is provided on the current diffusion layer 56, and the other electrode 510 is provided on the n-gallium arsenic substrate. 51 on the opposite side. • In the light-emitting diode of this embodiment, a current blocking layer ^ 8 is provided in the center portion of the device and is between the second plating layer 55 and the current diffusion layer 56. As a result, the self-electrode 511 The emitted current is further diffused through the current diffusion layer 56 to further improve the light extraction efficiency. (Embodiment 6) As another embodiment of the semiconductor light emitting device of the present invention, a gallium indium phosphorus type light emitting diode It will be explained. Embodiment 6 is the same as Embodiment 5, with the exception A current blocking layer 68 is provided on the peripheral portion of the device and is between a second plating layer 65 and a current diffusion layer 66. Fig. 8 is a schematic cross-sectional view illustrating the light-emitting diode structure of this embodiment, which emits light. The diode includes a η-gallium base material 61, the main plane of which is about 15. The angle is inclined toward the [0.11] direction from the (100) plane. The light emitting diode further includes a first buffer layer 69, a first Two buffer layers 62, a first plating layer 63, an active layer 64, and a second plating layer 65. The first buffer layer 69 has a thickness of about 0.5 micrometers and a η-ALGanAs composition (0 containing xSl; in this example χ = 〇 and the silicon concentration is, for example, about 5 × 10 " cm · 3), the second buffer layer 62 has a thickness of about 0.05 micron and -25-(Please read the precautions on the back before writing this page). Binding! --------: f '0 This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) 4 Ss A7 B7 23 V. Description of the invention () —n-AlyGaJnbyuP composition (〇 gyg 1 and 〇sz S 1; in this example, y = 0.3 ′ z = 〇.〇 and the silicon concentration is, for example, about 5 × 10 ”cm. The first plating layer 63 has about 1′0 M thickness and an n-AlsGatln ^ tP composition (〇 且 and 〇 Sig 1; in this example s = 0.5, t = 0.0 and stone concentration such as about 5 x 1017 cm · 3) 'active layer 64 has The thickness is too about 0.5 micron and a compound (0 ag 1 and 0 sbg 1; in this example, for example, a = 04, b = 0.5), the second plating layer 65 has a thickness of about 1.0 micron and a p_A 丨. GadInicdP composition (OScSl and Osdgl; in this example c = 0,5, d = 0.5 JL zinc concentration, such as about 5x10 mouth cm · 3). A current blocking layer 68 is provided on a peripheral portion of the top surface of the second plating layer 65. The current blocking layer 68 has a thickness of about 0.5 micrometers and a η-gallium composition (the zinc concentration here is about lmx 0.99 cm). · 3), the current diffusion layer 66 is deposited on the current resistance. The exposed surface of the fault 68 and the second plating layer 65, the current diffusion layer 66 has a thickness of about 5 micrometers and an infAlgGai, f_sP composition (0 < f < 1 and0 & lt g <1; in this example, f = 0.01, g = 0, and the zinc concentration is, for example, about 5x1018 cm3). One electrode 611 is provided on the current diffusion layer 66, and the other electrode 610 is provided on the opposite side of the n-GaAs substrate 61. In the light-emitting diode of this embodiment, the current blocking layer 6S is provided on the peripheral portion of the device t 'and is between the second plating layer 65 and the current diffusion layer 66. As a result, the current emitted from the electrode 61 1 is advanced into a step-diffusion-appropriate overcurrent diffusion layer, thereby further improving the light extraction efficiency β. According to the present invention, the main plane of the gallium arsenic substrate is removed from (1 〇〇) The effect of the plane orientation [011] orientation is very significant. It adopts a double-layer structure for the buffer layer, including the first buffer layer of AlxGa 丨 -xAs (0SXS1) and the second buffer of AlyGa "ni ^ zP (OSySlJLOSzSl) Floor. As a result, it can obtain a semiconductor-26- This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page) Λ ^^ i.— ιι 丨— 丨 Order 丨! -7 ·-_ _ 46512 7
五、發明說明（ 發光裝置，其中發光段特 „ ^ ή 守别疋王動層者之結晶度大幅改善 ，精以改善放射效率。 ::適：：：第二緩衝層之叙合物不同於第一鍍層者， == 光段特別是主動層者之結晶度，藉以改 。二$者，猎由適度設定第二緩衝層之生長溫度 、 、 虱精由逐漸改變第二緩衝層或第一鍍 層之生長溫度，其可谁—w 進步改善發光段特別是主動層者之 結晶度，藉以改善放射效率膝 —、 狀 、 丨双半特別疋顯考效果可預期於 弟-鍍層（館含量大於第二緩衝層之铭含量時，互第二緩 衝廣之想含量等於或大於大狀3，且小於或等於大約〇8。 藉由提供-電流擴散層於第二鍍層上，注入之電流可擴 散通過電流擴散層.，以利有效地使用整個主動層發光，藉 以改鲁放射效率。 、藉由提供一電流阻斷層於第二鍍層與電流擴散層之間， 注入之電流可擴散通過電流擴散層，以利有效地使用整個 主動層發光’藉以改善放射效率^ 藉由提供電流阻斷層於裝置之中央部分内，其可將注入 之電流擴散趨向裝置之周邊部分且有效地將所生之電流抽 離裝置，藉以大幅改善放射效率。 另者，電流阻斷層可提供於裝置之周邊部分内，在此一 例子中’其可定位電流於裝置之令央部分’藉以增大電流 密度且有效地將所生之電流抽離裝置，藉以大幅改善放射 效率。 藉由相關於第一鍍層以提供一光反射層較接近於基材， -27 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） (請先閱讀背面之注意事項杂填寫本頁) m 4 651 2 7 A7 B7 五、發明說明（ 25 由基材吸收之—部分所生光線可由光反射層反射，因此其 可目裝置抽離，藉以大幅改善所生光線之使用效率。 本發明可藉由提供一電流阻斷層及一帽蓋層於第二鍍層 上，以提供一半導體雷射裝置。 在不脱離本發明之精神及範疇下，不同之其他修改型式 可烏習於此技者所知及達成，緣是，申請專利範圍不應視 爲侷限於上述説明中，而應做廣義解釋。 (請先閱讀背面之注意事項再，填寫本頁) ;i.ti:-------tr!---- M. 經濟部智慧財產局員工消費合作社印製 -28« 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）V. Description of the invention (Light-emitting device, in which the light-emitting section is specially improved. The crystallinity of those who move away from the king is greatly improved to improve the radiation efficiency. :: Suitable ::: The composition of the second buffer layer is different For the first coating layer, the crystallinity of the light segment, especially the active layer, can be changed. For the second coating layer, the growth temperature of the second buffer layer is appropriately set, and the lice can gradually change the second buffer layer or the first buffer layer. The growth temperature of the coating can be improved by improving the crystallinity of the light-emitting section, especially the active layer, so as to improve the radiation efficiency. When the content of the second buffer layer is high, the content of the second buffer layer is equal to or greater than 3 and less than or equal to about 0. By providing a current diffusion layer on the second plating layer, the injected current can be diffused. Through the current diffusion layer, in order to effectively use the entire active layer to emit light, thereby improving the radiation efficiency. By providing a current blocking layer between the second plating layer and the current diffusion layer, the injected current can diffuse through the current Diffusion layer, in order to effectively use the entire active layer to emit light, thereby improving radiation efficiency ^ By providing a current blocking layer in the central part of the device, it can diffuse the injected current to the peripheral part of the device and effectively generate the The current is drawn away from the device, thereby greatly improving the radiation efficiency. In addition, a current blocking layer can be provided in the peripheral portion of the device. In this example, 'it can locate the current in the command center portion of the device' to increase the current density. And effectively extract the generated current from the device, thereby greatly improving the radiation efficiency. By relating to the first plating layer to provide a light reflecting layer closer to the substrate, -27 This paper standard applies to China National Standard (CNS) A4 Specifications (210 X 297 public love) (Please read the notes on the back and fill in this page first) m 4 651 2 7 A7 B7 V. Description of the invention (25 Absorbed by the substrate-part of the light generated can be reflected by the light reflection layer, Therefore, the device can be detached by eye, thereby greatly improving the use efficiency of the generated light. The present invention can provide half of the current by providing a current blocking layer and a capping layer on the second plating layer. Body laser device. Without departing from the spirit and scope of the present invention, different other modifications can be learned and achieved by those skilled in the art, because the scope of applying for a patent should not be considered to be limited to the above description, It should be explained in a broad sense. (Please read the notes on the back before filling out this page); i.ti: ------- tr! ---- M. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs -28 «This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)
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| JP4497269B2 (en) * | 2002-08-23 | 2010-07-07 | ソニー株式会社 | Semiconductor laser device and manufacturing method thereof |
| KR100541110B1 (en) * | 2004-06-25 | 2006-01-11 | 삼성전기주식회사 | Method of producing multi-wavelength semiconductor laser device |
| KR100541111B1 (en) * | 2004-06-25 | 2006-01-11 | 삼성전기주식회사 | Method of producing multi-wavelength semiconductor laser device |
| JP4899348B2 (en) * | 2005-05-31 | 2012-03-21 | 信越半導体株式会社 | Method for manufacturing light emitting device |
| JP4694342B2 (en) * | 2005-10-14 | 2011-06-08 | 三菱電機株式会社 | Semiconductor laser device and manufacturing method thereof |
| TWI452716B (en) * | 2007-06-08 | 2014-09-11 | Formosa Epitaxy Inc | Gallium nitride based light emitting diode and manufacturing method thereof |
| JP2012124306A (en) * | 2010-12-08 | 2012-06-28 | Toyoda Gosei Co Ltd | Semiconductor light-emitting element |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2804714B2 (en) | 1988-09-29 | 1998-09-30 | 三洋電機株式会社 | Method for manufacturing visible light semiconductor laser device |
| US5103271A (en) * | 1989-09-28 | 1992-04-07 | Kabushiki Kaisha Toshiba | Semiconductor light emitting device and method of fabricating the same |
| JPH0513881A (en) * | 1990-11-28 | 1993-01-22 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor laser |
| JP3124209B2 (en) | 1994-06-30 | 2001-01-15 | シャープ株式会社 | Method for manufacturing compound semiconductor crystal layer |
| JPH08288544A (en) * | 1995-04-14 | 1996-11-01 | Toshiba Corp | Semiconductor light-emitting element |
| JP2783210B2 (en) * | 1995-09-04 | 1998-08-06 | 日本電気株式会社 | Surface-emitting diode |
-
2000
- 2000-07-19 JP JP2000219898A patent/JP4024463B2/en not_active Expired - Lifetime
- 2000-09-26 TW TW089119840A patent/TW465127B/en not_active IP Right Cessation
- 2000-09-27 US US09/671,777 patent/US6465812B1/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JP2001168382A (en) | 2001-06-22 |
| US6465812B1 (en) | 2002-10-15 |
| JP4024463B2 (en) | 2007-12-19 |
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