4 6 5 0 9 6 Λ7 Β7五、發明説明（）5“發明領域： 經濟部智恶財凌局肖工消赀合作社印鉍4 6 5 0 9 6 Λ7 Β7 V. Description of the invention () 5 "Field of invention: Xiao Gong Xiaoling Cooperative Co., Ltd., Ministry of Economic Affairs
Etv 3¾ 有 是 明 發 本 m e m 別 特 且 NFt (( 體體 憶憶 記記 性電 發鐵 揮種 kr4 一 '一?1 種於 一關 於有 包 月 憶 己 =0 電 失 流 料 資 免 避 鐵， 之流 構電 結漏 封 土 密防 用地 使效 其有 ，以 V)可 Γ 1 ο 1 ΠΊ1) Tleel m c 景 背 明 發 電 中個個 構一兩 結i於 的ET在 體(F存 rl體中 記晶器 在電容 效電 場由 電 機 隨Etv 3¾ There is a Mingfa Ben Mem special and NFt ((body body memory memory electric iron type kr4 a 'one? 1 kind of one on a monthly basis memory = electric power loss material avoids iron The current structure of the electric junction junction can be used to seal the soil and prevent the use of land. V) can be Γ 1 ο 1 ΠΊ1) Tleel mc Jing Beiming constructs one or two ETs (F, rl) The capacitor in the capacitor effect electric field is followed by the motor
Dya 容 之 極 個藉的 一是成 由存造 是儲而 般的化 一料極 胞資層 隐。電 記成介 取構的 存所間 會憶就 荷記也 電取。 的存作 間機操 之隨常 極得正 電使其 個，持 兩電維 在放能 存動才 儲自新 ，而更 而性與 然特電 。 理充 成物地 達的性 所層期 積電週 累介須 荷為必 電因體 料性 資發 I 1 EP 卫# ’ 為 電器 放容 合a 電 荷的 電 用 的使 内所 器 中 容體 電]¾ ， 記 斷般 切一 源， 電此 。 旦因 e 一 ，失01 說流(V 是會的 用鐵 利用 係使 體常 憶通 記 。 之失 器流 容料 電資 電免 鐵避 用以 使質 sliaU 才 0 Jr 一 電 出介 提為 曾作 去料 過材 電 鐵 要質 需材 不電 , 鐵 i— Lti. 丰 itl 資藉 存荷 儲電 地， 效性 有特 以的 可質 ’材 介電 媒鐵 存為 儲因 為是 作要 器主 容 ’ 電新 電更 失 流 而 電 放 為 因 易 容 不 較 積 累 而 匕 極 本紙張尺度適用中國國家標準（CN'S ) A4規格（2丨0X 297公釐）One of Dya Rong's most important things is to make a deposit from a storage or a storage. The electricity will be recorded in the depository of the intermediary structure. The operation of the storage machine is always extremely positive, so that the two power grids can be stored and recharged before they are discharged, and more specifically, they are more special. The physical and electrical properties of the electrical and electronic devices are accumulated in the interim period, and the accumulated charge is required to be generated due to the physical properties of the material. [Bulk] ¾, cut a source like a cut, call this. Once e, lose 01, the flow (V is the use of iron to make the body often remember the Tongji. The loss of fluid capacity, electricity, electricity, electricity, iron, avoiding the use of quality, sliaU, 0, Jr, and electricity. For the old electric iron, the quality of the material and the material is not electricity, iron i—Lti. Feng itl borrowed and stored the electricity storage site, and the efficiency of the material is particularly good. The main capacity of the main device is that the new electricity and electricity are more lost, and the electric discharge is because the capacity is not more accumulated. The paper size is applicable to the Chinese National Standard (CN'S) A4 specification (2 丨 0X 297 mm).
(請先閱讀f-面之注意事項再皮.本百C 装· 線 50 96 A 7 Βη 五、發明説明（ 經濟部智慧財產局員工涓費合作社印製 鐵電材質是藉由施加外部電場來選定或切換極化狀 態，並且在移除外部電場之後，依然能保留其極化狀態。 如熟習此技藝者所知，鐵電電容器可取代傳統在動態隨 機存取（DRAM)記憶體中所使用的二氧化矽電容器，其可 以快速地儲存電荷，並且在電力移除之後，鐵電電容器 依然可以長時間地維持其極化狀態。因此，鐵電材質提 供了發展簡單、低價、高密度、非揮發性記憶體的可能 性。而且 > 傳統的DRAM記憶體容易受到游離輻射的照 射而損壞，鐵電材質對輻射損壞具有很高的阻抗性，其 極化狀態不會因為輻射而改變。此外，鐵電記憶體不需 要很高的操作電壓，且如同傳統的記憶體一般，可以迅 速地進行編寫及讀取°所以，在積體電路記憶體的設計 與製造中，已經逐漸地開始研究及發展鐵電材質的應用。 請參照第1圖，其繪示習知一般丨T -1 C鐵電記憶胞 之結構示意圖。鐵電記憶胞係架構在半導體基底1 〇上， 包括有閘極堆疊層 3 0，以及源極2 2與汲極2 4。閘極堆 疊層3 0係形成在基底10上，源極2 2與汲極2 4分別形 成在閘極堆疊層3 0的兩側。一般閘極堆疊層3 0為金屬-鐵電-金屬-絕緣-矽層（M F ΜIS)結構，半導體基底1 0由磊 晶矽構成，其上包括由下而上堆疊之閘極介電層3 2、下 電極3 4、鐵電層3 6與上電極3 8。源極2 2與汲極2 4分 別經由源極線與汲極線連接到外部電路’閘極（即上電極 位置3 8)則經過字元線W L連接到控制電晶體5 0的源極/ 汲極，藉由控制電晶體50的開關決定是否施加電壓於此 先 閱- 背· ιέ 之- 注 意 言 再 太 ¥ 裝(Please read the precautions on the f-face first, and then peel it. This hundred C installed · line 50 96 A 7 Βη V. Description of the invention (The employee of the Intellectual Property Bureau of the Ministry of Economic Affairs, the staff of the cooperative, printed the ferroelectric material by applying an external electric field. Select or switch the polarization state, and retain its polarization state after removing the external electric field. As is known to those skilled in the art, ferroelectric capacitors can replace the traditional use in dynamic random access (DRAM) memory Silicon dioxide capacitors, which can store charge quickly, and ferroelectric capacitors can maintain their polarization state for a long time after power is removed. Therefore, ferroelectric materials provide simple development, low cost, high density, Possibility of non-volatile memory. And > Traditional DRAM memory is susceptible to damage by free radiation. The ferroelectric material has high resistance to radiation damage, and its polarization state will not change due to radiation. In addition, ferroelectric memory does not require a high operating voltage, and can be programmed and read quickly like traditional memory. So, In the design and manufacture of memory, the research and development of ferroelectric materials have gradually begun. Please refer to Figure 1, which shows the structure of a conventional general T -1 C ferroelectric memory cell. Ferroelectric memory cell The architecture is on the semiconductor substrate 10, and includes a gate stack layer 30, and a source 22 and a drain 24. The gate stack layer 30 is formed on the substrate 10, and the source 22 and the drain 2 4 are formed on both sides of the gate stack layer 30. Generally, the gate stack layer 30 has a metal-ferroelectric-metal-insulation-silicon layer (MF MIS) structure, and the semiconductor substrate 10 is composed of epitaxial silicon. The gate includes a gate dielectric layer 3 2, a bottom electrode 3 4, a ferroelectric layer 36, and an upper electrode 38, which are stacked from bottom to top. The source 22 and the drain 2 4 pass through the source line and the drain line, respectively. Connected to the external circuit 'gate (ie, upper electrode position 3 8) is connected to the source / drain of the control transistor 50 through the word line WL. The switch of the control transistor 50 determines whether a voltage is applied before this. Reading-back · ιwich--note words too too ¥ equipment
1T 線 本紙張尺度適用中國國家標準（CNS ) Λ4规格（2Ι0Χ 297公釐） A 7 B7 46 50 9 6 五、發明説明 記憶胞 接著請參照第2圖1其繪示習知之鐵電記憶胞在充 電之後的電荷分佈狀態°當我們施加正電壓 VG至閘極 堆疊層3 0時，正電荷進入閘極堆疊層3 0並在此累積， 同時鐵電層 3 6受電場影響而極化，此時極化方向為向 上，在閘極堆疊層3 0的電荷分佈，如圖中所示。在鐵電 層3 6與上電極3 8之間，正電荷與負電荷中和，其淨電 荷為零，同樣地，在鐵電層3 6與下電極3 4之間的淨電 荷亦為零，只有在下電極3 4與閘極介電層3 2之間存在 正的淨電荷，資料即是藉由此充電步驟存入鐵電記憶胞 中。然而，使用此結構會有漏電流的問題1主要是因為 控制電晶體5 0的源極/汲極是形成在基底1 〇中，且不容 易控制其漏電流發生，鐵電記憶胞中所儲存的電荷容易 經過字元線W L，從電晶體5 0的源極/汲極處漏出’因而 造成電荷流失，此會導致資料保留的時間縮短’更嚴重 時會造成資料流失。 請. 先 閱- 請 背， 面 之 注 意 事 項 再 ▲ 頁 述 概 及 的 目 明 發 經濟部智笼財產局負工消f合作社印製 容明 構發 結本 胞1 憶此 記因 電 。 鐵短 的縮 統間 傳時 ，存 中保 景料 背資 明成 發造 之， 述流 上電 於漏 鑒生 產 易 堆之加 極線增 閘元， 在字失 ， 與流 胞層荷 憶疊電 記堆的 電極存 鐵閘儲 型得内 封使層 密，# 種層堆 1 電極 供介閘 提層免 ，一 避 求覆 , 需包離 述部隔 上外夠 對層能 針疊間 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） 4 6 5〇9〇 a? Ϊ37 經濟部智慧財產局Β工消f合作社印製 五、發明説明（ ) ! i 資 料 保 存 的 時 間 〇 1 1 I 本 發 明 提 供 一 種 密 封 型 鐵 電 記 憶 胞 之 結 構 係 架 構 1 1 在 一 半 導 體 基 底 上 其 至 少 包 括 一 堆 疊 電 容 閘 極 形 請， 先 ! 間 ! 成 在 基 底 上 以 及 — 源 極 與 一 汲 極 形 成 在 堆 τβ 電 容 閘 讀 背· I i 極 兩 側 之 基 底 中 〇 堆 疊 電 容 閘 極 包 括 有 一 間 極 介 電 層 ιΐί 之- i 注 1 形 成 在 基 底 上 一 下 電 極 形 成 在 閘 極 介 電 層 上 一 鐵 意 ψ 1 電 層 j 形 成 在 下 電 極 上 一 上 電 極 形 成 在 鐵 電 層 上 項 再 1 1 一 密 封 層 覆 蓋 且 密 封 上 電 極 、 鐵 電 層 下 電 極 、 閘 極 本 I 裝 堆 疊 層 以 及 一 外 電 極 形 成 在 密 封 層 上 且 位 在 鐵 電 頁 、·_- 1 1 層 的 上 方 0 其 中 密 封 層 係 由 介 電 材 質 所 構 成 如 氧 化 I I 鈦 氡 化 錯 與 氧 化 鋁 等 〇 鐵 電 層 則 由 低 介 電 常 數 之 鐵 電 i f 材 質 所 構 成 j 如 鈦 酸 Μ 外 電 極 藉 由 施 加 電 場 決 定 鐵 1 i 電 層 的 極 化 方 向 以 儲 存 資 料 由 於 有 密 封 層 的 隔 絕 訂 I 因 此 儲 存 的 電 何 被 密 封 在 密 封 層 内 不 會 與 外 部 連 接 造 1 1 成 漏 電 流 ί 影 響 資 料 的 儲 存 〇 1 1 5- 4 9 式簡單說明 1 1 線 ] 本 發 明 的 較 佳 實 施 例 將 於 往 後 之 說 明 文 字 中 輔 以 下 1 ! 列 圖 形 做 更 詳 細 的 闡 述 ! I 第 1 1繪示習 知一 種 趨 電 記 憶 體 的 結 構 鐵 電 記 憶 1 1 胞 之 問 極 堆 疊 電 容 中 的 上 電 極 經 由 字 元 線 連 接 到 控 制 電 I I 晶 體 的 源 極 / >及極區^ 並 且 造 成 漏 電 流 0 1 i 第 2 圖繪示習 知之鐵電 記 5 情 胞 在 充 之 後 的 電 J··#- 何 分 i i 1 I I ! 本紙張尺度適用中國國家標準（CNS ) A4規格（210Χ2()7公釐） 經濟部智惡財產局Μ工消費合作社印製 16 5 0 9':: a? B7 五、發明説明（） 佈狀態。 第3圖繪示本發明之一較诖實施例的結構剖面示意 圖。 第4圖繪示本發明之鐵電記憶胞在充電之後的電荷 分佈狀態。 第5圖繪示本發明之堆疊電容閘極的等效電路圖。 第6圖繪示本發明之鐵電記憶胞的等效電路圖。 第7圖繪示本發明之鐵電記憶胞的操作方法。 圖號對照說明： 10 基底 22、 2 4 源極/汲_極區 32 閘極氧化層 34 下電極 36 鐵電層 38 上電極 50 控制電晶體 WL 字元線 100 基底 122 ' 124 源極/汲極區 132 閘極氧化層 134 下電極 L36 鐵電層 138 上電極 200 介電層 202 外電極 vG 閘極電壓 5-5發明詳細說明： 本發明揭露一種密封型鐵電記憶胞，在閘極堆疊層 的外部包覆一層介電層，使儲存電容與字元線隔離’可 6 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X 297公釐） —[ I 私衣 11 Ί .~~. 線 (請先閲讀背面之注意事項再11.本頁) ( G _ 經濟部智慧財產局員工消費合作社印製 4 _____ B7五、發明説明（） 以使資料完整地儲存在電容器中，避免漏電流產生，使 資料保存的時間更長。 首先將對本發明之密封型鐵電記憶胞的結構進行說 明。請參照第3圖，其繪示本發明之較佳實施例的結構 剖面示意圖。本發明之鐵電記憶胞係架構在半導體基底 1 0 0上，比如是矽基底。本發明之鐵電記憶胞主要由堆 疊電容閘極，以及位在堆疊電容閘極兩側的源極與汲極 所構成。其中，堆疊電容閘極係形成在基底1 〇 〇上，包 括有傳統的閘極堆疊層1 3 0，包覆且密封閘極堆疊層1 3 0 的密封層200，以及形成在密封層200上的外電極202, 連接至外部的字元線1或是外電極 2 0 2本身即為字元線 的一部份。 閘極堆疊層 1 3 0以傳統的 M F ΜI S結構為例進行說 明，其包括由下向上堆疊之閘極介電層132'下電極134、 鐵電層1 3 6與上電極1 3 8。其中，閘極介電層1 3 2比如 是由二氧化矽（S i Ο 2)所構成，下電極 1 3 4的構成材質比 如是翻（Pt)、銀（Ir)或是氧化銀（IrO；；)等，上電極138的 構成材質則對應於下電極1 34，比如是鉑（Pt) '銥Π〇或 是氧化銥（Ir〇2)等，除了上述舉例的材質外，其他適用 於M F ΜI S結構之材質亦可。至於鐵電層1 3 6的構成材 質比如是鈦酸鉛锆（ΡΖΤ)或是鈦酸勰鉍（SBT)等，然而基 於電性考量，本發明所使用鐵電層 1 3 6的材質以具有較 低介電常數的鐵電材質較诖’比如是s Β τ等。 ί請先閱讀背面之注意事項再填^ .4買) 裝 訂 線 7 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X 297公釐） 經濟部智慧財產局員工消費合作社印製 ^ 6 5 0 9 5 A7 ___B7___ 五、發明說明（） 另外，密封層 2 0 0係使用介電材質，藉以對閘極堆 疊層1 3 0與字元線W L之間提供良好的隔離，防止儲存 電荷流失。密封層2 0 0對閘極堆疊層1 3 0具有良好附著 性，所使用的介電材.質比如是氧化鈦（TiO:)、氧化鍅（ZrO:) 或是氧化鋁（A12 Ο 3)等。至於外電極2 0 2則使用一般的導 電材料，比如是紹（A 1)或銅（:C u)等。 由於此結構之製程多為熟習此技藝者所熟知之技 術，所以僅作簡單的說明，但並不因此限制本發明結構 之製造方法。首先在基底 1 0 0上依序沉積閘極介電層 1 3 2、下電極1 3 4、鐵電層1 3 6與上電極1 3 8。接著定義 出閘極堆疊層1 3 0的圖案。然後比如以離子植入法在閘 極堆疊層1 3 0兩側形成源極/汲極1 2 2與1 2 4。之後在閘 極堆疊層130外部暴露的表面覆蓋一層密封層 200。| 後在密封層200上且在鐵電層136上方形成外電極202。 如此即完成本發明之密封型鐵電記憶胞。 請參照第4圖，其繪示本發明之鐵電記憶胞在充電 之後的電荷分佈狀態。本發明係利用外電極202所產生 的電場極化鐵電層 1 3 6，同時在閘極堆疊層 1 3 0内形成 分離的電荷分佈，藉以儲存資料。外電極2 0 2連接字元 線W L (請參照第1圖），藉由切換控制電晶體5 0的開關， 控制施加於外電極2 0 2的電壓，當我們經由外電極 202 施加正電壓V g至閘極堆疊層 U 0時’鐵電層1 3 ό内的 8 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --I----------*-!^·----Γ---訂---------'^一 I (請先閱讀背面之注意事項再填寫本頁> 經濟部智慧財產局員工消費合作社印製 465096 A7 _____B7___ 五、發明說明（） 偶極受到電場影響而極化向上 '同時上電極1 3 8與下電 極1 3 4内亦受電場影響形成分離的電荷分佈，如圖中所 示。在上電極1 3 8與鐵電層1 3 6之間的淨電荷為零，同 樣地在鐵電層1 3 6與下電極1 3 4之間的淨電荷亦為零。 只有在上電極1 3 8頂部的負電荷與下電極1 3 4底部的正 電荷為有效電荷。資料即藉由此步驟存入電容器中。 當施加的外部電壓VG移除之後，由於鐵電材質本身 的特性，在外加電場移除之後依然能保持其極化方向， 如此使得儲存的資料得以保存。由於本發明於閘極堆疊 層1 3 0的外部包覆一層密封層2 0 0，儲存在閘極堆疊層1 3 0 内的電荷即因為密封層 2 0 0的包覆，因此不會有電荷流 失的現象發生。此外，儲存於閘極堆疊層 1 3 0内的電荷 因為鐵電層1 3 6的極化而分離，加上正負電荷相距甚遠， 約大於0.6微米（/Z m )，因此不容易發生電荷中和的問題。 請參照第5圖，其繪示本發明之堆疊電容閘極的等 效電路圖，為三個電容串接1其中分別代表閘極介電層 132、鐵電層136與密封層200。由於在鐵電層136的上 方增加一層密封層 200，會改變整體的等效電容值，其 偶合比率（c 〇 u p 1 i n g r a t i 〇)就顯得重要，因此鐵電層 136 的電容值必須較小，以增加作用在鐵電層 1 3 6的有效電 場。所以，鐵電層 1 3 6所使用的材質以低介電常數的鐵 電材質較佳，比如是S B T。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ft ^^1 —fc ^^1 -n ^iF ί —Λ. r * t— ^^1 n n ^^1 I" 『< n n ^^1 I n I (請先閱讀背面之注意事項再填寫本頁) 4 6 5l A7 ____B7_ 五、發明說明（） 接著將對本發明之鐵電記憶胞的操作方法進行說 明。請同時參照第6圖與第7圖，第6圖繪示本發明之 鐵電記憶胞的等效電路示意圖。編寫的方法是在閘極 G 施加或是' VDD ’此時基底接地，即可將資料” 1或”0‘， 寫入記憶胞中°讀取的方法可以在閘極G施加電壓Vr， 該V r值介於” 0 ”和Γ’的臨界電壓之間，由電晶體的開和 關判別和”1 ’’。 綜合以上所述，本發明揭露一種密封型鐵電記憶胞， 可以使鐵電電容器中所儲存的電荷資料密封，不會因為 與外部電路連接而發生漏電流，可延長資料在記憶胞中 的保存時間。 以上所述僅為本發明之較佳實施例而已，並非用以 限定本發明之申請專利範圍，凡其它未脫離本發明所揭 示之精神下所完成之等效改變或修飾，均應包含在下述 之申請專利範圍内。 ί ι 1^1 rjt t/ψ \ 1^1 I - I— II n i ^1· T—··> 1 n 1^1 n n I / i-a j {請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用+國國家標準（CNS)A4規格mo X 297公.¾ )The paper size of the 1T line is applicable to the Chinese National Standard (CNS) Λ4 specification (2Ι0χ 297 mm) A 7 B7 46 50 9 6 V. Description of the invention Memory cell Then please refer to Figure 2 for a description of the conventional ferroelectric memory cell. Charge distribution after charging ° When we apply a positive voltage VG to the gate stack layer 30, the positive charge enters the gate stack layer 30 and accumulates there. At the same time, the ferroelectric layer 36 is polarized by the influence of the electric field. When the polarization direction is upward, the charge distribution in the gate stack layer 30 is shown in the figure. Between the ferroelectric layer 36 and the upper electrode 38, the positive and negative charges are neutralized, and its net charge is zero. Similarly, the net charge between the ferroelectric layer 36 and the lower electrode 34 is also zero. Only if there is a positive net charge between the lower electrode 34 and the gate dielectric layer 32, the data is stored in the ferroelectric memory cell through this charging step. However, the problem of leakage current using this structure 1 is mainly because the source / drain of the control transistor 50 is formed in the substrate 10, and it is not easy to control the leakage current of the transistor, which is stored in the ferroelectric memory cell. The charge easily leaks through the word line WL and leaks out from the source / drain of the transistor 50, thus causing a charge loss, which will lead to a shorter data retention time, and more serious data loss. Please. Please read it first-please memorize the items above. ▲ The general description of the page is issued by the Ministry of Economic Affairs, the Cage Property Bureau, the Ministry of Economic Affairs, and the cooperative printed by Rong Ming. When the iron was shortened and passed down from time to time, the deposits and guarantees were created by the backstory, and the electricity was added to the gate to increase the sluices in the easy-to-repair production process. The electrode deposit iron gate of the telegraph reactor is sealed in the inner layer to make the layer dense. # Seed layer stack 1 electrode is provided for the gate to lift the layer. One avoids the need to cover. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 4 6 5090a? Ϊ37 Printed by the Intellectual Property Bureau of the Ministry of Economics, B Industrial Consumers Cooperative Society, Fifth, the description of the invention ()! I Data storage The time 〇1 1 I The present invention provides a structure of a sealed ferroelectric memory cell structure 1 1 on a semiconductor substrate which includes at least a stacked capacitor gate shape, please! First! On the substrate and-source A drain is formed in the substrate on both sides of the stack τβ capacitor gate readback. The stacked capacitor gate includes: Intermediate dielectric layer ιΐί-i Note 1 Formed on the substrate Lower electrode formed on the gate dielectric layer An iron ψ 1 Electrical layer j formed on the lower electrode An upper electrode formed on the ferroelectric layer 1 1 A sealing layer covers and seals the upper electrode, the lower electrode of the ferroelectric layer, the stacking layer of the gate electrode, and an external electrode formed on the sealing layer and located above the ferroelectric page, 1- 0 1 of which the sealing layer It is made of dielectric materials such as oxide II, titanium halide, alumina, etc. 0 Ferroelectric layers are made of ferroelectric if materials with low dielectric constant j, such as titanic acid M, external electrodes determine iron by applying an electric field 1 i The polarization direction of the electrical layer is used to store the data. Due to the isolation of the sealing layer, the stored electricity is sealed in the sealing layer and will not be connected to the outside to create a leakage current. 1 Affects the storage of data. 1 1 5-4 9 Simple description 1 1 line] The preferred embodiment of the present invention will be supplemented by the following 1! Column graphics to explain in more detail! I Chapter 1 1 shows a trend Structure of the electrical memory Ferroelectric memory 1 1 The upper electrode in the stacked capacitor of the cell is connected via the word line to the source of the control circuit II crystal and the electrode region ^ and causes a leakage current of 0 1 i Figure 2 Demonstration of the ferroelectric memory 5 of the acquaintances after the charge J ·· #-Ho Fen ii 1 II! This paper size applies the Chinese National Standard (CNS) A4 specification (210 × 2 () 7 mm) Ministry of Economic Intelligence Printed by the Property Bureau, M Industrial Consumer Cooperative, 16 5 0 9 ':: a? B7 V. Description of Invention () Distribution status. Fig. 3 is a schematic structural cross-sectional view of a comparative embodiment of the present invention. Fig. 4 shows the charge distribution state of the ferroelectric memory cell of the present invention after charging. FIG. 5 shows an equivalent circuit diagram of the stacked capacitor gate of the present invention. FIG. 6 is an equivalent circuit diagram of the ferroelectric memory cell of the present invention. FIG. 7 illustrates the operation method of the ferroelectric memory cell of the present invention. Description of drawing numbers: 10 substrate 22, 2 4 source / drain region 32 gate oxide layer 34 lower electrode 36 ferroelectric layer 38 upper electrode 50 control transistor WL word line 100 substrate 122 '124 source / drain Polar region 132 Gate oxide layer 134 Lower electrode L36 Ferroelectric layer 138 Upper electrode 200 Dielectric layer 202 External electrode vG Gate voltage 5-5 Detailed description of the invention: The present invention discloses a sealed ferroelectric memory cell, which is stacked on the gate The outer layer of the layer is covered with a dielectric layer to isolate the storage capacitors from the character lines. The size of the paper is applicable to the Chinese National Standard (CNS) Λ4 specification (210X 297 mm) — [I 私 衣 11 Ί. ~~. (Please read the precautions on the back first and then this page) (G _ Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy 4 ___ B7 V. Description of the invention () so that the information is completely stored in the capacitor to avoid leakage current The data is stored for a longer time. First, the structure of the sealed ferroelectric memory cell of the present invention will be described. Please refer to FIG. 3, which is a schematic structural cross-sectional view of a preferred embodiment of the present invention. Ferroelectric The memory cell system is structured on a semiconductor substrate 100, such as a silicon substrate. The ferroelectric memory cell of the present invention is mainly composed of a stacked capacitor gate, and a source and a drain located on both sides of the stacked capacitor gate. Among them, The stacked capacitor gate is formed on the substrate 100, and includes a conventional gate stacked layer 130, a sealing layer 200 covering and sealing the gate stacked layer 130, and a sealing layer 200 formed on the sealing layer 200. The external electrode 202, which is connected to the external word line 1 or the external electrode 2 0 2 is a part of the word line itself. The gate stack layer 130 is described by taking a conventional MF MEMS structure as an example. It includes a gate dielectric layer 132 ', a lower electrode 134, a ferroelectric layer 136, and an upper electrode 138, which are stacked from bottom to top. The gate dielectric layer 1 3 2 is, for example, silicon dioxide (S i Ο 2) The material of the lower electrode 1 3 4 is, for example, Pt, silver (Ir), or silver oxide (IrO ;;). The material of the upper electrode 138 corresponds to the lower electrode 1 34, such as It is platinum (Pt), iridium Π〇 or iridium oxide (Ir〇2), etc. In addition to the above examples, other materials are suitable for MF ΜS The material of the structure can also be. As for the material of the ferroelectric layer 136, such as lead zirconate titanate (PZT) or hafnium bismuth titanate (SBT), etc., based on electrical considerations, the ferroelectric layer 1 used in the present invention 3 6 The material is lower than the ferroelectric material with a lower dielectric constant, such as s Β τ, etc. ί Please read the precautions on the back before filling ^ .4 to buy) Binder 7 This paper applies Chinese national standards (CNS) Α4 specification (210X 297 mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs ^ 6 5 0 9 5 A7 ___B7___ V. Description of the invention () In addition, the sealing layer 2 0 0 is made of a dielectric material to The gate stack layer 130 and the word line WL provide good isolation to prevent stored charge from being lost. The sealing layer 2 0 has good adhesion to the gate stack layer 1 3 0. The dielectric material used is, for example, titanium oxide (TiO :), hafnium oxide (ZrO :), or aluminum oxide (A12 Ο 3). Wait. As for the external electrode 2 0 2, a general conductive material is used, such as Shao (A 1) or copper (: Cu). Since the manufacturing process of this structure is mostly a technique familiar to those skilled in the art, it will only be described briefly, but it does not limit the manufacturing method of the structure of the present invention. Firstly, a gate dielectric layer 1 32, a lower electrode 1 34, a ferroelectric layer 1 36, and an upper electrode 1 38 are sequentially deposited on the substrate 100. Next, the pattern of the gate stack layer 130 is defined. Then, for example, source / drain electrodes 1 2 2 and 1 2 4 are formed on both sides of the gate stack layer 130 by an ion implantation method. Then, the exposed surface of the gate stack layer 130 is covered with a sealing layer 200. An external electrode 202 is then formed on the sealing layer 200 and above the ferroelectric layer 136. This completes the sealed ferroelectric memory cell of the present invention. Please refer to FIG. 4, which shows the charge distribution state of the ferroelectric memory cell of the present invention after charging. The invention uses the electric field generated by the external electrode 202 to polarize the ferroelectric layer 136, and simultaneously forms a separate charge distribution in the gate stack layer 130 to store data. The external electrode 2 0 2 is connected to the word line WL (refer to FIG. 1), and the voltage applied to the external electrode 2 0 2 is controlled by switching the switch of the control transistor 50. When we apply a positive voltage V through the external electrode 202 g to the gate stacking layer U 0 'ferroelectric layer 1 3 8 8 paper sizes applicable to China National Standard (CNS) A4 specifications (210 X 297 mm) --I --------- -*-! ^ · ---- Γ --- Order --------- '^ 一 I (Please read the notes on the back before filling out this page > Employee Consumer Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs Printed 465096 A7 _____B7___ V. Description of the invention () The dipole is affected by the electric field and the polarization is up. At the same time, the upper electrode 1 3 and the lower electrode 1 3 4 are also affected by the electric field to form a separate charge distribution, as shown in the figure. The net charge between the upper electrode 1 3 8 and the ferroelectric layer 1 3 6 is zero, and the net charge between the ferroelectric layer 1 3 6 and the lower electrode 1 3 4 is also zero. Only in the upper electrode 1 The negative charge at the top of 3 8 and the positive charge at the bottom of 1 3 4 are effective charges. The data is stored in the capacitor by this step. After the applied external voltage VG is removed, due to the ferroelectric material With its own characteristics, the polarization direction can be maintained after the external electric field is removed, so that the stored data can be preserved. Since the invention is coated with a sealing layer 2 0 on the outside of the gate stack layer 1 30, it is stored in The charge in the gate stack layer 130 is covered by the sealing layer 200, so there is no charge loss. In addition, the charge stored in the gate stack layer 130 is because of the ferroelectric layer 1. The polarization and separation of 36 and the positive and negative charges are very far apart, which is greater than 0.6 micrometers (/ Z m), so the problem of charge neutralization is not easy to occur. Please refer to FIG. 5, which shows the stacked capacitor gate of the present invention. The equivalent circuit diagram of the electrode is three capacitors connected in series1, which respectively represent the gate dielectric layer 132, the ferroelectric layer 136, and the sealing layer 200. The addition of a sealing layer 200 above the ferroelectric layer 136 will change the overall The equivalent capacitance value and its coupling ratio (c 〇up 1 ingrati 〇) are very important, so the capacitance value of the ferroelectric layer 136 must be small to increase the effective electric field acting on the ferroelectric layer 136. Therefore, ferroelectric Materials used for layers 1 3 6 A ferroelectric material with a low dielectric constant is better, such as SBT. This paper size is applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm) ft ^^ 1 —fc ^^ 1 -n ^ iF ί — Λ. R * t— ^^ 1 nn ^^ 1 I " 『< nn ^^ 1 I n I (Please read the precautions on the back before filling out this page) 4 6 5l A7 ____B7_ 5. Description of the invention () Then A method of operating the ferroelectric memory cell of the present invention will be described. Please refer to FIG. 6 and FIG. 7 at the same time. FIG. 6 shows a schematic diagram of an equivalent circuit of the ferroelectric memory cell of the present invention. The writing method is to apply the gate G or 'VDD' at this time when the substrate is grounded, then the data "1" or "0" can be written into the memory cell. The reading method can apply the voltage Vr to the gate G. The The value of V r is between the threshold voltage of “0” and Γ ′, and the sum of “1” is determined by the on and off of the transistor. In summary, the present invention discloses a sealed ferroelectric memory cell, which can make iron The charge data stored in the electric capacitor is sealed, and no leakage current occurs due to connection with an external circuit, which can extend the storage time of the data in the memory cell. The above is only a preferred embodiment of the present invention, and is not intended to Limit the scope of patent application of the present invention, all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be included in the scope of patent application below. Ί 1 ^ 1 rjt t / ψ \ 1 ^ 1 I-I— II ni ^ 1 · T— ·· > 1 n 1 ^ 1 nn I / ia j (Please read the notes on the back before filling out this page) This paper size applies to the national standard (CNS) A4 size mo X 29 7 male.¾)