TW465078B - Manufacturing method of inductor formation using redistribution process of flip-chip - Google Patents

Abstract

This invention provides manufacturing method of inductor formation using redistribution process of flip-chip. The inductor is formed at the same time when metal bumps are formed using thick film process. The two terminal points of the inductor are formed together with the solder pads and the inductor is covered by resin layer with low dielectric constant.

Description

46 50 7 L

V. Description of the invention (1) [Field of invention] In particular, it relates to the method. The present invention relates to a method for manufacturing an inductor. A conventional technique for forming an inductor in a flip-chip redistribution process is a conventional technique. Inductors are generally constructed by winding a spiral wire. Radio frequency (radl0 frequency; RF) circuits are widely used in applications such as mobile phones, wireless circuits, wireless modems, and other communication equipment. With the advancement of integrated circuit technology, inductors can be manufactured using integrated circuit technology, and inductors and other 7L components can be integrated on a single crystal cube to reduce the cost of manufacturing circuits. At present, electrical convolute metal layers integrated in integrated circuit manufacturing processes are common. However, the inductor integrated in the integrated circuit manufacturing process ^ has some problems. These problems will be explained in conjunction with Figure 1 below. As shown in the cross-sectional view of FIG. 1, the convoluted metal layer 16 ", which is conventionally used as an inductor, is manufactured together with the pad 16 ', and the two ends of the convoluted metal layer 16 " are connected respectively To the metal layer 12d below it, in this figure, in addition to the swirling metal layer 16 "and the pad 16", the metal layer 12a, 12b, 12c and 12d are also included, and Electrical isolation is performed by using a SiO 2 layer 14. Among them, in the substrate 10 corresponding to the convoluted metal layer 16 ", a shallow trench isolation region (Shai i0wt French i so 1 at i on; ST I) 1 1 'must be formed to reduce the convoluted metal layer 16 " Effect on the substrate 10. Therefore, the convoluted metal layer 16 "will occupy the

465078 V. Description of the invention (2) For the front-face multi-facet 'If the layout area of the spiral metal layer 16 is reduced in order to save the area of the substrate 10, the requirement for the inductance value cannot be met. In addition, "Since the spiral metal layer 16" and the shallow trench isolation area 丨 丨 are electrically isolated by a silicon oxide layer 14 and the adjacent metal wires of the spiral metal layer 16 "themselves are also oxidized. The silicon layer is electrically isolated. However, the oxidized stone has a relatively high dielectric constant, which is about 3.9 to 4.5. Therefore, parasitics may occur between the substrate ι0 and the swirling metal layer 16 11 Capacitance 'and the swirling metal layer 16 " itself will also generate parasitic capacitance between adjacent metal wires, which reduces the self-resonant frequency of the swirling metal layer 16 ", which is an inductor, thus limiting the It is a spiral metal layer of an inductor 16 " for high frequency applications. Furthermore, the swirling metal layer 16 "is easily coupled to the substrate 10, and an eddy current is generated in the substrate 10; in addition, between the substrate 10 and the swirling metal layer 1 6 " and the swirling metal layer 1 6 "The parasitic capacitance itself will cause energy loss, so the quality factor (Q value for short) is too low. [Objective of the Invention] In view of this, an object of the present invention is to provide a method for manufacturing an inductor, which can reduce the capacitive effect between the inductor and the substrate, and reduce the capacitive effect of the inductor itself. Furthermore, the object of the present invention is to provide a method that can increase the distance between the inductor and the substrate, so as to reduce the generation of the mirror current in the substrate. In addition, an object of the present invention is to provide a method that can increase the layout area of an inductor without increasing or even reducing the area of a chip.

Page 5 465078 V. Description of Invention (3). In addition, the present invention also provides a method for increasing the threshold value of an inductor without increasing or even reducing the area of a chip. Therefore, the present invention provides a method for manufacturing an inductor, comprising: forming first, second, and third pads on a substrate; the first pads are used for making electrical connection with the outside world; A dielectric layer and a first resin layer with a low dielectric constant are sequentially formed on the third pad, and then the dielectric layer and the first resin layer with a low dielectric strength are patterned to form the first and the first therein. The second and second openings respectively expose the first, second, and third pads and then perform a thick film process to form a thick metal layer on the first resin layer having a low dielectric constant, and then patterning it to ' A bump and an inductor are formed, wherein the bump is connected to the first pad, and the two ends of the inductor are connected to the second and third pads, respectively. Then, a second layer with a low dielectric constant is covered on the bump and the inductor. Resin layer. According to a preferred embodiment of the present invention, the material of the first resin layer and the second tree layer is, for example, polyimide, and the thickness of the first resin layer is about 10 micrometers to about 30 micrometers. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below, and in conjunction with the accompanying drawings, the detailed description is as follows: [Schematic description of the drawings] FIG. 1 is a drawing This is a cross-sectional view of a structure that traditionally integrates inductors in integrated circuits.

Page 6 465078 8 Years of Redemption 6 卩 岱 -ΓΓ. ’H Case No. 89116836 Amendment 5 Explanation of the Invention (4)

Figures 2A to 2D are cross-sectional views illustrating a manufacturing process for forming an inductor using a flip-chip redistribution process according to the preferred embodiment of the present invention. FIG. 3 is a top view of FIG. 2C, where FIG. 2C is a cross-sectional view taken along line I-Γ of FIG. [Symbol description] Shallow trench isolation area: 11 Silicon oxide layer: 1 4 Substrate: 10, 100 f I | | Metal layer: 10 2a, 102b, 102c, 102d, 116 Dielectric layer: 104, 108 , 110 Pads: 106a, 106b, 106c Resin layers: 11 2, 11 8 Openings: 11 4 a, 11 4 b Bumps: 16 ', 116a, inductor (convolution-shaped metal layer [Example] The Q value of the inductor has The relationship between Qe 0L / R, where ω is the resonance cheek rate, and L · is the inductance value of the resistance of the inductor itself. The present invention uses a flip-chip redistribution process to form a metal bump together. The formation of the inductor 'improves the resonance frequency ω, the inductance value L, and the resistance R of the inductor 114c, 16b, and 16b, thereby increasing the Q value of the inductance. Figures 2A to 2D show a preferred embodiment according to the present invention. A cross-sectional view of the manufacturing process of the inductor according to the embodiment. First, please refer to FIG. 2A to provide a substrate, such as a semiconductor chip substrate, and a component (not shown) and an interconnect have been formed.

im 0503 巧 139TWfl.ptc page 7 465078 V. Description of the invention (5) The interconnect includes a first metal layer 102a, a second metal layer 102b, a third metal layer 102c, and a fourth metal layer i As shown in FIG. 2D, a dielectric layer 104 is used for electrical isolation. Thereafter, pads 6a, 6b, and 106c 'are formed on the dielectric layer 〇4 as the uppermost structure of the interconnect. The pad 〇0a is used to make electrical connections with the outside world, and The pads 106b and 06c are used to connect two ends of an inductor to be formed later. Then, the pads 106a, 106b, and 106c are sequentially covered with the dielectric layer 108, the dielectric layer 110, and the resin layer with a low dielectric constant, as a protective layer, and the dielectric layer 10 is The material of 8 is, for example, silicon oxide, the material of the dielectric layer 11 is, for example, silicon nitride, and the material of the resin layer 11 2 is, for example, polyimide, and the thickness of the resin layer 1 12 is about 10 to 30 microns. . Subsequently, the resin layer 112, the dielectric layer 110, and the dielectric layer 108 are patterned, and openings i14a, U4b, and 114c are formed therein to expose the pads 106a, 106b, and 106c, respectively. Next, referring to FIG. 2B, a thick film process is performed to form a metal layer 116 on the resin layer 1 12. The material is, for example, is copper alloy, and is filled in the openings 114a, 114b, and 114c. 106a, 106b and 106c make electrical contact. The thick film process is, for example, applied by screen printing, and the thickness of the formed metal layer 116 is about 2 μm to 4 μm. Next, please refer to Figure 2C and its top view, Figure 3, where the I-Γ section in Figure 3 is Figure 2C. The metal layer 116 is patterned to form the bump 116a and the inductor 116b ′ at the same time. The inductor U6b is, for example, a convoluted metal structure, where the bump 116a is connected to the solder pad 106a, and the end of the inductor H6b is connected to the solder pad 10 6b connection, the other end is connected to the pad 106c. Since this electricity

46 50 7 8 V. Description of the invention (6) The thickness of the 11 6b is about 2 micrometers to 4 micrometers. Therefore, the wearing area of this convoluted metal structure is larger than conventional, so the resistance of the inductor 116b itself can be reduced. 'The Q value of the inductor 116b can be increased. In addition, the traditional inductor must be fabricated over the shallow trench isolation region to avoid the inductor from generating a mirror current in the substrate. The inductor H 6b of the present invention is formed together with the bump 116a, and the distance from the substrate 10 () has been increased from 6 micrometers to about 20 micrometers to about 30 micrometers, so that the inductor U6b can be avoided from the base, 1 ο 〇A mirror current is generated within the inductor. Therefore, the inductor 6b of the present invention does not need to be placed above the shallow trench isolation region, so the inductor can be prevented from occupying the use area of the substrate 100, which can reduce the crystal area. area. If the inductor 116b of the present invention is arranged above the shallow trench isolation region, the influence of the inductor 116b on the substrate 100 and other components can be more completely avoided ^ Furthermore, the inductor 116b is used to connect its internal endpoints The parasitic capacitance between the conductive wires (ie, the bonding pads 106b) is also reduced by filling the resin layer 112 with a low dielectric constant and increasing the distance, so the resonance frequency of the inductor U6b can be increased. Next, referring to FIG. 2D, a resin layer 118 'having a low dielectric constant is formed on the bump 116a and the inductor 116b, and the material of the resin layer 118 is, for example, polyurethane. Therefore, the adjacent metal lines used as the spiral metal structure of the inductor 11 6b are filled with a resin layer 11 8 having a low dielectric constant, so that the parasitic capacitance (or serial capacitance Ls) of the inductor 11 6b itself can be reduced. Therefore, the resonance frequency of the inductor 116b can be increased, thereby further increasing its q value. In addition, since the inductor 116b of the present invention is relatively free from spatial restrictions, the number of turns of the spiral-shaped metal structure used as the inductor 116b can be increased. and

Page 9 465078 V. Description of the invention (Ό Also, the interval between adjacent metal lines of the swirling metal structure can be increased. This interval is about 10 microns to 40 microns to further reduce the inductance. 6b itself Parasitic capacitance, in addition, can also improve the yield of the process. Then the subsequent packaging process, but this is not relevant to the present invention, not to repeat it here. [Invention features and effects] In summary, the present invention provides at least the following advantages Points: 1. The distance between the inductor of the present invention and the substrate has been increased to about 20 micrometers to 30 micrometers', which is about 3 to 5 times that of the conventional inductor, so the influence of the inductor on the bottom and other components can be reduced. Inventor of the invention Invented metal adjacent to the present invention The present invention provides a low electric capacity as a series of electrical constants; in order to improve the nature of the increase 3. the phase of the metal structure 4. lower, 5. with low dielectric capacity (Even if the delay is large, the layout width can be reduced by ^ / -5¾ TW TO WF 10,000, and the area of the crystal cube can also be reduced. The inductance of the inductor is not limited by space, and the number of convolutions can be increased to increase Electricity Value; _ can increase the spacing between the convoluted metal junctions to improve the yield of the process. The thickness of the inductor is thicker, so the Q value of the Lexham inductor. Therefore, the resistance of the inductor itself can sense the phase of the convoluted metal structure. Adjacent metal lines are filled with resin, so the inductor itself has a lower parasitic electrical coupling s, and the inductor and the wires used to connect its two ends are also filled with a resin with a low dielectric constant and the distance is added. The parasitic capacitance between the inductor and the substrate is also reduced. The resonant frequency of the inductor further increases its Q value. Yiming has disclosed the above with a preferred embodiment, but it is not intended to

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4 6 5 C 7 B V. Explanation of the invention (8) The invention is limited. Any person skilled in the art can make changes and retouches without departing from the spirit and scope of the invention. Therefore, the scope of the invention should be considered after the fact. The attached application patent shall prevail.

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Claims (1)

465078 VI. Patent scope 1. A manufacturing method for forming an inductor using a flip-chip redistribution process, which is applicable to a substrate on which a component and a first dielectric layer have been formed. The manufacturing method includes the following steps: A first pad, a second pad, and a third pad are formed on the substrate. The first pad is used to make electrical connection with the outside; on the first, second, and third pads Forming a second dielectric layer, forming a first resin layer with a low dielectric constant on the second dielectric layer, patterning the second dielectric layer and the first resin layer with a low dielectric constant, Forming a first opening, a second opening and a third opening respectively exposing the first solder pad, the first solder pad and the third solder pad; and performing a thick film process so that A metal layer is formed on the first resin layer having an electric constant; the metal layer is patterned to form a bump and an inductor, wherein the bump is connected to the first pad One end connected to the inductor is connected to the second solder pad, and the other end is connected to the first-more than pad; and a second resin layer with a low dielectric constant is formed on the bump and the inductor. The method for manufacturing an inductor according to item 1 of the scope of the patent application, wherein the second dielectric layer includes an oxide layer and a nitrogen-fossil layer. 3. The manufacturing of the inductor as described in item 1 of the scope of patent application: η k, wherein the first resin layer having a low dielectric constant includes a polyimide layer with a thickness of 10 μm to 30 μm. . Manufacturing of inductors as described in item 1 of the patent application Page 12 465078 6. The second resin layer with low dielectric constant in the scope of patent application includes a polyimide layer. 5. The method for manufacturing an inductor according to item 1 of the scope of the patent application, wherein the metal layer includes a charm copper alloy layer. 6. The method for manufacturing an inductor according to item 1 of the scope of patent application, wherein the thickness of the metal layer is between 2 microns and 4 microns. 7. The method for manufacturing an inductor as described in item 1 of the scope of patent application, wherein the inductor includes a swirling metal structure. 8. The method for manufacturing an inductor according to item 7 of the scope of the patent application, wherein the distance between adjacent metal lines of the swirling metal structure is 10 micrometers to 40 micrometers. Page 13