465020 五、發明說明（1) 本發明疋有關於一種半導體（semiconductor)積體電 路（integrated circuits ; iCs)製程技術，特別是一種有 關具有圓化頂部肖落（rounded top corner)的淺溝槽隔離 物（shall ow trench isolation ;STI)的製造方法。 在半導體基底的特定區域形成淺溝槽（shal 1〇w t r e n c h)，接著填入絕緣材料（丨n s u 1 a t 〇 r )於此淺溝槽以形 成的淺溝槽隔離物技術’已廣泛地被使用於半導體積體電 路的4段製程。並且，此淺溝槽隔離物已成功地用來隔絕 半導體元件。通常上述淺溝槽是利用非等向性蝕刻法 (anisotropic etching)，例如反應性離子蝕刻法 (reactive i〇n etching ;RIE)去除部分半導體基底而得 到’通常利用非等向性蝕刻法形成的淺溝槽頂部角落（t〇p corner)之輪廓相當陡峭（非平滑），因此容易造成應力點 (stress point)以及元件的漏電現象（ieakage)。 有鑑於此，本發明提供一種淺溝槽隔離物的製造方 法’能夠有效地形成具有圓化頂部角落的淺溝槽隔離物， 以避免上述漏電現象，進而提昇半導體元件性能。 根據上述目的，本發明提供一種淺溝槽隔離物的製造 方法’包括下列步驟：（a)提供一半導體基底，該基底在 主動區域形成有一罩幕圖案；（b)利用該罩幕圖案為遮蔽 物’並且餘刻該半導體基底，以形成一溝槽；（c)去除該 罩幕圖案的外周圍，以露出該溝槽的頂部角落；（d)利用 物J里性減:擊方式處理該溝槽的頂部角落，以形成具有圓化 頂部角落的溝槽；以及（e )在上述具有圓化頂部角落的溝465020 V. Description of the invention (1) The present invention relates to a semiconductor integrated circuit (ICs) process technology, and particularly to a shallow trench isolation with a rounded top corner (Shall ow trench isolation; STI) manufacturing method. The formation of shallow trenches (shal 10wtrench) in specific areas of semiconductor substrates, followed by the filling of insulating materials (丨 nsu 1 at 〇r) in this shallow trench to form shallow trench isolation technology has been widely used 4-step process for semiconductor integrated circuits. Moreover, this shallow trench spacer has been successfully used to isolate semiconductor devices. Generally, the above shallow trenches are formed using anisotropic etching, such as reactive ion etching (reactive ion etching; RIE) to remove a part of the semiconductor substrate, and are usually formed using anisotropic etching. The contour of the top corner of the shallow trench is quite steep (non-smooth), so it is easy to cause stress points and leakage of components. In view of this, the present invention provides a method for manufacturing a shallow trench spacer, which can effectively form a shallow trench spacer with rounded top corners to avoid the above-mentioned leakage phenomenon, thereby improving the performance of semiconductor devices. According to the above object, the present invention provides a method for manufacturing a shallow trench spacer, including the following steps: (a) providing a semiconductor substrate, the substrate is formed with a mask pattern in an active area; (b) using the mask pattern as a mask And the semiconductor substrate is etched to form a trench; (c) removing the outer periphery of the mask pattern to expose the top corners of the trench; (d) using the material J to reduce the nature of the impact: the process A top corner of the groove to form a groove with a rounded top corner; and (e) a groove with a rounded top corner as described above
465020 五、發明說明（2) 槽内填入絕緣材料以形成-淺溝槽隔離物。 再者’上述淺溝槽隔離物的製造方法之中，該罩幕圖 案可以由下層具有墊氧化物的氮化矽材料構成。 ，者’上述淺溝槽隔離物的製造方法之中，步驟（c ) 去除該罩幕圖案可以利用溼式蝕刻法（例如磷酸溶液）完 成0 並且’上述淺溝槽隔離物的製造方法之中，步驟（c) 去除該罩幕圖案可以利用乾式蝕刻法完成。 再者上述淺溝槽隔離物的製造方法之中，步驟（d) 之物理濺擊可以是氩氣濺擊。 再者’淺ϊ冓槽隔離物的製造方法之中，步驟（c)去除 罩幕圖案的外周圍範圍大約介於5〇〜25〇埃。 /並且，上述淺溝槽隔離物的製造方法之中，步驟（d) 之後可以更包括利用一氫氟酸清洗步冑，以去除物理性濺 擊方式殘留的雜質。 再者，上述淺溝隔離物的製造方法之中，步驟（e)之 前可以更包括利用熱處理㈣，以在該具有g化頂部角落 的溝槽的表面形成一襯塾氧化層。 平坦化上述二氧化矽材料， 並且，上述淺溝槽隔離物的製造方法之中’填入該絕 緣材料的方式係包括下列步驟：（i)利用高密度電聚化學 氣相沈積法以形成一虱化矽材料；（Η)以化學機械研磨法 以形成一淺溝槽隔離物 465020 五、發明說明（3) ---___ 明如下： 圖式之簡單說明： 第1圖係根據本發明實圹 步驟剖面圖。 、匕例形成淺溝槽隔離物之起始 第2圖係第1圖之後續步 圖。 k u物理性濺鍍）的剖面 第3圖係第2圖之後續步驟（氫. 第4圖係第3圖之後續步虱軋酸溶液）的剖面圖。 第5圖係第4圖之後J牛驄（絕緣材料填入）的剖面圖。 幕圖案）的剖面圖。 1 V (化學機械研磨以及去除罩 符號之說明 1 1 0〜塾氧化層。 HM、HM’〜罩幕圖案。 100〜半導體基底。 120、120a~氮化矽材料。 1 3 0〜淺溝槽。 T C〜淺溝槽之頂部角落。 1 6 0〜絕緣材料層。 AA〜主動區域。 TC〜淺溝槽之圓化頂部角落 150〜襯墊氧化層。 160a〜淺溝槽隔離物。 實施例 以下利用第1圖〜第5圖所示之淺溝槽隔離物的製程剖 面圖來說明本發明之實施例。 首先’請參照第1圖’此圖顯示形成有罩幕圖案HM的 半導體基底100，上述罩幕圖案⑽係由墊氧化層110以及氮 化石夕材料120構成’並且形成於主動區域（active465020 V. Description of the invention (2) The trench is filled with insulating material to form a shallow trench spacer. Furthermore, in the above-mentioned method for manufacturing a shallow trench spacer, the mask pattern may be made of a silicon nitride material having a pad oxide in a lower layer. In the above method of manufacturing the shallow trench spacer, step (c) removing the mask pattern may be completed by a wet etching method (such as a phosphoric acid solution), and in the above method of manufacturing the shallow trench spacer. In step (c), the mask pattern can be removed by a dry etching method. Furthermore, in the method for manufacturing a shallow trench spacer, the physical sputtering in step (d) may be an argon sputtering. Furthermore, in the method for manufacturing a shallow trench spacer, the outer periphery of the mask pattern removed in step (c) is approximately 50 to 25 angstroms. / Moreover, in the method for manufacturing a shallow trench spacer, after step (d), it may further include cleaning the step with a hydrofluoric acid to remove impurities remaining by a physical sputtering method. Furthermore, in the method for manufacturing a shallow trench spacer, before step (e), it may further include using a heat treatment to form a lining oxide layer on the surface of the trench having the top corner. The silicon dioxide material is planarized, and the method of 'filling the insulating material in the above-mentioned method of manufacturing the shallow trench spacers includes the following steps: (i) using a high-density electrochemical polymer chemical vapor deposition method to form Lice silicon material; (Η) Chemical mechanical polishing method to form a shallow trench spacer 465020 V. Description of the invention (3) ---___ The description is as follows: A brief description of the figure: Figure 1 is based on the invention圹 Step sectional view. The beginning of the formation of shallow trench spacers Figure 2 is a subsequent step to Figure 1. Section of k u physical sputtering) Figure 3 is a cross-sectional view of the subsequent step of Figure 2 (hydrogen. Figure 4 is a cross-sectional view of the lice rolling solution of Figure 3). Figure 5 is a sectional view of J Niuyu (filled with insulating material) after Figure 4. Curtain pattern). 1 V (Description of chemical mechanical polishing and removal of the mask symbol 1 1 0 to 塾 oxide layer. HM, HM 'to mask pattern. 100 to semiconductor substrate. 120, 120 a to silicon nitride material. 1 3 0 to shallow trench TC ~ Top corner of shallow trench. 160 ~ Insulation material layer. AA ~ Active area. TC ~ Rounded top corner of shallow trench 150 ~ pad oxide layer. 160a ~ Shallow trench spacer. Example Hereinafter, an embodiment of the present invention will be described using the manufacturing process cross-sectional views of the shallow trench spacers shown in FIGS. 1 to 5. First, 'please refer to FIG. 1' This figure shows a semiconductor substrate 100 having a mask pattern HM formed thereon. The mask pattern is composed of a pad oxide layer 110 and a nitride nitride material 120 and is formed in an active area.
第6頁 465020 五、發明說明¢4) area)AA。然後，利用此罩幕圖案HM當作遮蔽物，然後以 活性離子蝕刻法蝕刻未被上述罩幕圖案HM遮蓋的半導體基 底 100，以形成一淺溝槽（shallow trench)130。 然後’請參照第2圖，此圖為第1圖之後續步驟剖面 圖’利用例如磷酸溶液（H3 P 0 4)溼蝕刻方式去除上述罩幕 圖案HM的外周圍大約50〜250埃，以露出上述淺溝槽130頂 部角落（top corner )TC。接著，利用物理性濺擊方式，例 如氬氣濺鍍（Ar sputtering)處理上述頂部角落TC的尖角 使其鈍化。當然’亦可利用各種乾式蝕刻法取代上述磷酸 溶液’以去除部分的罩幕圖案HM外周圍。 其次，請參照第3圖’此圖為第2圖之後續步驟剖面 圖’利用含有氫氟酸（HF)的緩衝氧化蝕刻液（buffered oxide etchant ; B0E)，以去除因氬氣濺鍍所產生的雜 質’而得到具有圓化頂部角落TC’的淺溝槽130(如第3圖所 示）。 接著，請參照第4圖，此圖為第3圖之後續步驟剖面 圖，形成具有圓化頂部角落TC’的淺溝槽130之後，在大約 iooo°c的溫度下進行氧化反應’以形成襯墊氧化層（liner 1 ayer ) 1 5 0 ’來修補因溝槽蝕刻造成的表面損傷。然後， 利用高密度電漿化學氣相沈積法（high density plasma chemical vapor deposition ;HDP-CVD)以在上述淺溝槽 1 3 0形成二氧化矽材料構成的絕緣層丨6 〇。緊接著，利用化 學機械研磨法（chemical mechanical polishing ;CMP)平 坦化上述絕緣層1 6 0，以形成本發明的淺溝槽隔離物Page 6 465020 V. Description of the invention ¢ 4) area) AA. Then, the mask pattern HM is used as a shield, and then the semiconductor substrate 100 not covered by the mask pattern HM is etched by an active ion etching method to form a shallow trench 130. Then "Please refer to Figure 2, which is a cross-sectional view of the subsequent steps of Figure 1." Using a phosphoric acid solution (H3 P 0 4) wet etching to remove the outer periphery of the mask pattern HM by about 50 to 250 Angstroms to expose The top corner TC of the shallow trench 130 mentioned above. Next, the sharp corners of the top corners TC are treated with a physical sputtering method, such as Ar sputtering, to passivate them. Of course, 'a variety of dry etching methods may be used in place of the phosphoric acid solution' to remove part of the outer periphery of the mask pattern HM. Next, please refer to Figure 3, 'This figure is a cross-sectional view of the subsequent steps of Figure 2.' Using buffered oxide etchant (B0E) containing hydrofluoric acid (HF) to remove the argon sputter The impurity 'is used to obtain a shallow trench 130 having a rounded top corner TC' (as shown in FIG. 3). Next, please refer to FIG. 4, which is a cross-sectional view of the subsequent steps of FIG. 3. After forming a shallow trench 130 having a rounded top corner TC ', an oxidation reaction is performed at a temperature of about 100 ° C to form a liner. A pad oxide layer (liner 1 ayer) 1 50 'is used to repair the surface damage caused by trench etching. Then, a high-density plasma chemical vapor deposition (HDP-CVD) method is used to form an insulating layer made of a silicon dioxide material in the shallow trench 130 described above. Next, the above-mentioned insulating layer 160 is flattened by chemical mechanical polishing (CMP) to form the shallow trench spacer of the present invention.
第7頁 4 6 5〇2〇Page 7 4 6 5〇2〇
法，能夠成功地形成具有圓化頂 以避免上述漏電現象，進而提昇 A 根據本發明的製造方 4角落的淺溝槽隔離物， 半導體元件性能。 雖然本發明已以較祛给 KB A知例揭露如上，然其並非用以 「R弋本發明，任何熟習土卜$ 俅〗^此項技藝者，在不脫離本發明之精 和範圍内，當可作更動與潤飾，因此本發明之保護範圍 當視後附之申請專利範圍所界定者為準。Method, can successfully form a rounded top to avoid the above-mentioned leakage phenomenon, and further improve the performance of the semiconductor device in the shallow trench spacers at the four corners of the manufacturer according to the present invention. Although the present invention has been disclosed as above to KB A, it is not used to "R 弋 the present invention, any person familiar with local soil $ 俅〗 ^ This artisan does not depart from the spirit and scope of the present invention When changes and retouching can be made, the scope of protection of the present invention shall be determined by the scope of the attached patent application.