TW463267B - P-type metal oxide semiconductor manufacture process - Google Patents

Abstract

This invention provides the P-type metal oxide semiconductor manufacture process by preventing boron penetration. Firstly, gate oxide layer and gate electrode layer are formed on a given semiconductor substrate. A resist layer is formed on top of the gate electrode layer and pattern is transferred onto the resist layer through exposure. The resist layer is used as mask to etch gate electrode layer and gate oxide layer. The resist layer is then stripped off. Rapid oxidation and nitridation processes are employed to grow thin oxynitride layer and highly doped drain of boron ion shallow junction is formed by ion implantation. TEOS oxide and silicon nitride are formed by using low pressure chemical vapor deposition and spacer is formed by etching TEOS oxide and silicon nitride. Highly doping process and annealing treatment of boron ions are carried out and part of the redundant thin oxynitride (NO, N2O) layer is removed. Finally, metal silicide process is performed.

Description

46326 7 V. Description of the invention (1) 5 -1 Field of the invention: The present invention relates to a method for generating pM0s used in the process of manufacturing semiconductor devices, and in particular to a method for preventing boron infiltration to generate PM0s. 5 -2 Background of the Invention: When the density of integrated circuits is continuously expanding, in order to keep the chip area the same, or even to reduce the unit cost of the circuit, the only way is to continuously reduce the circuit design specifications ( design rule). And when the size of the component is reduced, the junction surface in the source / drain must be shallower to avoid short-channel effects. Therefore, when we do ion implantation of highly doped drain electrodes at the PMOSi junction, we must use low-energy, high-dose boron ions (boron or boron fluoride). However, during the tempering process, the crystal structure on the surface of the Shi Xi wafer is restored, and at the same time, the side ions implanted in the source and the electrode undergo thermal diffusion in the silicon wafer, thereby reducing the concentration of boron ions near the surface, causing the source The increase of the non-polar resistance value and the decline of the driving current (ID, SAT) reduce the efficiency of the semiconductor device. 5-3 Invention Purpose and Overview:

Page 4 463267 V. Description of the invention (2) In the above background of the invention, there are many shortcomings of the traditional method of generating PMOS. The present invention provides a process to solve the problem of traditional generation of PMOS. "An object of the present invention is to Provided is a method for generating pMos, which can prevent boron infiltration. Since the present invention uses a fast, chemical, and nitridation process to grow a thin oxide gas layer in the process of generating pMos, the thin nitrogen oxide layer can be used to lice (NO) or dinitrogen oxide (%.), #Thus the thin nitrogen oxide (n0, ~ 〇) ', which can effectively prevent boron ions in the source / drain electrode during the tempering process: diffusion and decrease Its concentration near the surface 'achieves the purpose of maintaining the concentration of boron ions near the surface. The purpose of this month is to provide a kind of semiconductor device that produces ps: high-performance semiconductor devices, because in the subsequent tempering system ^ 1 The implanted shed ions reduce their concentrated production near the surface due to thermal diffusion, = the increase in resistance in the source / pole electrode and the driving current% of the gas ions, M) the formation of rotten ions can maintain rotten ions 乂Surface concentration, resulting in low resistance of the source / drain and High drive

), Thereby improving the efficiency of the semiconductor device. Motor, VSAT

In the future, the present invention provides a method for preventing PMOS from being generated by the deletion process. First, a semiconductor bottom; y · 廿 —L = chemical layer and interrogation layer. Then, the pattern of the photoresist layer is transferred to the photoresist layer on the working surface of the interlayer layer, and the photoresist layer is used as a mask.

Article 5 463267 V. Description of the invention (3) Gate layer and gate oxide layer, and perform photoresist removal process. Next, a rapid oxidation and nitridation process is used to grow a thin nitrogen oxide layer. Secondly, a highly doped drain (HDD) of the side ion shallow junction is performed by the ion implantation method. TEOS and silicon nitride were deposited by low migration chemical vapor deposition, and TE0s and nitride were etched to form the partition wall. Next, the boron ions are heavily doped and tempered, and the unnecessary thin nitrogen oxide (N0, 乂 0) layer is partially removed. Finally, the metal oxide process is performed. Figure 5-4 is a brief description: The first diagram is a flowchart of an embodiment of the present invention; the first diagram A to the second I show a section of each step in the method of preventing rotten parameters to generate a PMOS according to the embodiment of the present invention. Schematic diagram; Representative symbols of main parts: 10 semiconductor substrate 1 1 gated layer 12 gated layer 14 oxidized gas layer 16 highly doped drain 1 6 A source 1 6 B pole 18 TE〇s

4 6326 7 V. Description of the invention (4) 2 0 2 1 2 2 2 4 2 6 2 8 Nitride layer gap wall gate gate stone Cobalt source Cobalt silicide Drain Cobalt silicide-5 The method is provided in step 2 and then after the step, the pattern is transferred and the closed oxide layer is rapidly oxidized, and the heavily doped process using low-voltage TEOS and nitride is implanted by ion implantation. At first will be below first

A diagram showing the present semiconductor 3, moving to light, and performing a nitriding process to learn the formation and tempering of fumed silicon. FIG. 2A shows a solid substrate according to the present invention and a photoresist layer resist layer to go up to the optical path. Boron ion deposition creates gaps. The last mentioned figure to the flowchart provided in the description of the main steps of generating a preventive embodiment are to form a gate oxide layer on the gate layer and a gate layer, and then use the photoresist layer as a mask to etch the resist. Next, a thin nitrogen oxide layer is formed in steps. Secondly, the shallow junctions are highly doped and non-polar. Knife / child product TE0S and gas fossils Yubi. Next, in step γ, step 8 and step 8 are performed in the metal manufacturing process. The two I diagrams of the different steps are mentioned and explained. Stop boron infiltration. First, the gate layer. After exposure, the electrode is used in step 4. In step 5 and step 6, the etching is performed under the appropriate conditions for the boron ionite semiconductor substrate 1 〇, which uses N-type silicon.

Page 7 46326 7 V. Description of the invention (5) The substrate 'sent into the oxidation furnace tube' uses a dry oxidation method to oxidize the silicon dioxide on the surface to a thickness of about 100 to 2 50 angstroms. The silicon oxide layer will serve as a gate oxide layer 11 of the semiconductor device. Immediately afterwards, polycrystalline stones with a thickness of about 2000 to 300 angstroms were deposited on silicon dioxide by LPCVD 'low pressure chemicaJ [vap〇rd epos iti on'. It is controlled at about 600 to 650 degrees Celsius and the pressure is about 0 to 6 torr (t or r). By thermal diffusion or ion implantation, a high concentration of boron, phosphorus, or arsenic is doped into the newly deposited polycrystalline silicon to reduce the gate resistivity and reduce the "RC time delay of the gate conductive layer ( RC time de 1 ay) ". It must be mentioned briefly here that the semiconductor substrate i 0 is a structure with elements formed therein, and these are not important to the present invention, and the present invention cannot be understood because the details are not described in detail. Then, a photoresist layer is deposited on the polycrystalline stone, and a stepper is used for local exposure, so that the pattern on the photomask is completely transferred to the photoresist, and then the photoresist is performed. Resistance to define the gate size. Photoresist is used as an etching mask, and polycrystalline silicon is etched by an auto-aligned reactive ion etching method (se 1 f -a 1 i gn RIE) to form a gate 12 structure, and an unnecessary gate oxide layer is removed. Finally, the photoresist is removed in a dry or wet etching manner, as shown in FIG. 2A. Figure B shows the use of rapid oxidation (rap i d therma 1 oxidation (RTO) and rapid thermal nitridation)

4632 ^ 7 V. Description of the invention (6) Nitrogen (NO, N20) enhances the subsequent restructuring of boron infiltration, but also 'makes the boron ion current (formable, can be in the ion) to TE0S stepless to reduce the resistance Value and elevation grow a thin oxide layer 14 on the semiconductor substrate 10 and the gate electrode 22, and the thickness of the nitrogen oxide layer is about 20 to 30 angstroms for resistance of penetration penetration. This is because in the fire process, although the crystalline junction on the surface of the silicon wafer can be restored, the implanted boron ions will thermally expand in the silicon wafer. ^ Decreasing the concentration near the surface will cause an increase in resistance and drive U'sat. Decline. This effectively prevents the occurrence of boron penetrat layer and external diffusion (Oil tdiff us i on) during the green tempering process of the thin nitrogen oxide (NO, Ν20) layer, so that the source / ion maintains its The concentration near the surface causes the source / drain drive current (ID, SAT) to further improve the performance of the semiconductor device. Next, we use the gate 12 just established as a screen and boron as an ion source. The wafer is implanted with boron ions (boron or boron fluoride). The ion implantation energy used is about 0.5 to 8 ke V, and the implanted dopant wave length is about 1 015 ions / cm2. It is used as a high doped drain (HDD) 16 to prevent the occurrence of short channel effects. It is called PHDD implantation, and because of the low energy, the implanted ions are in the semiconductor. The depth of implantation in the substrate will be relatively shallow, so it is called a shallow junction. It is worth noting that the highly implanted drain ion implantation step of this shallow junction can also be placed in the deposition. Before the thin nitrogen oxide layer process, it will not be affected by the sequence To the present invention.

Page 9 463267 V. Description of the invention ¢ 7) The second D diagram shows that TEOS and silicon nitride are deposited on the wafer by low pressure chemical vapor deposition (LpcVD) respectively. The thickness of the TEOS layer is about 200 to 500 Angstroms. 'The silicon nitride layer has a thickness of about 20 to 2000 Angstroms. Next, in the second diagram E, the silicon nitride and TE0s are etched by using an anisotropic etching method to form a partition wall 2 1 on the side wall of the gate electrode 12. The second F image shows that the boron (boron or boron fluoride) is used as the ion source, and the wafer is subjected to south-concentration and deeper ion implantation to re-dop the source 16 A and the drain 16 B. (Heavy doping), with a concentration of about 10 ivcm2, referred to as P implantation, and then the heavily doped implanted wafers are sent into a krypton diffusion furnace at a temperature of about 900 to 1000 degrees Celsius. At a high temperature, diffusion of boron atoms is performed. At the same time, the silicon atomic structure on the surface of the wafer that has been damaged by ion implantation is annealed. Then, the unnecessary thin nitrogen oxide (NO, Nz0) layer is partially removed. The process from the second G chart to the I chart is called the refractory metal silicide process, and its main characteristics are: low resistance, resistivity, anti-electron migration (electrón migrati〇n), Melting point and so on. The main application is to form a polycide structure, which is effective for forming low-resistance ohmic contacts (polyhedral contact) between polycrystalline stones and metal conductors. 2 The delay time is reduced by 1 ^, which improves the speed of component execution. f is composed of metal sulphide, and the element is titanium, titanium, tungsten, cobalt, etc. Next, we will use cobalt as an example to describe the process and conditions of metal silicide.

463267 V. Description of the invention (8) The second G-graph shows that metal cobalt 2 2 having a thickness of about 200 to 1000 angstroms is deposited on the entire wafer surface by magnetron DC sputtering. Next, using the south temperature of about 600 to 800 degrees Celsius, at this time, part of the deposited hafnium film will react with the polycrystalline stone on the gate and the drain and the stone on the source to form the gate, respectively. Cobalt silicide 24, source cobalt silicide 26, and drain silicide 2 8 are shown in the second figure. Finally, the cobalt remaining after not participating in the reaction or after the reaction (but not necessarily remaining in the form of cobalt) is then removed in a wet manner, as shown in the second figure. The above description is only a preferred embodiment of the present invention, and is not used to determine the present invention = patent application S]; all other equivalent changes or modifications made without departing from the spirit r disclosed in the present invention should include Within the scope of the next patent. kappa please

Claims (1)

463267 辕 Methods include at least: 6. Scope of patent application 1. A method to prevent the penetration of boron? ] ^ 〇5 The method provides a semiconductor substrate; forming a gate oxide layer on a part of the semiconductor bottom bismuth y surface and forming a gate layer above the surface of the gate oxide layer. The surface of the layer above and on both sides; 丨The dielectric layer is used to prevent boron infiltration to form a first dielectric layer above the gate and the surface of the semiconductor substrate, the first transparent and external diffusion; dielectric = Γ dielectric " and ... dielectric layer An anisotropic etching method is used to sequentially etch the third dielectric layer and the second dielectric layer on the first side to form a -spacer wall, which is located on both sides of the gate layer to form a two-doped region. In the semiconductor substrate, it is located below the two sides of the gap wall to form a source / drain of the semiconductor element; and a tempering process is performed. ° Among the above-mentioned semiconductor substrates to 2. The method according to item 1 of the scope of the patent application contains less N-type semiconductor substrates. 3. The method according to item 1 of the scope of patent application, wherein the above-mentioned gate reed contains polycrystalline silicon ❶ "· 4. The method according to item 1 of the scope of patent application, wherein said first dielectric layer includes at least one of the following: an oxidizing gas (NO) or dinitrogen oxide (j ^ 〇). Page 12 463267 6. Scope of patent application 5. If the method of the fourth scope of the patent application, the first dielectric layer is formed by rapid oxidation and nitridation methods. 6. If the method of the fourth scope of the patent application, the thickness is about 20 Angstroms to 30 Angstroms. The first dielectric layer mentioned above 7. The method of item 1 in the patent scope, which includes one of the following: boron or boron fluoride. Among them, the above-mentioned doping and upgrading are at least 8. The method according to item 1 of the patent application scope includes at least TEOS. Wherein the above-mentioned second dielectric layer 9. The method according to the first item of the patent application scope includes at least silicon nitride, among which the above-mentioned third dielectric layer 10. A method for preventing the infiltration of boron to generate PMOS, the method includes at least providing a Semiconductor substrate; Guang Konger added on the surface of the substrate of Han / Bao and Sun Pingtai too; a gate layer was formed over the surface of the gate oxide layer; 'a first dielectric layer was formed on the gate layer; Above the table and the semiconductor bottom wire # and above the π group Erco surface on both sides, the first dielectric temporary penetration and external diffusion: s is used to prevent the side Page 13 4 6 326 7 VI. Scope of patent application ---- d. Identifying the second step> Highly doped drain poles in the semiconductor substrate are located below the sides of the gate layer. ; 、 Sequential formation of blades— 坌 _a A Jr dielectric layer and a third dielectric layer on the second dielectric layer S 2 on the surface of the dielectric layer, etc .: The third dielectric layer is sequentially etched by a sexual etching method. And the second edge, s, to form a gap wall, which is located on both sides of the gate layer to form a double doping in the semiconductor substrate, which is located below the sides of the gap wall and 5 Within the scope of the Heshang doped drain region, it is used as the source / drain of the Xifeng conductor element; MW performs the tempering process; removes the part of the first dielectric layer; and performs the metal silicide process. 11. The method of claim 10, wherein the semiconductor substrate includes at least an N-type semiconductor substrate. 12. The method according to item 10 of the patent application range, wherein the gate layer includes at least polycrystalline stone. 1 3 _ The method according to item 10 of the scope of patent application, wherein the first dielectric layer includes at least one of the following: nitrogen oxide (NO) or dinitrogen oxide (N2O). 14. The method according to item 13 of the scope of patent application, wherein the above-mentioned dielectric material Page 14 4 6326 7 VI. Patent Application Layer The layer is formed by rapid oxidation and nitridation methods. 15. The method according to item 13 of the patent application range, wherein the thickness of the first layer is about 20 angstroms to 30 angstroms. Low electricity quality 16. The method of item 10 in the scope of patent application, wherein the above-mentioned high dopant contains at least the following sheds or II. Heterogenous dopants 17. The method of item 10 in the scope of patent application, wherein the above-mentioned highly doped ion-exchange human implantation energy is about G.5iWeVe 1 8. The method of item 10 in the scope of patent application, wherein the second introduction The dielectric layer contains at least TEOS. [9] The method of claim 10, wherein the third dielectric layer includes at least nitride. 20. The method according to item 10 of the scope of patent application, wherein the above-mentioned metal silicide includes at least one of the following: Qin, molybdenum, button, crane, knot. 21. —A method of preventing PM from infiltrating boron, the method includes at least: providing a semiconductor substrate; forming a gate oxide layer over a portion of the surface of the semiconductor substrate; [Page 5] 463267 6. The scope of the patent application forms an interrogation layer above the surface of the hafnium oxide layer; a highly doped drain electrode forming two shallow junctions is located below the semiconductor substrate on both sides of the gate layer 'It forms a first dielectric layer on the surface of the gate layer and above the surface of the semiconductor substrate'. The first dielectric layer: lateral penetration and external diffusion; QM prevents boron infiltration. A second dielectric layer and a third dielectric 4 # dielectric layer are sequentially formed over the surface of the dielectric layer; the electrical layer is the first or second dielectric layer, etc .: the third dielectric layer and the The first side; the quality layer 'xi to form a gap wall, which is located on both sides of the gate layer, inside the semiconductor substrate', which is located in the conductive element μ t south doped plutonium region of the gap wall. 'Used as the source / drain of the semi-defense 7L piece; D is tempered; the first dielectric layer is removed; and a metal silicide process is performed. The method of item 21 of the patent scope of 2 2j, I, ι, ^ I, wherein the semiconductor substrate to 乂 includes an N-type semiconductor substrate. 2 3 j. The method of applying for item 21 of the patent scope is to be printed, wherein the gate layer mentioned above is at least 3 crystalline silicon. Page 16 46 32 6 7 6. Application for Patent Scope 2 4. The method for applying for Scope 21 of the Patent Application, wherein the first dielectric layer includes at least one of the following: nitrogen oxide (NO) or dinitrogen oxide (N20 ). 25. The method of claim 24, wherein the first dielectric layer is formed by a rapid oxidation and nitridation method. 26. The method of claim 24, wherein the thickness of the first dielectric layer is about 20 angstroms to 30 angstroms. 27. The method of claim 21 in the scope of patent application, wherein the highly doped dopant includes at least one of the following: boron or boron fluoride. 28. The method of claim 21 in the scope of patent application, wherein the above-mentioned highly doped dopant ion implantation energy is about 0.5 to 8 k e V. 29. The method of claim 21, wherein the second dielectric layer includes at least TEOS. 30. The method according to item 21 of the scope of patent application, wherein the third dielectric layer includes at least nitride stone. 31. The method of claim 21 in the scope of patent application, wherein the metal silicide includes at least the following: titanium, molybdenum, button, tungsten, cobalt. Page 17 4 632 6 7 This method includes at least six 'application patent scopes 32 — a method of preventing boron infiltration to generate pM0s, providing — an N-type semiconductor substrate; a f-type oxide layer is opened on part of the N-type semiconductor A conductor layer is formed above the concrete surface; a gate layer is formed above the surface of the gasification layer of the gate; n-type ϊ i-i: a concrete layer is above and on both sides of the surface of the gate layer and the ^ 1 flat conductor bottom The nitrogen oxide layer is used to prevent boron penetration and external diffusion on the surface of the material. The highly doped drain electrodes forming two shallow junctions are located below the two sides of the gate layer. ; 'Sequentially formed-Cong layer and-nitride stone layer on the surface of the nitrogen oxide layer, using the anisotropic rice carving method in order to silk year old 蝼 蝼 gas, hereby a person of 1 μ] etched to J The siliconized silicon layer and the TEOS layer are separated from each other to form a gap wall, which is located on both sides of the gate layer. A double doping is formed in the N-type semiconductor substrate, which is located on both sides of the wall. And the highly doped drain region are used as the source / drain of the semiconductor element; ^ is used for the tempering process; the portion is removed Nitric oxide layer; and a metal silicide process is performed. : Contains Π; Method of Patent Scope No. 32 '... at least the polar layer 4 6326 7 6. Scope of Patent Application 34. The method of item 32 in the scope of patent application, wherein the polysilicon etching is made by self-aligned reactive ion etching. 35. The method of claim 32, wherein the above gate layer contains at least one of the following dopants: boron, phosphorus, or arsenic. 36. The method of claim 32, wherein the dopant is doped by an ion implantation method. 37. The method according to item 32 of the scope of patent application, wherein said dopant is doped by a thermal diffusion method. 3 8. The method according to item 32 of the scope of patent application, wherein the nitrogen oxide layer includes at least one of the following: nitrogen oxide (NO) or dinitrogen oxide (N2O). 39. The method according to item 38 of the scope of patent application, wherein the above-mentioned nitrogen oxide layer is formed by a rapid oxidation and nitridation method. 40. The method of claim 38, wherein the thickness of the above-mentioned nitrogen oxide layer is about 20 angstroms to 30 angstroms. 41. The method of claim 32, wherein the highly doped dopant includes at least one of the following: boron or boron fluoride. Page 19 4 β 3 2 6 7 VI. Patent Application Range 42 'The method as described in item 32 of the patent application range', wherein the above-mentioned highly doped thrust ion implantation energy is about 0.5 to 8 keV. 43. The method according to item 32 of the scope of patent application, wherein the metal silicide includes at least one of the following: titanium, molybdenum, button, tungsten, cobalt. 44. A method for preventing PMOS from infiltrating to generate a PMOS, the method at least comprises providing a formation, a formation, a formation, and an outer diffusion which are respectively located in a formation of an N-type semiconductor; On the side, the semiconductor element is returned to the N-plastic semiconductor substrate; the gate oxide layer is above a part of the surface of the N-type semiconductor substrate; the gate layer is above the surface of the gate oxide layer; the highly doped drain electrode of the shallow junction is the N In a semiconductor substrate, the gate layer is below both sides of the gate layer; the nitrogen oxide layer is above the surface of the gate layer and on both sides and above the surface of the substrate, and the nitrogen oxide layer is used to prevent boron from penetrating and forming— A TEOS layer and a silicon nitride layer are sequentially etched on the surface of the nitrogen oxide layer by an isotropic etching method to etch the silicon nitride layer and the TE0s layer 1 ′ 2 ′, which are located on both sides of the gate layer; $ Pushing in the N-type semiconductor substrate 'it is located below the gap' and in the range of the highly doped drain region, used as the source / drain of the component; IHI Page 20 463267 6. Scope of patent application Remove this part of the nitrogen oxide layer; and carry out the metal silicide process. 45. The method of claim 44 in which the above-mentioned gate comprises polycrystalline silicon. V 46. The method according to item 44 of the scope of patent application, wherein the last engraving is made by self-aligned reactive ion etching. V. Erosion of the sun and sand 47. If the method of applying for the patent No. 44 of the patent park, it contains one of the following dopants: boron, phosphorus or crushed. < The above-mentioned gate layer is at least 48. The sub-implantation method is doped as in the method of the 44th aspect of the patent application. The above-mentioned dopants are doped by a diffusion method such as the method described in item 44 of the Chinese patent application. Among them, the above-mentioned dopant is based on 埶 50. As described in item 44 of the patent application, at least the following--nitrogen oxide (NO) or oxidized: the above-mentioned nitrogen oxide layer to 乂 emulsified mononitrogen U2). 51. For example, the scope of application for patent No. 50 is formed by rapid oxidation and nitridation methods. ... of the above-mentioned gasification nitrogen layer, 463267 6. Application for patent scope 5 2. The method of applying for the scope of patent application No. 50, wherein the thickness of the above-mentioned nitrogen oxide layer is about 20 angstroms to 30 angstroms, 53. The method according to item 44, wherein the highly doped dopant includes at least one of the following: boron or boron fluoride. 54. The method of claim 44 in which the above-mentioned highly doped dopant ion implantation energy is about 0.5 to 8k eV. 5 5. The method according to item 44 of the scope of patent application, wherein the above-mentioned metal lithophyte contains at least one of the following: titanium, pin, sister, Yan, and Shi. Page 22