TW463128B - Boot system - Google Patents

Abstract

A boot system comprises: a first flash memory; a second flash memory; a CPU, and a selection circuit. The first flash memory is used to store a first boot program and a first system program code. The second flash memory is used to store a second boot program and a second system program code. The CPU is used to output a chip selection signal, and reads from the first flash memory or the second flash memory. The selection circuit comprises a third memory for recording a first value or a second value, and a slot selection device for receiving a chip selection signal. When the content of the memory is a first value, the CPU reads from the first flash memory; when the content of the memory is a second value, the CPU reads from the second flash memory, thereby performing a boot operation.

Description

463 12 8 V. Explanation of the invention (1) The present invention relates to a booting system with a selectable system code ', and in particular to a bootable system with a selectable system code that can perform software upgrade (sftware upgrade) . In consumer digital products that use embedded CPUs, product manufacturers usually need software upgrades for this digital product for business needs or to improve product stability. In addition to software upgrades for digital products, a good boot system is also essential. Please refer to Figures 1 A ~ 1 B ', which shows the booting system of traditional digital products. Figure 1A shows the boot system of the first traditional digital product; Figure 1B shows the boot system of the second traditional digital product. Please refer to figure j A. For a digital product, such as a digital satellite receiver, the boot system usually includes a central processor unit (CPU), hereinafter referred to as CPIOIOO, a first socket 102 and a second socket 104. Placed on the first slot 102 is a read-only memory (ROM) 106 that stores a boot program for booting (B001), and its memory capacity is, for example, 256Kbyte. Socket 104 is a flash memory (Fiash Memory) 108 for storing System Code, and its memory capacity is, for example, 1Mbyte. Among them, the 'boot program is a basic input / output system ( (B asic I nput / Output System, BIOS) o When the digital product is powered on and starts the power-on operation, the CPU 1 0 0 reads the read-only memory 1 in the bootable slot 1 0 2 After booting the program, then read the system of flash memory 1 0 8 on the second slot 104.

463 1 2 ε V. Description of the invention (2) System code ’to enable the digital product to operate normally. When the digital product needs to update the system code of the flash memory 1 08 in the second slot, the new system code must be stored in a dynamic random access memory (Dynamic Random Access Memoi'y) first. DRAM) U0. Then, program the system code into the flash memory 108. After the programming is completed, the operation of updating the system code is completed. Among them, the CPU 100 can download the new system code to the dram through the network or satellite connection to the server 'for burning operation. Moreover, the CPU 100 stores the new system code in the DRAM, and the code required in the programming is provided by the flash memory 108 of the second slot 104. However, 'if the system is unstable and the power is cut off during the programming process', the system code will fail to be flashed to the flash memory 丨 〇8 and the flash memory 1 〇8 will not work properly. use. In this way, after the next boot, the C P U 1 0 0 cannot read the system code of the flash memory 1 0 8 in the second slot 104, which makes the digital product unable to work normally. But 'Because the system program of flash memory 1 08 in the second slot 丨 0 4 is no longer available, cp U 1 〇 00 cannot obtain new system code from the server, and cannot perform flash memory The recording operation in the body 108 can only send this digital product to the factory for repair, which causes inconvenience in use. Please refer to Fig. 1B, "To solve this problem, another traditional method is to" install the first flash memory 112 with a large capacity in the first slot 102 ", whose capacity is, for example, 1Mbyte. The first flash memory 112 in the first slot 102 is large because of its large capacity.

4 63 12 8 V. Description of the invention (3) The machine program and all system code for normal operation of the digital product are placed in the first flash memory 1 1 2 in the first slot. The content of the second flash memory 1 1 4 in the second slot 104 only contains system code. When CPU 100 executes the booting operation, it reads the boot code and system code of the first flash memory 1 12 in the first slot 102. Only when necessary, can the system code of the second flash memory 1 14 in the second slot 104 be read. When the CPU 1 00 is to update the system code of the second flash memory 1 1 4, the CPU 1 00 completes the update of the second flash by reading the system code of the first flash memory 1 1 2 Flash memory 1 1 4 action. Similarly, when the CPU 1 0 needs to update the system code of the first flash memory 1 12, the CPU 1 0 0 reads the system code of the second flash memory 1 1 4 to The operation of updating the first flash memory 1 1 2 is completed. However, if the system is unstable and power is lost during the process of updating the first flash memory 1 12, the operation of updating the first flash memory 1 12 will fail. That is, the operation of burning the new system code to the first flash memory 1 1 2 is interrupted, so that the first flash memory 1 1 2 cannot be used again. In this way, the next time the system restarts, C P U 1 0 0 cannot read the contents of the first flash memory 1 12 and cannot perform the startup operation. Finally, this digital product can only be sent to the factory for repair, which causes considerable inconvenience in use. In view of this, an object of the present invention is to provide a booting system. By selecting the flash memory to be used for the booting operation, the above-mentioned problem of being unable to boot due to the failure of the programming operation can be avoided, and the system is increased.

463 12 V. Description of the invention (4) Efficiency and stability of the system. According to the purpose of the present invention, a boot system is provided, which includes a first flash memory, a second flash memory, a central processing unit, and a selection circuit. The first flash memory is used to store a first boot program and a first system code, and the second flash memory is used to store a second boot program and a second system code. The central processing unit outputs a chip selection signal and reads the first flash memory or the second flash memory to perform a booting operation. The selection circuit includes a third memory and a slot selection device. The third memory is used to record a first value or a second value. The slot selection device is used to receive a chip selection signal. When the content value of the memory is the first value, the central processing unit reads the first flash memory to perform a booting action; when the content value of the memory is the second value, the central processing unit reads the second flash memory Memory for booting. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: 1st A ~ 1 Figure B shows the booting system of a traditional digital product; Figure 2 shows a block diagram of a booting system according to a preferred embodiment of the present invention; Figure 3 shows the first kind of a preferred embodiment according to the present invention The circuit diagram of the booting system; and FIG. 4 shows a circuit diagram of the second booting system according to a preferred embodiment of the present invention.

V. Description of the invention (5) Label description: 100, 200: Central processing unit 102, 202: First slot 104, 2 0 4: Second slot 1 0 6: Read-only memory 1 0 8: Flash memory Bank 1 1 0: Dynamic Random Access Memory 1 1 2, 2 0 3: First Flash Memory 1 1 4, 2 0 5: Second Flash Memory 2 0 6: Selection Circuit 2 0 8, Non Volatile memory 2 1 0: slot selection device 2 1 2: delay unit 302: 0 type flip-flop 304, 404: multiplexer 3 0 6: inverter 4 0 2: microprocessor 4 0 6: —A preferred embodiment of the secondary triggering monostable logic circuit is shown in FIG. 2, which illustrates a block diagram of a booting system according to a preferred embodiment of the present invention. The booting system according to the present invention includes a central processor unit (CPU) hereinafter referred to as a CPU 200, a first slot 2 0 2 and a first flash memory 2 3, a second slot 2 0 4 and The second flash memory 205, and the selection circuit 206. Among them, select

Five 'Explanation of the invention (6) Circuit 206 sentence Kugu # 2 0 8. The non-volatile memory (Non-Volatne Register) slot selection I is set to 21D, and the delay unit 212. The first flash memory 203 in the required betting slot 202 includes the second Chinese code when the system is turned on and the system code required to make the system operate normally. The second flash memory 205 is also provided with a system code when it is turned on. When the system program and the system program required for the normal operation of the system are located in the slot 2 of the slot The boot program of the first flash memory 2 0 or "pq pq: ... is damaged or needs to be updated, then the CPU 2 0 0 can read the system code in the second line i ί 体 2 05" New action on the 2nd flash memory 2 0 3. f In the traditional method of FIG. 1B, whenever the CPU is turned on, the CPU 1pu, 1 # ^ \ a chip selection signal CS () to the first flash in the first slot 102. The Japanese and Japanese movie selection signal CS0 includes a start address (start h 'used to indicate the start address of the first flash memory 2 to be read after booting. And the first slot 102 of the first flash memory 112 = 22 The boot program corresponding to the start address is sent to 〇100 for the booting action. 沾？ 5 test Ϊ 2 diagrams' and in order to achieve the optional flash memory of the present invention _ 发明 The CPU 2 0 0 of the invention is a chip The selection signal CS0 is first transmitted = the circuit 2 06 is selected, and then transmitted to the first slot 202 or the second slot 2 04. The non-volatile memory 2 0 8 is used for storage-the first value or A second = is used to record the flash memory to be used when the system is turned on. For example, when the content value of the non-volatile memory 2 08 is a value, then the circuit 2 6 selects the chip selection signal. (^ 〇 teleport to the first slot

Page 9 4 6c ^ V. Description of the invention (7) ----------, 2 "Type 2 and parallel reading system process type 1 slot 20 2 ... Flash memory 2 ° 3 of the boot-: i:,: = slot 2. The selection test of the middle film is transmitted to the second slot 2. 4 'and reads the boot program and system code of the $ U # PI flash memory 205 to start the operation with j 仃 and make the system normal operating. Upward Pole. The operation of the slot is performed by the slot selection device 2 1 0. The read device 2 1 10 reads the value of the non-volatile memory 208 slot 20 2 or the second slot 204. When the content of the non-volatile memory Zhao 20 8 read by the slot selection is set to the first value as 0Λ ′, the slot selection device 210 selects the chip 2 as the chip. When the non-volatile mm content value read by the slot selection device 210 is the second value, for example, 1, the slot selection device 210 transmits the chip selection signal cs0 to the second slot 204. When the system is turned on, the system generates a system reset signal SR to trigger the nonvolatile memory 208 to transmit its content value to the slot selection device 10. Moreover, the system reset signal indicates that the SR has undergone a delay. Unit 212 is pressed, & 2 0 0, CPU 2 0 2 0 3 or the boot program in the second flash memory 2 05 to start the booting operation. The main function of the delay unit 212 is to make the CPU 200 perform the operation time later than the time when the chip selection signal cso is transmitted to the first flash memory 203 or the second flash memory 208. In this way, after determining the flash memory to be read during the power-on operation, perform the power-on operation before

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V. Description of the invention (8) It will not cause the CPU 200 to malfunction. Take the content value of the non-volatile memory 208 as the first value (0) as an example. At this time, 'C P U 2 0 0 reads the first flash memory 2 0 3 in the first slot 2 0 2 and performs a boot operation. After booting, if the system needs to update the system code in the second flash memory 205, the following steps will be performed: First 'CPU 2' 0 0 read the first flash memory 2 〇3 System code to download new system code from the server to a Dynamic Random Access Memory (DRAM) (not shown in the figure). Then, the CPU 2000 reads the system code in the first flash memory 2 03 to burn the new system code in the DRAM to the second flash memory in the second slot 204 Body 2 0 5. After the programming is completed, the system changes the value of the non-volatile memory 2 0 8 to the second value. Read the second flash in the first slot 204 and the second flash memory 205 in the second slot 204 in the second slot. ”” Ϊ zf When the new action of the system program of the flash memory 2 0 3 is performed, the CPU 20 0 will read the system code of the second flash memory I 2 0 5 of the second slot 2 04 _ The first update of the second memory 2 0 3 is the action of the new system code. ^ The operation of the new system code by T yi di mian β 。. After the burning operation is completed, the system saves the non-volatile memory 2 The content value of 〇8 is changed to the first value (0). At the next power-on, the CPU 200 will read the first flash memory 203 in the first slot 002 for power-on. Action: If the power is off due to system instability during the flashing of the first flash memory 203, the 'flashing of the first flash memory 203'

4 63 1 Description of the Invention (9) The action was declared a failure because it could not be programmed completely. However, because the content value of the non-volatile memory 208 can be changed only when the programming is successful. So if the operation of flashing the first flash memory 203 in slot 204 is failed, the next time the computer is turned on, cpli 200 will still read the second slot in slot 204. Two flash memory 205 to start the operation. In this way, it will not be the case that in the traditional method, the first flash memory in the first slot 102 is burned, and the operation of the flash memory 1 12 fails, resulting in a failure to boot. In addition, when the flash memory is to be programmed, c p U 2 0 0 will send a second chip selection command CS 1 to transmit the address of the flash memory to be programmed. And 'If the CPU 200 performs a delay when the CPU 200 performs a power-on action, the delay unit 2 i 2 of the present invention is not needed, and Cp (j 2 0 0 The memory reads the system code. And the 'boot program can also be updated during the process of updating the system code. That is, the new boot program and system code can be downloaded from the server to the DRAM at the same time. Then, CPU 2 0 0 reads the system code in the first flash memory 2 03 to burn the new boot program and system code in the DRAM to the second flash memory in the second slot 2 0 4 In the body 205. Similarly, the CPU 200 can also update the boot program and the system code of the first flash memory 203 in the first slot 202. In the present invention, the non- Volatile memory can also be replaced by flash memory. As long as it can reach the memory whose content value will not disappear after shutdown, it is in line with the spirit of the present invention. Example of circuit design

Page 12 5. Description of the Invention (ίο) is for illustration 'but it is not sufficient to limit the invention. Please refer to FIG. 3, which shows a circuit diagram of a first booting system according to a preferred embodiment of the present invention. The slot selection device 21 can be implemented using a D-type flip-flop 302 and a multiplexer 304. When the system is turned on, the system reset signal of 5 feet is input to the CPU 2 0 0, the first flash memory 2 0 3 and the second flash memory 2 0 5 'and the inverter 3 0 6 Send to D-type flip-flop ^ 〇2: Clock signal input terminal CK. After receiving the 0/1 signal transmitted by the non-volatile shame body 208, the D-type flip-flop 302 transmits the 0/1 signal to the multiplexer & 304. The multiplexer 304 also receives the chip selection signal CSO from the CPU 200 round. The multiplexer 304 transmits the chip selection signal cs0 to the first slot 202 or the second slot 204 according to the received 0/1 signal, so that the CPU 200 reads the first flash memory 203 or The second flash memory 205 is used to complete the booting action. Among them, the reason why the inverter 206 is used is because the trigger signals required by the D-type flip-flop 210 and the CPU 200 are inverted. In addition, since the CPU 200 starts to perform the booting operation later than the D-type flip-flop 3 02, it is not necessary to use the delay unit 2 1 2 in this example. Please refer to FIG. 4 ', which shows a circuit diagram of a second booting system according to a preferred embodiment of the present invention. The slot selection device 21 can be achieved by using the microprocessor 402 and the multiplexer 404, and the delay unit 212 can be a one-shot triggering monostable logic circuit (One ~ Shot Mono-stable Logic) 406. When the system is turned on, the “system reset signal” is input to the microprocessor 402 and the one-shot monostable logic circuit 4 06. The one-shot monostable logic circuit 40 6 is triggered by the system reset signal SR and then outputs One pulse

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V. Description of the invention (11) A wave signal is used to trigger the CPU 20 0, the first flash memory 203 and the second flash memory 205. After receiving the signal transmitted by the non-volatile memory 208 * from the microprocessor 4 02, it transmits a 0/1 signal to the multiplexer 404. The multiplexer 400 receives the chip selection signal C S0 output from the CPU 200. The multiplexer 304 transmits the chip selection signal CS0 to the first slot 2202 or the second slot 2 04 according to the received 0/1 signal, and reads to fetch the first flash memory 2 0. 3 or the second you ^ memory 2 0 5 to complete the boot action. ^ Internal effect [Inventive effect] The booting system disclosed in the above embodiments of the present invention uses a flash memory to perform a booting operation ... to avoid the problem of being unable to boot due to burning, and to increase the efficiency and stability of the system. As mentioned above, although the present invention has been disclosed as above with a preferred implementation, it is not intended to limit the present invention. Any person skilled in the art can deviate from the spirit and scope of the present invention and make various changes and modifications. The scope of protection of the invention shall be determined by the scope of the attached patent application.

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Claims (1)

6. Scope of Patent Application 1. A boot system > includes a first memory for storing a first boot program and a first system program and a second memory for storing a second boot program and a first system Code> a central processing unit 'is used to output a chip selection signal and read the first --- flash memory or the second-flash memory to perform a booting action 9- a selection circuit, including *-a third memory Memory for recording a first value or a second value * a slot selection device for receiving the chip selection signal when the content value of the second memory is the first value) read by the CPU The first memory to perform a booting action> when the content value of the second memory is the second value, the central processing unit reads the 2 memory) for booting operation 0 2. The booting system as described in item 1 of the scope of patent application »wherein the first and second memories are flash memory 0 3. If _ please the scope of patent item 1 In the booting system, the selection circuit further includes a delay unit for delaying the booting operation of the central processor by 0. 4. The booting system described in item 3 of the patent scope > wherein the delay unit includes Trigger a monostable logic circuit once (0 ne -Sho t Mo no -S tab 1 e Logic) 〇 5. As described in the first range of the patent scope of the boot system 5 wherein the boot system further includes a first Slots and Caps — Look at the slots used to place the Page 16 463 128 6. Scope of patent application The booting system described in the first memory and the second memory, wherein the first memory. The booting system according to the above item, wherein the booting system according to the above item, wherein the memory or the second memory is updated by the first memory to complete the programming operation of the first memory, and when the During the central processing operation, the booting system described in the content item of the third memory, wherein the first system code or the code of the central memory performs an update burning operation. The booting system according to item 9, wherein the first booting program of the memory or the flashing operation is performed by the new booting program. The boot system according to item 1, wherein the sixth memory in the scope of patent application is a non-volatile memory 7. The third memory in the scope of patent application is a flash memory. 8. If the first CPU in the scope of the patent application is used to program the first record, when the central processing is performed, the internal device of the third memory completes the program to the second memory. The second value. 9. If the scope of the patent application is No. 8, the central processing unit is used for the second system memory of the first second memory. If the scope of the patent scope is applied, the central processor is further used for the first and second memory. The second start-up process 11. If the first range of the patent application scope is 0. 12. The booting system as described in item 1 of the scope of patent application, wherein the second value is 1. 1 3. The booting system as described in item 1 of the patent application scope, wherein the slot selection device includes a multiplexer. 14. The booting system described in item 13 of the scope of patent application, wherein the Page 17 4 Ί 2β 6. The scope of patent application Slot selection device includes a flip-flop. 15. The boot system described in item 13 of the scope of patent application > wherein the slot selection device further includes a '-microprocessor 0 16 The boot system described in item 1 of the scope of patent application; system, which The chip selection signal includes a start address. The start address is used to instruct the central processing unit to perform a boot-up action. The start address of the first or second memory or the second memory to be fetched is 0 17 .--A boot system that is generated when the boot system performs a boot action-^ System reset signal The boot system includes a first flash memory for storing a first boot program and a first system The code t < the second flash memory is used to store the second boot program and a first system code > the CPU is used to output a chip selection signal And read the first flash memory or the second flash memory j and perform a booting action ♦ a memory for recording a first value or-~ f a second value flip-flop for receiving the memory The first value or the second value receives the system reset signal and outputs the first value or the second value> the multiplexer receives the first value or the second value transmitted by the flip-flop and receives The chip selection signal y, when the content value of the memory is the first value, the central processing unit reads the first flash memory and performs a boot operation; when the content value of the memory is the second value, the central processing unit The device reads the second flash memory, and performs a booting action. 18 The booting as described in item 17 of the scope of patent application: Page 18 463128 6. Scope of patent application The first value is 0, and the second value is 1. 19. The boot system according to item 17 of the scope of patent application, wherein the memory is a non-volatile memory. 20. The booting system as described in item 17 of the scope of patent application, wherein the central processing unit is further configured to perform a flashing update operation on the first flash memory or the second flash memory. When the central processing unit completes the programming operation of the first flash memory, the content value of the memory is the first value, and when the central processing unit completes the programming operation of the second flash memory, the memory The content value of the body is the second value. 2 1. A boot system, when the boot system performs a boot operation, the boot system generates a system reset signal, the boot system includes: a first flash memory for storing a first boot program and a The first system code; a second flash memory for storing a second booting program and a second system code; a central processing unit for outputting a chip selection signal and reading the first flash Flash memory or the second flash memory and perform a booting action; a memory for recording a first value or a second value; a microprocessor for receiving the first value of the memory Or the second value, receiving the system reset signal, and outputting the first value or the second value: a multiplexer for receiving the first value or the second value transmitted by the microprocessor, Receiving the chip selection signal sent by the central processing unit, when the content value of the memory is the first value, the central processing unit reads the first flash memory and performs a booting operation, when the memory Content value Page 19 4 6n,.: A VI. When the patent application scope is the second value, the central processing unit reads the second flash memory and performs a booting operation. 2 2. The booting system as described in item 21 of the scope of patent application, wherein the booting system further comprises a one-shot mono-stable logic circuit (One-Shot Mono-stable Logic) for receiving a reset signal of the system And generate a pulse signal to trigger the central processing unit. 2 3. The boot system according to item 21 of the scope of patent application, wherein the first value is 0 and the second value is 1. 2 4. The booting system as described in item 21 of the patent application scope, wherein the memory is a non-volatile memory. 25. The booting system according to item 21 of the scope of patent application, wherein the central processing unit is further configured to update the first flash memory or the second flash memory, and when the central processing unit When the processor completes the programming operation on the first flash memory, the content value of the memory is the first value, and when the central processing unit completes the programming operation on the second flash memory, the memory The content value is the second value. Page 20