TW463096B

TW463096B - Enhanced high performance PCI

Info

Publication number: TW463096B
Application number: TW087105008A
Authority: TW
Inventors: Paul L Clouser; Richard Allen Kelley; Danny Marvin Neal; Charles Ray Johns; Steven Mark Thurber
Original assignee: Ibm
Priority date: 1997-06-11
Filing date: 1998-04-02
Publication date: 2001-11-11
Also published as: KR19990006433A; CA2236060A1; ID21264A

Abstract

A peripheral component interconnect (PCI) bus is adapted for differential signaling. Two signal lines are providing for each bus signal and information is encoded as either a polarity or a magnitude of a voltage difference between the two signal lines. Enhanced PCI compliant devices include drivers and receivers capable of differential signaling. The resulting bus architecture supports clocking data on both edges as well as source synchronous clocking. The enhanced PCI bus architecture also supports data blocking, pacing, split transactions, and synchronization commands.

Description

46309 6 五、發明説明（46309 6 V. Description of Invention (

相關申請案本發明係與下列概括.性讜、命 .... , 丨生逼渡的待審美國專利申請案之主題有關：於出申請的 (内部案號AT9· 經濟部中央標準局員工消費合作社印裝 96-329)"用於具有差動卢味m 動彳5唬傳送之較高性能周邊元件互連的新連接器”；以及於—^提㈣㈣_<㈣㈣ AT9-97-G37)用於具有差動信號傳送之增強型周邊元件互連之驅動器/接收器雷致” 电路。本發明特此引用上述待審申請案之内容以供參照。發明背景 1, 技術領域：本發明係大致有關資料處㈣統中之匯流排架構，尤係有關PCI現有匯流排架構之強化。更具體而言，本發明係有關提供一種採用差動信號傳送之增強型匯流排架構，並有關經由一匯流排至匿流排橋接功能而支援現有的PCI介面卡。 2. 相關技街説明：資料處理系統在諸如工業標準架構（Industry standard Architecture ;簡稱ISA)及延伸工業標準架構（Extended Industry Standard Architecture ;簡稱 EISA)等舊型輸入 / 輸出（I/O)標準架構下，通常會遭遇到資料瓶頸。當資料傳輸速率無法滿足資料處理系統内的處理單元或其他組件的需求時，將發生這些瓶頸。目前已藉由較高頻寬匯流排的長·供’而開發出足以消除此種瓶頸的替代I/O架構。一種此類替代架構是周邊元件互連（Peripheral Component -4 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨OX 29?公釐） (#先閱讀背面之注意事項再填寫本頁) :---------_--ί----ri'装-----τ I 訂---- 4 63 09 6 A7 B7 五、發明説明（2Related applications The present invention is related to the following topics: sex, life, ..., 丨 the subject of a pending US patent application: forced to file (internal case number AT9 · staff of the Central Bureau of Standards, Ministry of Economic Affairs (Consumer Cooperative Print 96-329) " New connector for interconnecting higher-performance peripheral components with differential transmissions and dynamic transmission "; and ^ 提㈣㈣_ < ㈣㈣ AT9-97-G37 ) Driver / Receiver Lightning for Enhanced Peripheral Component Interconnect with Differential Signal Transmission. The present invention hereby cites the contents of the above pending application for reference. BACKGROUND OF THE INVENTION 1. Technical Field: The present invention relates generally to a bus architecture in a data processing system, and more particularly to an enhancement of an existing PCI bus architecture. More specifically, the present invention relates to providing an enhanced bus architecture using differential signal transmission, and to supporting an existing PCI interface card through a bus-to-bus bridge function. 2. Description of relevant technology streets: Data processing systems are in the old input / output (I / O) standard architectures such as Industry standard Architecture (ISA) and Extended Industry Standard Architecture (EISA). Under these circumstances, data bottlenecks are often encountered. These bottlenecks occur when the data transfer rate cannot meet the needs of processing units or other components within the data processing system. At present, alternative I / O architectures have been developed to eliminate such bottlenecks through the long supply of higher bandwidth buses. One such alternative architecture is Peripheral Component Interconnect (Peripheral Component -4 This paper size applies to Chinese National Standard (CNS) A4 specifications (2 丨 OX 29? Mm) (#Read the precautions on the back before filling this page): ---------_-- ί ---- ri 'equipment ----- τ I order ---- 4 63 09 6 A7 B7 V. Description of the invention (2

Interconnect ;簡稱PCI)區域匯流排，這是—種具有多工位址及資料信號線之32位元或64位元匯流排。若要得^ 現行PCI區域匯流排標準的機械、電氣、及作業特性，: 參閲由 PCI Special Interest Group(P〇rtland，〇reg〇n)出版二 "PCI Local Bus Specification, Revision 2.1-( ,p ^ ^ ^ PC!規格"）。在未來相當長的—段時間中，預期將在資料處理系統中採用現行的PCI規格及（或）變化版本。 PCI、區域匯流排規格提供了 —種與處理器無關的外加卡 (通常亦稱爲擴充卡或介面卡)之介面。因爲交流電切換特性的限制，所以PCI匯流排通常受限於資料傳輸速率及所支援的介面卡插槽數（fan_out)。一 PCI匯流排中之資料傳輸速率及支援的介面卡插槽數具有相依的關係，因而使其 :-項增加時，通常將造成另—項的減少。現行33百萬赫 0、64位兀PCI架構定義冑供了每秒264百萬位元組的尖峰 =料傳輸速率，且每一 PCI 1/〇匯流排最多可支援4個插曰。在現有的工作站要求下，上述資料傳輸速率對許多高 =的介面卡而言是太慢了。現行66百萬赫的⑽架構定供了每秒528百萬位元组的尖峰資料傳輸速率，但每一 PCI I/Q M流排最多只能支援2個插槽。所支援的該介 ::::數受到相當的限制，因而限制了 66百萬赫^ 条構的實用性。因f ’最好能提供—種類似於pci的高效能且爲一般用 =ΓΓ/0匯流排，此種1/0匯流排具有較佳之效能，龙◊ d面卡插槽數大於現行66百萬赫PCI匯流排定經濟部中央標隼局員工消费合作社印製 4 63 09 6 A7 ________ B7 五、發明説明（3 ) 義所能提供者。此種新的匯流排架構最好能經由一個額外的匯流排至匯流排橋接功能而與現有@ pci匯流排架構相容。發明概述因此本發明纟目的在於提供一種用於資料處理系統之增強型匯流排架構。本發明之另一目的在於提供一種經由一個額外的匯流排至匯流排橋接功能而與現有的pCI匯流排架構相容之增強型匯流排架構。本發明之又一目的在於提供一種採用差動信號傳送及其他強化功能且同時可支援現有pCI介面卡之增強型匯流排架構。現在將説明如何達到上述各項目的。一 pci匯流排係適用於差動信號傳送。將兩條信號線提供給每一匯流排信號 ’並將資訊編碼成這兩條信號線間的一電壓差之極性或量。符合PCI規格的增強型裝置包括可用於差動信號傳送之驅動器及接收器。所得到的匯流排架構支援以兩個波緣進行資料的時序控制（Clocking data)、以及來源同步時序控制（source synchronous clocking)。該增強型 PCI 匯流排架構亦支援資料區段化（data blocking)、配速（pacing)、分割交易（split transactions)、同步命令、可選擇的纜線延伸、及額外的匯流排負載。若參照下文的詳細説明，將可易於了解本發明的上述這些及其他的目的、特徵、及優點。 _ 6 - 本紙張尺度適用中國國家標率（CNS ) A4^格（2丨Οχ 297公楚） —-:~~:卜---r'装I- (請先閱讀背面之注意事項再填寫本頁) 丁- 、·=$ 經濟部中央標準局員工消費合作社印製 4 63〇9:名 A7 ~----—_ B7 五、發明説明（4 ) 附圖簡述將在最後的中凊專利範園中述及本發明的創新特徵。然而’若參照下文巾對—實施例之詳細説明，並配合各附圖，將可完全了解本發明及其較佳使用模式、其他目的與優點，這些附圖有：圖1 π出可實施本發明一較佳實施例之一資料處理系統；圖2Α-2Β是在-資料處理系統内的一主機後板或介面卡上的信號線之比較圖；圖3Α-3Β是-資料處理系統内的一介面卡連接器的接腳配置之比較圖；圖4是一個根據本發明一較佳實施例而使用差動信號傳送的增強型PCI匯流排的一雙向信號傳送網路之方塊圖；圖5示出一個根據本發明一較佳實施例而使用差動信號傳送的增強型PCI匯流排之一替代信號傳送網路；圖6A-6B疋可在根據本發明一較佳實施例的一增強型 PCI匯流排中採用的資料時序控制機制之時序圖；以及圖7是可在根據本發明一較佳實施例的一增強型pci匯流排中採用的一資料流動機制之時序圖。較佳實施例之詳細説明現在請參閱各圖示，尤其請參閲圖1，圖中示出一個可實施本發明一較佳實施例的資料處理系統之方塊圖。資料處理系統（100)可以是諸如由IBM股份有限公司（Armonk， New York)生產的RS/6000TM系統。資料處理系統（100)因而包含連接到系統匯流排（108)之處理器（1〇2)與（104)、以本紙乐尺度適用中國國家標率（CNS ) Α4規格（2丨0Χ297公釐） --]---L-----f .裝-- V,:. (#先閱讀背面之注意事碩再填寫本頁j -β 4 63 09 6 經濟部中央標準局員工消費合作社印製 8 A7 B7 五、發明説明（5 ) — ' 及區域記憶體（106)。一主橋接器（"PCI主橋接器〇")(11〇) 亦連接到系統匯流排（1 08)，主橋接器（丨丨〇)提供了 —個在系統匯流排（108)與PCI匯流排（112)間之介面。諸如主择接器（"PCI主橋接器1"(114)等其他的主橋接器提供了在系統匯流排（108)與各PCI匯流排間之類似介面。主橋接器（ιΐ4) it供了 PCI匯流排（116)的一介面。可將至少一個pci介面卡（117a-117n)連接到PCI匯流排（116)。各pci介面卡及（或）擴充匯流排橋接器（118)係連接到 PCI匯流排（112)，該擴充匯流排橋接器（118)提供了 —個在 PCI匯流排（112)與擴充匯流排（120)間之介面。擴充匯流排 (120)可以是ISA或EISA匯流排，提供了若干插槽，用以連接諸如鍵盤/滑鼠介面卡122等輸入裝置。亦可將諸如光碟機等其俾的I/O或周邊裝置經由裝置介面卡（124)而連接到擴充匯流排（120)。Interconnect (referred to as PCI for short) area bus. This is a 32-bit or 64-bit bus with multiple addresses and data signal lines. To obtain the mechanical, electrical, and operational characteristics of the current PCI area bus standard: See the PCI Local Bus Specification, Revision 2.1- (published by PCI Special Interest Group (Portland, 〇reg〇n)) , p ^ ^ ^ PC! Specifications "). For quite some time to come, it is expected that the current PCI specifications and / or variants will be used in data processing systems. The PCI and regional bus specifications provide an interface to processor-independent add-on cards (also commonly referred to as expansion cards or interface cards). Due to the limitation of AC switching characteristics, PCI buses are usually limited by the data transfer rate and the number of supported interface card slots (fan_out). A data transfer rate in a PCI bus and the number of supported interface card slots have a dependent relationship, so that when one item is increased, it usually causes another one to decrease. The current definition of the 33 Mhz 0- and 64-bit PCI architecture provides a peak transmission rate of 264 Mbits per second, and each PCI 1/0 bus can support up to 4 interrupts. Under the requirements of existing workstations, the above data transfer rate is too slow for many high-speed interface cards. The current 66 megahertz frame rate provides a peak data transfer rate of 528 megabytes per second, but each PCI I / Q M stream can only support up to 2 slots. The number of supported :::: numbers is limited, which limits the usefulness of the 66 megahertz ^ structure. Because f 'is best to provide a kind of high-performance similar to pci and for general use = ΓΓ / 0 bus, this 1/0 bus has better performance, and the number of slot of d face card is greater than the current 66 hundred Wanhe PCI Confluence is scheduled to be printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 4 63 09 6 A7 ________ B7 V. Description of the invention (3) The providers of justice. This new bus architecture is ideally compatible with the existing @ pci bus architecture via an additional bus-to-bus bridging function. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide an enhanced bus architecture for a data processing system. Another object of the present invention is to provide an enhanced bus architecture that is compatible with the existing pCI bus architecture via an additional bus-to-bus bridge function. Another object of the present invention is to provide an enhanced bus architecture that uses differential signal transmission and other enhanced functions and can support existing pCI interface cards. How to achieve the above items will now be explained. A PCI bus system is suitable for differential signal transmission. Two signal lines are provided to each bus signal ′ and the information is encoded into the polarity or amount of a voltage difference between the two signal lines. PCI-compliant enhanced devices include drivers and receivers for differential signal transmission. The resulting bus architecture supports clocking data and source synchronous clocking with two edges. The enhanced PCI bus architecture also supports data blocking, pacing, split transactions, synchronization commands, optional cable extensions, and additional bus loads. These and other objects, features, and advantages of the present invention will be readily understood by reference to the following detailed description. _ 6-This paper scale is applicable to China National Standards (CNS) A4 ^ grid (2 丨〇χ 297 公楚) —-: ~~: Bu --- r'pack I- (Please read the notes on the back before filling (This page) D-, · = $ Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 4 63〇9: Name A7 ~ -------- B7 V. Description of the invention (4) Brief description of the drawings will be in the final凊 The patent model garden describes the innovative features of the present invention. However, if you refer to the detailed description of the following embodiments and the accompanying drawings, you will fully understand the present invention and its preferred mode of use, other purposes and advantages. These drawings are as follows: Figure 1 A data processing system according to a preferred embodiment of the invention; Figures 2A-2B are comparison diagrams of signal lines on a host back plate or interface card in the data processing system; Figures 3A-3B are in the data processing system A comparison diagram of the pin configuration of an interface card connector; FIG. 4 is a block diagram of a bidirectional signal transmission network using an enhanced PCI bus using differential signal transmission according to a preferred embodiment of the present invention; FIG. 5 FIG. 6A-6B shows an enhanced PCI bus using differential signal transmission in accordance with a preferred embodiment of the present invention instead of a signal transmission network. A timing diagram of a data timing control mechanism used in a PCI bus; and FIG. 7 is a timing diagram of a data flow mechanism that can be used in an enhanced PCI bus according to a preferred embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference is now made to the figures, and in particular to FIG. 1, which shows a block diagram of a data processing system that can implement a preferred embodiment of the present invention. The data processing system (100) may be, for example, an RS / 6000TM system produced by IBM Corporation (Armonk, New York). The data processing system (100) thus includes processors (102) and (104) connected to the system bus (108), and applies the Chinese National Standards (CNS) A4 specification (2 丨 0 × 297 mm) to the paper scale. -] --- L ----- f .Equipment-V,:. (#Read the cautions on the back before filling in this page j -β 4 63 09 6 System 8 A7 B7 5. Invention description (5) — 'and area memory (106). A master bridge (" PCI master bridge 0 ") (11〇) is also connected to the system bus (1 08) , The main bridge (丨丨〇) provides an interface between the system bus (108) and the PCI bus (112). Such as the main connector (" PCI main bridge 1 " (114) and other The main bridge provides a similar interface between the system bus (108) and each PCI bus. The main bridge (ιΐ4) it provides an interface for the PCI bus (116). At least one PCI interface card ( 117a-117n) are connected to the PCI bus (116). Each PCI interface card and / or expansion bus bridge (118) is connected to the PCI bus (112), and the expansion bus The connector (118) provides an interface between the PCI bus (112) and the expansion bus (120). The expansion bus (120) can be an ISA or EISA bus, and provides several slots for connection Input devices such as keyboard / mouse interface card 122. Other I / Os or peripheral devices such as optical disc drives can also be connected to the expansion bus (120) via the device interface card (124).

熟悉本門技術者當可了解，一可以變化圖1所示之硬體。例如，亦可將光碟機等其他的周邊裝置用來増添到或取代所示之硬體。所示之例子並非意指架構上的限制。使用PCI 匯流排架構或其他匯流排架構的任何資料處理系統亦可採用本發明。根據本發明的一較佳實施例，圖i所示的至少一對的主橋接器及PCI匯流排實施—增強型PCI匯流排架構。例如，主橋接器（114)及PCI匯流排（116)可實施本發明的增強型pci匯流排架構（増強型PCI)，而主橋接器（ιι〇)及pci 匯流排（112)可實施-個符合現有PCI匯流排架構規格的匯本紙張尺度適用中國國家標準（CNS ) A4规柢（1 w八輕 (請先閱讀背面之注意事項再填寫本頁)Those skilled in the art will understand that one can change the hardware shown in Figure 1. For example, other peripherals such as optical disc drives can be used to add to or replace the hardware shown. The examples shown do not imply architectural limitations. The present invention can also be applied to any data processing system using a PCI bus architecture or other bus architectures. According to a preferred embodiment of the present invention, at least one pair of main bridges and PCI buses shown in FIG. I implement an enhanced PCI bus architecture. For example, the main bridge (114) and the PCI bus (116) may implement the enhanced PCI bus architecture (stubborn PCI) of the present invention, and the main bridge (ιι〇) and the PCI bus (112) may implement- The paper size of the paper that meets the specifications of the existing PCI bus architecture is applicable to the Chinese National Standard (CNS) A4 (1w eight light (please read the precautions on the back before filling this page)

怒濟部中央標準局員工消費合作社印製 4 63 09 6 A7 ------ B7 五、發明説明（6 ) 流排（"傳統的PCI")。增強型PCI匯流排（116)支援現有的 PCI協定及信號順序規則。亦支援現有pCI匯流排架構的功能性作業’例如重新嘗試作業。增強型PCI匯流排架構支援32位元的位址/資料匯流排，並可支援64位元的位址 /資料匯流排（在可提供此種支援的接腳數之情形下）。雖然支援許多現有的PCI匯流排架構結構，但是增強型 pci匯流排架構在主橋接器、PCI匯流排、及連接到增強型PCI匯流排的裝置或介面卡上採用了差動信號傳送。因此’增強型PCI匯流排架構定義中的每一信號都需要兩個信號線。也必須定義用於增強型PCI架構的一種新連接器。差動信號傳送環境的加入對於PCI協定而言應是透通的 ’且可得到増加的頻率，該增加的頻率可擴展到所選擇驅動态/接收器技術所需的最大頻率。當在一高出許多的頻率上工作時’必須根據所採用的驅動器/接收器技術及所選擇的實際最大頻率來調整pCI的時序要求。因爲支援了許多現有或”傳統的"PCI協定，所以增強型 PCI匯流排（116)的主橋接器（π 4)可將整合式傳統pci支援 (126)提供給一個傳統的pci匯流排（128)。除了各別匯流排 (116)及（128)的接收器及輸出驅動器級以外，主橋接器 (114)及（12 6)所需的許多作業可採用相同的電路。因此，單增強型/傳統的PCI橋接器（114/126)可經由各別的匯流排而支援到增強型及傳統的PCI裝置之連接。此外，連接到增強型PCI匯流排（116)的一各別橋接器亦可提供連接到傳統PCI裝置之橋接支援，或可由一各別的pCI主橋接器本紙張尺度適用中國國家標準（CNS ) A4規格（2丨0 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) -----{:裝------—訂-------fj.-----^-1;___ 463096 經濟部中央標準局員工消費合作社印製 A7 _____B7五、發明説明（7 ) (110)提供對傳統PCI裝置的支援。請參閲圖2A及2B，圖中示出在—資料處理系統内的一主機後板或介面卡上的信號線之比較圖。圖2A示出採用傳統信號線的效果。PCI匯流排架構目前所採用的傳統單端信號偵測需要偵測相對於接地點的一信號位準（高位準或低位準）。在信號線（202及204)與接地點（206)間之電容性交叉耦合造成了電磁場（208)β因此，在匯流排上傳送資訊的過程中，能量耗用在匯流排電容的充電及放電上。各信號線也相互交叉耦合或干擾，因而產生了雜訊的問題。圖2Β 7F出在一個根據本發明一較佳實施例的增強型 PCI匯流排内的一主機後板或介面卡的一對信號線配置。圖示之信號線配置適用於採用PCI的系統或其他的系統。並不採用目前在PCI匯流排架構中所使用的傳統單端信號線，而是採用了差動信號線對（210a_21〇b)及（212a212b) 。差動彳s號的每一仏號需要兩條信號線，且係偵測這兩條信號線間的電壓差之極性或大小，而傳送資訊。信號線對（21〇a-21〇b)及（2^2121))最好是傳送大小相等但極性相反的信號。亦即，如果信號線（21〇a)載送—個 + 1.0伏的信號，則信號線（210b)同時載送一個_1〇伏的信號。因此，在諸如信號線對（21〇a_210b)等的一^# 接地點㈣間之電磁場可以忽略，這是因爲信與接地點（206)間之電磁場抵消了另—信號線（21〇b)與接地點（206)間之電磁場。只有一信號線對中各信號線間（在 #號線（210a)與（210b)間）之電磁場（214)仍相當顯著。如圖所 _；__- 10- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公楚） (讀先閱讀背面之>i意事項再填离本頁} l· ---1 -I— - —Γ. - -- I —I—--1 --\-"衣 I : _ · ir^ :/·Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Nuoji 4 63 09 6 A7 ------ B7 V. Description of Invention (6) Streamline (" Traditional PCI "). The enhanced PCI bus (116) supports existing PCI protocols and signal sequence rules. Functional operations of the existing pCI bus architecture are also supported, such as retry operations. Enhanced PCI bus architecture Supports 32-bit address / data bus and 64-bit address / data bus (when the number of pins that can provide this support). Although many existing PCI bus architectures are supported, the enhanced PCI bus architecture uses differential signaling on the main bridge, PCI bus, and devices or interface cards connected to the enhanced PCI bus. Therefore, each signal in the definition of the 'enhanced PCI bus architecture requires two signal lines. A new connector for the enhanced PCI architecture must also be defined. The addition of a differential signal transmission environment should be transparent to the PCI protocol and an increased frequency can be obtained, which can be extended to the maximum frequency required for the selected driver / receiver technology. When operating at a much higher frequency, the timing requirements of pCI must be adjusted based on the driver / receiver technology used and the actual maximum frequency selected. Because many existing or "traditional" PCI protocols are supported, the primary bridge (π 4) of the enhanced PCI bus (116) can provide integrated traditional PCI support (126) to a traditional PCI bus ( 128). Except for the receiver and output driver stages of the respective buses (116) and (128), many of the operations required for the main bridges (114) and (126) can use the same circuit. Therefore, the single enhancement Type / Traditional PCI Bridge (114/126) supports connection to enhanced and traditional PCI devices via separate buses. In addition, a separate bridge to the enhanced PCI bus (116) Bridging support for connection to traditional PCI devices is also available, or a separate pCI master bridge can be used. This paper is sized for China National Standard (CNS) A4 (2 丨 0 X 297 mm) (Please read the note on the back first) Please fill in this page again for matters) ----- {: install -------- order ------- fj .----- ^-1; ___ 463096 Staff Consumer Cooperatives, Central Standards Bureau, Ministry of Economic Affairs Print A7 _____B7 V. Description of Invention (7) (110) Provide support for traditional PCI devices. Please refer to Figures 2A and 2B, which are shown in the figure —Comparison of signal cables on a main board or interface card in the data processing system. Figure 2A shows the effect of using traditional signal cables. The traditional single-ended signal detection currently used in the PCI bus architecture needs to detect the relative A signal level (high level or low level) at the ground point. The capacitive cross-coupling between the signal lines (202 and 204) and the ground point (206) caused the electromagnetic field (208) β. Therefore, it was transmitted on the bus In the process of information, energy is used to charge and discharge the bus capacitors. The signal lines are also cross-coupled or interfered with each other, which causes a problem of noise. Figure 2B 7F shows a preferred embodiment according to the present invention. A pair of signal cable configurations of a host backplane or interface card in the enhanced PCI bus. The signal cable configuration shown in the figure is suitable for systems using PCI or other systems. It is not used in the current PCI bus architecture. The traditional single-ended signal lines used are differential signal line pairs (210a_21〇b) and (212a212b). Each signal of the differential 彳 s number requires two signal lines, and these two lines are detected Signal line The information is transmitted using the polarity or magnitude of the voltage difference. The signal line pairs (21〇a-21〇b) and (2 ^ 2121)) are preferably signals of equal magnitude but opposite polarity. That is, if the signal line ( 21〇a) carrying a + 1.0 volt signal, then the signal line (210b) carries a -10 volt signal at the same time. Therefore, at a ^ # ground point such as the signal line pair (21〇a_210b), etc. The electromagnetic field between the two can be ignored, because the electromagnetic field between the signal and the ground point (206) cancels the electromagnetic field between the other-the signal line (21b) and the ground point (206). In only one signal line pair, the electromagnetic field (214) between the signal lines (between line # 210a) and (210b) is still quite significant. As shown in the figure _; __- 10- This paper size applies to the Chinese National Standard (CNS) A4 specification (210X297). (Read the > I on the back of the paper before filling out this page} l · --- 1- I—-—Γ.--I —I —-- 1-\-" 衣 I: _ · ir ^: / ·

、1T 4 63 09 6 第871〇5〇〇8號專利申請案中文說明書修正頁（90年6月）, 1T 4 63 09 6 Patent Application No. 871〇5〇〇8 Chinese specification amendment page (June 90)

煩請委員鸮示早/月幺曰所提之經濟部中央標牟局貝工消費合作社印製修正本有無變更實質内容是否准予修正。示’ -信號線對中各差動信號線間形成的電磁場遠小於一傳統单端信號線與接地點間之電磁場，且前者比後者更局部化因此，當與傳統的信號傳送環境比較時，只需要遠較低的信號位牟轉變即可傳送資訊。於傳送資訊時，耗用在匯流排電容的充電及放電上的能量較少。此外，採用差動仏號傳送時，提咼了對雜訊的耐受性，並可以較高的速率傳送。儘量在資料處理系統採用的主基本及各介面卡上將差動信號線對（210a-210b)及（212a-212b)佈線在一起。此種方式將保證可實現差動信號傳送的效益，亦即消除各信號線與接地點或其他信號線間之交又耦合效應。然而，將各信號線對佈線在一起時，妨礙了與傳統pcI匯流排連接器的相谷性，因為傳統的PCI匯流排連接器在連接器的範圍内並未包含所需额外信號線之實體空間。此外，pci匯流排介面晶片最好是包含差動式驅動器/接收器。請參閱圖3A及3B，圖中示出一資料處理系統内的一介面卡連接器的接腳配置之比較圖。圖3A示出一個傳統的信號接腳配置。如圖所示，信號接腳（3〇4)及（3〇6)與接地腳（308)間之電磁場（302)可以是顯著的。圖3]B示出—個根據本發明一較佳實施例的增強型PCI匯流排之差動信號對配置。圖示之連接器接腳配置可適用於採用PCI的系統及其他的系統。為了利用差動信號傳送的效益且為了信號品質，在連接器中形成一差動對的兩個接腳之每一接腳都相互靠近。類似於圖2B所示之信號線配置’信號接腳對 -11 - 本紙張尺度適用中國國家橾準（CNS )八4規格（210·〆297公釐） ---------广¥-----LI訂'—^-----Q (請先閲讀背面之注意事項再填寫本頁) $年Θ 五、發明説明（Members are kindly requested to indicate whether the amendments printed by the Central Labor Bureau of the Ministry of Economic Affairs of the Central Labor Bureau of the Ministry of Economic Affairs have printed the amendments, and whether the substance of the amendments is allowed to be amended. This shows that the electromagnetic field formed between the differential signal lines in the signal line pair is much smaller than the electromagnetic field between a traditional single-ended signal line and a ground point, and the former is more localized than the latter. Therefore, when compared with the traditional signal transmission environment, It only takes a far lower signal bit to make the transition. When transmitting information, less energy is used to charge and discharge the bus capacitors. In addition, when differential transmission is adopted, the noise tolerance is improved, and transmission can be performed at a higher rate. Try to route the differential signal wire pairs (210a-210b) and (212a-212b) together on the main basic and interface cards used in the data processing system. This method will ensure the benefits of differential signal transmission, that is, eliminate the interaction and coupling effects between each signal line and the ground point or other signal lines. However, when the signal line pairs are wired together, it interferes with the traditional PCI bus connector, because the traditional PCI bus connector does not include the entity of the extra signal line required in the range of the connector. space. In addition, the PCI bus interface chip preferably contains a differential driver / receiver. Please refer to FIGS. 3A and 3B, which are comparison diagrams of pin configurations of an interface card connector in a data processing system. Figure 3A shows a conventional signal pin configuration. As shown in the figure, the electromagnetic field (302) between the signal pins (304) and (306) and the ground pin (308) can be significant. Figure 3] B shows a differential signal pair configuration of an enhanced PCI bus according to a preferred embodiment of the present invention. The connector pin configuration shown in the figure is applicable to systems using PCI and other systems. In order to take advantage of the benefits of differential signal transmission and for signal quality, each of the two pins forming a differential pair in the connector are close to each other. Similar to the signal line configuration shown in Figure 2B, the signal pin pair -11-This paper size is applicable to China National Standard (CNS) 8 4 specifications (210 · 〆297 mm) --------- Wide ¥ ----- LI 订 '— ^ ----- Q (Please read the notes on the back before filling this page) $ 年 Θ 5. Description of the invention (

修正 I I , '^,τ 4 63 09 0 第871050〇8號專利申請案中文說明書修正頁（9〇年6月） ⑴2a·㈣)與⑴4a_314b)間之電磁傳 PCI„接中使用傳統信號接腳配置的連接ίΐ: 電磁％ ’且則者比後者跫届却仆有更局邵化。圖示之一連接器接腳配置亦可讓在每—信號對中使用雙絞線的-個增強型PCI 區流排麟有用於PCI匯流排延伸的1G英尺長或更長。請參閱圖4,圖中示出—個根據本發‘較佳實施例而使用差動信號傳送的增強型PCI匯流排的一雙向信號傳送網路之方塊圖。此類信號傳送網路可用於一個需要雙向傳送能力的增強型PCI匯流排中所有的位址/資料信號線及其他的信號線。信號傳送網路（4〇2)在一輸入端/輸出端 (404)上自一增強型PCI匯流排主控裝置或目標裝置（圖中未不出）接收一單端信號，或傳送一單端信號到該裝置。匯流排主控裝置可以是一 PCI主橋接器、或可作為pCI 匯流排主控裝置的任何其他PCI裝置。信號傳送網路（407) 在一輸入端/輸出端（406)上自一增強型PCI匯流排目標裝置或匯流排主控裝置（圖中未示出）接收—單端信號，或傳送一單端信號到該裝置。匯流排目標裝置可以是一介面卡、或作為PCI匯流排目標裝置的任何其他pci裝置。輸入端（404)係連接到與pci匯流排主控裝置相關聯的單端至差動驅動器（408)，該驅動器（4〇8)根據本門技術中習知的方法而將單端信號轉換成一差動信號。驅動器（408) 經由差動信號線對（41 Oa-4 10b)而傳送差動信號。所傳送的差動信號可以多種方式指示不同的狀態。例如，差動信號線對（4 1 Oa-41 Ob)上的一電壓差可界定兩個不同的狀態？而 -12 本紙張尺度適用中國國家標準（CNS > A4規格（210XM7公缓） (請先閲讀背雨之注意事項再填寫本夏) 訂” .)r 經濟部中央標準局貝工消费合作社印製 4 63 09 6 A7 ---—---------_ 五、發明説明（10) 諸如當電壓差的極性顚倒時，電壓差保持相同的大小，但改變了方向。第一極性可代表（，，高位準"），而相反的極性則代表第二狀態（"低位準"）。此外，差動信號線對（410a_ 41 Ob)上的電壓差亦可保持固定的方向或極性，但沿著相反方向改變大小，其中第—量代表第一狀態，而第二量代表第二狀態。然而不論在哪一種情形，施加到差動信號線對 (41 Oa-41 Ob)的電壓應有相同的量之改變，但卻沿著相對於接地電位的相反方向，因而可以得到抵消的效應。經濟部中喪標率局員工消費合作社印裝 (請先閲讀背面之注意事項再填寫本頁} 差動信號線對（41 Oa-4 1 Ob)亦係連接到與PCI匯流排目標裝置相關聯的接收器（412)，該接收器（412)利用本門技術中習知的方法將差動信號轉換成單端信號。將所得到的單端信號經由輸出端（406)而傳送到pci匯流排目標裝置。因爲需要雙向信號傳送，所以與PCI匯流排目標裝置相關聯的一第二驅動器（414)係連接到輸出端（406)及差動信號線對 (41 Oa-410b)。驅動器（414)自PCI匯流排目標裝置經由輸出端（406)接收單端信號’並經由差動信號線對（4i〇a_41〇b) 傳送對應的差動信號。與PCI匯流排主控裝置相關聯的一接收器（416)係連接到差動信號線對（4 l〇a-41 Ob)及輸入端 (404)，該接收器（416)將所接收的差動信號轉換成單端信號，ϋ將單端信號傳送到PCI匯流排主控裝置。驅動器（408)與(4 14)以及接收器（412)與（416)分別包含一個起動信號輸入端，用以使各別裝置不會在未經觸發的情形下進行傳送或接收。協調施加到這些起動信號輸入端的信號，以便確保在一特定的匯流排週期中只能有一個驅動 -13- 本紙張國國家標準(CNS ) A4規格（2丨0〆297公釐） 1 "** 4 63〇ο,, 、 V ' Α7 Β7 五、發明説明（11 ) ~~ ~~ 器進行傳送。除了交叉耦合以外’與現有PCI架構中採用的傳統單端 fs號線有關的另一問題是反射信號傳送，此種現象限制了 PCI匯流排的實體長度，並因而限制了所支援的介面卡插槽數。若在各信號線上採用平衡式負载，將可消除信號反射，且可得到單一入射信號傳送。因此，每一收發器（418) 及（420)都包含與PCI匯流排主控裝置或pCI匯流排目標裝置相關聯的一對驅動器/接收器，而每一收發器（4 18)及 (420)都在差動信號線對（41 Oa-410b)的連接線上包含-電阻性負載。該電阻性負載包含：連接於一較高電源電壓與一差動信號線（410a)間之電阻R1、連接於一較低電源電恩與另一差動信號線（41 Ob)間之電阻R2、以及連接於差動信號線對（410&)與（4101))間之電阻113。尺1、112、及113之電阻値係經選擇，以便確保：收發器（418)及（420)中不論是誰在傳送且誰在接收，差動信號線對（4 1 〇a-41 Ob)所連接之負載都保持大致爲平衡且固定。驅動器/接收器對（408)及（4 16)最好是設於諸如PCI主橋接器的PCI介面内’且驅動器/接收器對（412)及（414)最好是設於諸如介面卡的一 PCI介面晶片内。在此實施例中，收發器（418)中之終端電阻尺1、112、及113係設於主基板上的靠近PCI主橋接器處。收發器（420)中之電阻網路R1 、R2、及R3亦係设於主機板上的pci匯流排網路末端處。請參閱圖5 ’圖中示出一個根據本發明—較佳實施例而使用差動信號傳送的增強型PCI匯流排之一替代信號傳送 ! -14- 本紙張尺度適州中國國家標準（CNS ) Λ4規格（21〇><297公釐） (請先閱讀背面之注意事項再填寫本頁) ,1Τ 經濟部中央標準局員工消費合作社印製 4 63 0 9 6 A7 --____,— ___ _B7_ 五、發明説明（彳2) 網路（方塊圖。諸如REQ#' GNT#等不需要雙向傳送能力的仏號、.泉可採用此種較簡單的信號傳送網路。信號傳送網路（502)經由連接到驅動器（5〇6)的輸入端（5〇4)自一匯流排主控裝置或目標裝置（圖中未示出）接收單端信號。驅動器 (506)將單知k號轉換成差動信號，並經由差動信號線對 (508a 508b)而傳送差動信號。連接到差動信號線對（5〇8&_ 5^08b)的接收器（51〇)將差動信號轉換成單端信號，並將單端仏號經由輸出端（5 12)而傳送到一匯流排主控裝置或目標裝置（圖中未示出）〇與驅動器（506)及接收器（5 10)相關聯的各電阻性負載確保差動信號線對（5〇8a_5〇8b)係連接到—平衡式負載。在驅動器（506)上係藉由下列各電阻達到上述目的：連接於一較高電源電壓與一差動信號線（5〇8a)間之電阻&、連接於一較低電源電壓與差動信號線（5〇8b)間之電阻&、以及連接於差動信號線（508a)與（508b)間之電阻Rc。_個類似的電阻性負載組態係與接收器（5 10)相關聯，但是在接收器（51〇)Amendment II, '^, τ 4 63 09 0 Patent Application No. 871050008 Chinese Correction Page (June 90) Electromagnetic transmission PCI between ⑴2a · ㈣) and ⑴4a_314b) using traditional signal pins The configuration of the connection: 电磁% electromagnetic, and it is more inferior than the latter. However, the connector pin configuration of one of the illustrations also allows the use of twisted pairs in each signal pair. The PCI zone bus is 1G feet or longer for PCI bus extension. Please refer to FIG. 4, which shows an enhanced PCI bus using differential signal transmission according to the present preferred embodiment. Block diagram of a bidirectional signal transmission network. This type of signal transmission network can be used for all address / data signal lines and other signal lines in an enhanced PCI bus that requires bidirectional transmission capability. Signal transmission network ( 4〇2) An input / output (404) receives a single-ended signal from an enhanced PCI bus master or target device (not shown in the figure), or sends a single-ended signal to the device The bus master control device can be a PCI master bridge or can be used as Any other PCI device of the pCI bus master device. The signal transmission network (407) has an input / output terminal (406) from an enhanced PCI bus target device or a bus master device (not shown in the figure). Out) Receive—Single-ended signal, or send a single-ended signal to the device. The bus target device can be an interface card, or any other PCI device that acts as a PCI bus target device. The input (404) is connected to and The single-ended-to-differential driver (408) associated with the PCI bus master control device, the driver (408) converts the single-ended signal into a differential signal according to a method known in the art. The driver (408) The differential signal is transmitted via the differential signal line pair (41 Oa-4 10b). The transmitted differential signal can indicate different states in various ways. For example, the differential signal line pair (4 1 Oa-41 Ob) A voltage difference can define two different states? And -12 This paper size applies the Chinese national standard (CNS > A4 specification (210XM7 public delay) (Please read the precautions of back rain before filling in this summer) Order.) r Bei Gongxiao, Central Bureau of Standards, Ministry of Economic Affairs Printed by the cooperative 4 63 09 6 A7 ------------------- 5. Explanation of the invention (10) For example, when the polarity of the voltage difference is inverted, the voltage difference remains the same, but the direction is changed . The first polarity can represent (,, high level "), while the opposite polarity represents the second state (" low level "). In addition, the voltage difference on the differential signal line pair (410a_ 41 Ob) can also maintain a fixed direction or polarity, but change the size in the opposite direction, where the first quantity represents the first state and the second quantity represents the second state . However, in either case, the voltage applied to the differential signal line pair (41 Oa-41 Ob) should be changed by the same amount, but in the opposite direction with respect to the ground potential, so that the cancellation effect can be obtained. Printed by the Consumer Cooperatives of the Bureau of Loss of Interest in the Ministry of Economic Affairs (please read the precautions on the back before filling out this page) The differential signal cable pair (41 Oa-4 1 Ob) is also connected to the target device associated with the PCI bus Receiver (412), the receiver (412) converts the differential signal into a single-ended signal using a method known in the art. The obtained single-ended signal is transmitted to the PCI bus through the output (406) Row target device. Because two-way signal transmission is required, a second driver (414) associated with the PCI bus target device is connected to the output (406) and the differential signal line pair (41 Oa-410b). The driver ( 414) Receive the single-ended signal from the PCI bus target device via the output terminal (406) and transmit the corresponding differential signal via the differential signal line pair (4i0a_41〇b). The associated with the PCI bus master control device A receiver (416) is connected to the differential signal line pair (4 10a-41 Ob) and the input terminal (404). The receiver (416) converts the received differential signal into a single-ended signal, ϋ Send single-ended signals to the PCI bus master. Drivers (408) and (4) 14) and the receivers (412) and (416) respectively include a start signal input terminal, so that the respective devices will not transmit or receive without triggering. Coordinate the signals applied to these start signal input terminals, In order to ensure that there can only be one driver in a particular bus cycle. -13- National Paper Standard (CNS) A4 (2 丨 0〆297mm) 1 " ** 4 63〇 ,, V 'Α7 Β7 V. Invention Description (11) ~~~~ In addition to cross-coupling' Another problem related to the traditional single-ended fs number line used in the existing PCI architecture is reflected signal transmission, which is a limitation of this phenomenon The physical length of the PCI bus is limited, and thus the number of supported interface card slots is limited. If a balanced load is used on each signal line, signal reflection can be eliminated, and a single incident signal can be transmitted. Therefore, each transceiver The receivers (418) and (420) each include a pair of drivers / receivers associated with the PCI bus master device or the pCI bus target device, and each of the transceivers (418) and (420) are differential Signal pair (41 Oa-410b) The wiring includes a resistive load. The resistive load includes: a resistor R1 connected between a higher power supply voltage and a differential signal line (410a), connected to a lower power source and another differential signal line A resistor R2 between (41 Ob) and a resistor 113 connected between the differential signal line pair (410 &) and (4101)). The resistances of rulers 1, 112, and 113 are selected to ensure that no matter who is transmitting and who is receiving in the transceivers (418) and (420), the differential signal wire pair (4 1 〇a-41 Ob ) The connected loads are kept approximately balanced and fixed. The driver / receiver pairs (408) and (4 16) are preferably provided in a PCI interface such as a PCI master bridge, and the driver / receiver pairs (412) and (414) are preferably provided in an interface such as an interface card. Inside a PCI interface chip. In this embodiment, the terminating resistors 1, 112, and 113 in the transceiver (418) are disposed on the main substrate near the PCI main bridge. The resistor networks R1, R2, and R3 in the transceiver (420) are also located at the end of the PCI bus network on the motherboard. Please refer to FIG. 5 ′, which shows one of the enhanced PCI buses using differential signal transmission in accordance with the present invention—a preferred embodiment instead of signal transmission! -14- This paper is in accordance with China State Standard (CNS) Λ4 specification (21〇 > < 297 mm) (Please read the notes on the back before filling this page), printed by 1T Consumers Cooperative of Central Standard Bureau of Ministry of Economic Affairs 4 63 0 9 6 A7 --____, — ___ _B7_ V. Description of the invention (彳 2) Network (block diagram. For example, REQ # 'GNT # and other nicknames that do not require bidirectional transmission capability,. Spring can use this simpler signal transmission network. Signal transmission network ( 502) Receive a single-ended signal from a bus master or target device (not shown) via an input terminal (504) connected to the driver (506). The driver (506) will know the k number Converted into a differential signal, and transmits the differential signal via the differential signal line pair (508a 508b). The receiver (51〇) connected to the differential signal line pair (508 & 5 ^ 08b) will differentially The signal is converted into a single-ended signal, and the single-ended signal is transmitted to a bus master through the output terminal (5 12). Device or target device (not shown in the figure). Each resistive load associated with the driver (506) and receiver (5 10) ensures that the differential signal line pair (508a-5008) is connected to a balanced type. Load. The driver (506) achieves the above purpose by the following resistors: the resistance & connected between a higher power supply voltage and a differential signal line (508a), and a lower power supply voltage and The resistance & between the differential signal line (508b) and the resistance Rc connected between the differential signal line (508a) and (508b). A similar resistive load configuration is with the receiver (5 10 ) Associated, but at the receiver (51〇)

上提供一個平衡式負載時，可能需要採用不同的電阻値尺、Ry、及 Rz 〇 X 請參閲圖6A及6B，圖中示出可在根據本發明一較佳實施例的一增強型PCI匯流排中採用的資料時序控制機制之時序圖。如圖6A所示，一個根據本發明—較佳實施例的增強型PCI匯流排可支援以時脈CLK的兩個波緣進行資料的時序控制。位址/資料信號線AD上的資料（6〇2)持續時間然後將只是一半的時脈週期，而支援較高的資料傳輸率。 __ -15- 本紙（CNS)从祕（21GX297公楚） ----—- 請閱讀背 1¾ 意事項再填本頁装訂經濟部中央標準局員工消費合作社印製 4 63 09 6 Α7 Β7 經漪部中央標準局員工消費合作社印製五、發明説明（13 增強型PCI匯流排上的所有裝置必須支援此種選項，以便以兩個時脈波緣進行匯流排上資料的時序控制。可在組態設定時決定對此種特性的裝置支援功能，且增強型PCI匯流排據此而工作。如圖6B所示，根據本發明一較佳實施例的一增強型pci 匯流排亦可支援來源同步資料時序控制，其中資料來源提供一選通脈衝信號STRB，以供資料的時序控制。目標裝置然後使用該資料選通脈衝STRB(非時脈CLK)來區別資料階段。當以兩個時脈波緣進行資料的時序控制時，資料選通脈衝信號STRB可採用與所示時脈信號CLK相同的頻率（但不同的階段），或者資料選通脈衝信號STRB可採用一較高的頻率，但是最好是採用時脈頻率的整數倍，例如 CLK頻率的兩倍。根據本發明一較佳實施例的一增強型PCI匯流排可根據資料區段（並非根據資料階段）來支援資料區段化、或資料流動控制。若干時脈週期決定資料區段，且資料區段爲對準的32位元組。傳送長度被分段成若干固定長度的32位元組區段。於使用可選擇的資料區段化時，資料轉移必須在32位元組的最小區段大小之資料轉移開始處開始進行且.必肩傳送該最小區段大小的整數倍。當資料轉移的最後—個區段小於32位元組時，係以正常的非區段化方式處理該資料轉移。資料區段化時可進行較快速的資料轉移、及資料轉移的優先順序設定。根據本發明一較佳實施例的一增強型PCI匯流排可支援 ____ ____ - 16 - 一本紙張尺£適用 (請先閱讀背面之注意事項再填寫本頁) II---,r 装-----：1111--------- 4 63 09 6 A7 __________B7 五、發明説明（14 ) 目標裝置或王控纟置在s _區段❼資料轉移之後所進行之配速或流速管制、及插入額外的等候狀態(wait state)。當採用可選擇的資料區段化時，只在各資料區段之間容許有配速。當並未使用資料區段化時，可在正常的資料轉移之間容許有配速。現在請參閱圖7，根據本發明一較佳實施例的一增強型 PCI匯流排可支援分割交易，其中對資料轉移的要求係與資料交易本身脱離。一分割交易的讀取要求包含一個唯— 識別該讀取要求之標記。可使一資料交易的位址（7〇4)與該交易的資料（706)分離。介於其間的時脈週期可包含一個不同交易的一位址（708)之傳送。同樣地，某一交易的位址 (708)及資料（710)可與一不同交易的資料（7〇6)分離。可以支援兩個裝置都符合增強型PCI.標準的情形下之分割交易，也可在諸如使用一增強型PCI/傳統pci橋接器的情形下不採用分割交易。除了上述的資料時序控制及資料轉移機制以外，本發明之增強型PCI匯流排亦可支援同步命令。可界定並採用一同步命令’使系統的其餘部分得知各增強型pci交易，因而可以監視同步事件。同樣地，可界定並採用一排序命令，以便在不干擾後續命令發出的情形下保證特定交易的完成順序。熟悉本門技術當可了解，前文參照圖6A-6B及7所述之屬性類似於加速圖形埠（Acceierated Graphics port ;簡稱 AGP)標準之能力，該AGP標準是—種主要用於個人電腦 -17- 本紙張尺度適用中國國家橾準（CNS ) Λ4規格（2丨0X 297公釐） (詩先閱讀背面之注意事項再填寫本頁) -—^ϋ —m · ·I----袈-------—ITl---- 經濟部中央標準局員工消费合作社印製When a balanced load is provided above, different resistors, Ry, and Rz may be used. Please refer to FIGS. 6A and 6B. The figure shows an enhanced PCI according to a preferred embodiment of the present invention. Timing chart of the data timing control mechanism used in the bus. As shown in FIG. 6A, an enhanced PCI bus according to the preferred embodiment of the present invention can support timing control of data with two edges of the clock CLK. The duration of the data (602) on the address / data signal line AD will then be only half of the clock period, while supporting a higher data transfer rate. __ -15- This paper (CNS) is from the secret (21GX297). ----——- Please read the back of the page and then fill in this page. Binding Printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 4 63 09 6 Α7 Β7 经Printed by the Consumers' Cooperative of the Central Bureau of Standards of the Ministry of Industry 5. Invention Description (13 All devices on the enhanced PCI bus must support this option in order to perform timing control of the data on the bus with two clock edges. It is determined when the configuration is set that the device support function of this kind of feature, and the enhanced PCI bus works accordingly. As shown in FIG. 6B, an enhanced PCI bus according to a preferred embodiment of the present invention can also support sources Synchronous data timing control, where the data source provides a strobe pulse signal STRB for data timing control. The target device then uses the data strobe pulse STRB (non-clock CLK) to distinguish the data phase. When two clocks are used When the wave edge is used for timing control of the data, the data strobe signal STRB can use the same frequency (but different phases) as the clock signal CLK shown, or the data strobe signal STRB can A higher frequency is used, but it is better to use an integer multiple of the clock frequency, such as twice the CLK frequency. An enhanced PCI bus according to a preferred embodiment of the present invention can be based on data segments (not based on data Phase) to support data segmentation, or data flow control. Several clock cycles determine the data segment, and the data segment is an aligned 32-byte. The transmission length is segmented into fixed-length 32-byte Segments. When using optional data segmentation, data transfer must begin at the beginning of data transfer of the minimum segment size of 32 bytes and must be an integer multiple of the minimum segment size. When data When the last segment of the transfer is less than 32 bytes, the data transfer is handled in a normal non-segmented manner. When the data is segmented, a faster data transfer and a priority setting of the data transfer can be set. An enhanced PCI bus according to a preferred embodiment of the present invention can support ____ ____-16-a paper rule. Applicable (please read the precautions on the back before filling this page) II ---, r- ---: 1111-- ------- 4 63 09 6 A7 __________B7 V. Description of the invention (14) Speed or flow rate control after the target device or Wang control device is placed in the s_sector and data transfer, and additional waiting is inserted Wait state. When optional data segmentation is used, speed is only allowed between data segments. When data segmentation is not used, it can be allowed between normal data transfers. Now referring to FIG. 7, an enhanced PCI bus according to a preferred embodiment of the present invention can support split transactions, wherein the requirement for data transfer is separated from the data transaction itself. The read request for a split transaction contains a token that uniquely identifies the read request. The address (704) of a data transaction can be separated from the data (706) of the transaction. The intervening clock cycle may include the transmission of a single bit address (708) for different transactions. Similarly, the address (708) and data (710) of a transaction can be separated from the data (708) of a different transaction. It can support split transactions in the case where both devices comply with the enhanced PCI. Standard, or it can be used without split transactions, such as when using an enhanced PCI / traditional PCI bridge. In addition to the above-mentioned data timing control and data transfer mechanism, the enhanced PCI bus of the present invention can also support synchronization commands. A synchronization command ' can be defined and used to keep the rest of the system informed of enhanced PCI transactions so that synchronization events can be monitored. Similarly, a sort order can be defined and adopted to ensure the order of completion of a particular transaction without interfering with subsequent orders. When you are familiar with this technology, you can understand that the attributes described earlier with reference to Figures 6A-6B and 7 are similar to the capabilities of the Acceierated Graphics Port (AGP) standard. The AGP standard is a type of PC-17 -This paper size is applicable to China National Standard (CNS) Λ4 specification (2 丨 0X 297 mm) (Read the notes on the back of the poem before filling this page) -—— ^ ϋ —m · · I ---- 袈- ------— ITl ---- Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs

4 63 09 6 第871050〇8號專利申請案中文說明書修正頁（9〇年6月）五、發明説明（15 ) 業的低階到中階圖形之圖形延伸標準。^而，本發明之辦強型PCI匯流排並不是作為只針對圖形介面卡而實施^ 二，有限延件或強化（係經由只用於圖形介面卡的邊頻帶知號而實現為點對點連接的PCI)，而是可讓多個匯流排王控裝置或目標裝置具有相同的能力。此外，熟悉本門技術者當可了解，上述屬性並不完全相同於可經由根據本明的增強型PCI匯流排而得到的所有效益或屬性。本發月之拓強型pCI匯流排提供了一種用於資料處理系統的較南效能且多分支之一般.用途1/0匯流排。該增強型PCI匯流排可根據工作頻率，而可獲致四傭或更多個插槽的所支援介面卡插槽數一個採用錢信號傳送的増強型PCI匯流排可達到的頻率超過了 2〇〇百萬赫。可以採用較少介面卡插槽的方式，獲致較高的工作頻率，這是一種相互的取捨。在本發明下，—個採用差動信號傳送及以兩個時脈波緣進行資料時隸制的增㈣PCI匯流排可達到的尖峰資料傳輸速率為：對於使用至少為2GG百萬赫頻率的3 2位元資料匯流排而言，所能速率為每…位元組或更高。因為亦可支料區間谷許有配速之分割交易及可選擇的資料區段化’所以本發明之増強型pci匯流排所能獲致的資料傳輸率鬲於只能經由増加頻率而獲致的資料傳輸率。雖然已^參照—較佳實施例而詳細示出並說明了本發月仁〃疋熟悉本門技術者當可了解，在不脫離本發明的精神及範園下，尚可對本發明之形式及細節作出各種改變。 -18- 本紙張尺度適用中關家標準（CNS ) M規格（2獻297公幻 (請先閲讀背面之注意事項再填寫本頁) :裝. -訂· 經濟部中央橾準局貝工消費合作社印聚修正| 補Μ 4 63 096 第87105008號專利申請案中文說明書修正頁（90年6月） A7 B7 ，年‘月产日經濟部中央標準局員工消費合作社印製五、發明説明（15a) 元件符號說明 100資料處理系統 404輸入端/輸出端 102處理器 406輸入端/輸出端 104處理器 407信號傳送網 106區域記憶體 408單端至差動驅動器 108系統匯流排 410a-410b差動信號線對 110主橋接器 412接收器 112 PCI匯流排 414第二驅動器 114主橋接器 40接收器 116 PCI匯流排 418收發器 117a-l 17η至少一個PCI介面卡 420收發器 120擴充匯流排 502信號傳送網 122鍵盤/滑鼠介面卡 504輸入端.. 124裝置介面卡 506驅動器 126整合式傳統PCI支援 508a-508b差動信號線對 128傳統PCI匯流排 510接收器 202信號線 512輸出端 204信號線 602資料 206接地 704位址 208電磁場 706資料 210a-210b差動信號線對 708位址 212a-212b差動信號線對 710資料 310電磁場 Rl，R2，R3終端電阻 312a-312b信號接腳對 CLK時鐘信號 314a-314b信號接腳對 AD位址/資料 402信號傳送網 STRB資料選通脈衝 -18a- (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐）訂·4 63 09 6 Patent Application No. 871050〇8 Chinese Manual Correction Page (June 90) V. Description of Invention (15) Graphic extension standard for low-to-medium-level graphics in the industry. ^ However, the strong PCI bus of the present invention is not implemented as a graphics interface card only. 2. Limited extensions or enhancements (implemented as point-to-point connections via the sideband identification number used only for graphics interface cards). PCI), but allows multiple bus king control devices or target devices to have the same capabilities. In addition, those skilled in the art will understand that the above attributes are not exactly the same as all benefits or attributes that can be obtained via the enhanced PCI bus according to the present invention. This month's top-of-the-line pCI bus provides a more efficient and multi-branch general purpose 1/0 bus for data processing systems. The enhanced PCI bus can obtain the number of supported interface card slots for four commissions or more slots according to the operating frequency. A stubborn PCI bus with a money signal transmission can reach a frequency exceeding 2. 0 Megahertz. It is possible to achieve a higher working frequency by using fewer interface card slots, which is a mutual choice. Under the present invention, the peak data transmission rate of an augmented PCI bus that is controlled by differential signal transmission and data with two clock edges is: for the 3 using the frequency of at least 2GG megahertz For a 2-bit data bus, the rate can be per byte or higher. Because it can also be divided into transactions with a speed range and optional data segmentation, the data transmission rate obtained by the stubby PCI bus of the present invention can be obtained only by increasing the frequency. Transmission rate. Although it has been shown and explained in detail with reference to the preferred embodiment, those skilled in the art will understand that without departing from the spirit and scope of the present invention, the form and Various changes made in details. -18- This paper size applies the Zhongguanjia Standard (CNS) M specification (2 offering 297 public magic (please read the precautions on the back before filling this page): Packing.-Order · Consumption by the Central Bureau of the Ministry of Economic Affairs Amendment to Cooperative Cooperatives | Supplement M 4 63 096 Patent Application No. 87105008 Revised Chinese Specification Sheet (June 90) A7 B7, printed by employees' cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs, Japan, Japan, Japan, Japan, Japan, Japan, Japan and Japan. ) Component symbol description 100 data processing system 404 input / output 102 processor 406 input / output 104 processor 407 signal transmission network 106 area memory 408 single-ended to differential driver 108 system bus 410a-410b differential Signal line pair 110 main bridge 412 receiver 112 PCI bus 414 second driver 114 main bridge 40 receiver 116 PCI bus 418 transceiver 117a-l 17η at least one PCI interface card 420 transceiver 120 expansion bus 502 signal Transmission network 122 keyboard / mouse interface card 504 input terminal: 124 device interface card 506 driver 126 integrated traditional PCI support 508a-508b differential signal line pair 128 traditional PCI bus 510 connection Device 202 signal line 512 output 204 signal line 602 data 206 ground 704 address 208 electromagnetic field 706 data 210a-210b differential signal line pair 708 address 212a-212b differential signal line pair 710 data 310 electromagnetic field Rl, R2, R3 terminal Resistor 312a-312b signal pin to CLK clock signal 314a-314b signal pin to AD address / data 402 signal transmission network STRB data strobe pulse -18a- (Please read the precautions on the back before filling this page) This paper Standards are applicable to China National Standard (CNS) Α4 specifications (210X297 mm).

Claims

No. 1059 ^ Patent Application for Chinese Patent Application for Amendment of Patent Scope (June 90) g88 A8 B8

Scope of patent application Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economics 1. A method for enhancing the performance of a PCI bus in a data processing system, including the following steps: providing two bus conductors for each PCI signal; and Wait for each bus conductor of the two bus conductors to use differential signal transmission, wherein the performance of the PCI bus is enhanced. For example, the method of applying for the first item of the patent scope also includes the following steps: Route the two bus conductors of each PCI signal to adjacent places on a circuit board, where the selection of the circuit board can be a master Sheep board or an additional interface card. -€ 3. The method according to item 1 of the patent application range, wherein the step of using differential signal transmission between each of the two bus conductors comprises the following steps: Transmitting a signal in a first state with a voltage difference in a first direction between the two bus conductors; and transmitting a second signal using the voltage difference in a second direction between the two bus conductors Signal of status. 4. The method of claim 1 in the scope of patent application, wherein the step of using differential signal transmission between each of the two bus conductors includes the following steps: A signal of a first state is transmitted between the bus conductors with a first amount of voltage; and a signal of a second state is transmitted using a voltage difference between the two bus conductors with a second amount. 5. If the method of applying for the first item of the patent scope, it also includes the following steps: Repair troubles, please ο Kui Wei 2 · fgui Wuming change six more> I if I am referring to the Japanese repair institute. The paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the notes on the back before filling out this page.) 4 630- Ό Α8 Β8 C8 D8 Ministry of Economic Affairs Central Standardization Bureau Off-line Consumer Cooperative The scope of printing and patent application provides at least one driver for this increase. 6. If the patent application scope provides at least one receiver, the augmentation. 7. If the patent application scope provides the enhanced segmentation. 8. If you apply for a patent, speed up / enforce the enhanced type. 9. If the patent is applied for the enhancement, it supports segmentation of data. 10. If the patent is applied for the enhancement, synchronize the command. u. If the patent application is for the enhancement order β 12 · If the patent application is for the enhancement,. 13. If applying for a patent

This device is connected to a PCI bus with a differential type. The method around item 1 further includes the following steps: devices connected to a PCI bus with a high dynamics. The method around item 1 includes the following steps: The method of enforcing the data area of each data transaction on the PCI bus-item 1 also includes the following steps: The data transfer between the data segments on the PCI bus The method of item 1 also includes the following steps: Each pipeline reads transactions on the PCI bus and trades. The method surrounding item 1 also includes the following steps: A data transaction on a type PCI bus and using the method of item 1 includes the following steps: A data transaction on a type PCI bus using a condition The method of item 1 also includes the following steps: The method of using a PCI bus with a length longer than about 10 feet around the item 1 also includes the following steps: -2 v degree Common Chinese Goods Standard (CNS) A4 specification (210X297 (Mm) (Please read the notes on the back and fill in this card) Order 9 3 6 4 ABCD

Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 6. Scope of patent application Connect at least four interface card slots to this enhanced PCI bus. 14. A device for enhancing the performance of a PCI bus in a data processing system, comprising: a connection component for providing two bus conductors to each PCI signal; and a signal transmission component for connecting the two Differential signal transmission is used between the bus conductors, wherein the performance of the PCI bus is enhanced. 15. The device according to item 14 of the patent application, wherein the connection assembly further comprises: a bus conductor wiring connection assembly, which is used to route the two bus conductors of each PCI signal to each other on a circuit board. Nearby. 16. For the device under the scope of patent application item 14, the signal transmission component further includes: a component for transmitting a first status signal, and the component for transmitting the first status signal uses a first component between the two bus conductors. A voltage difference in one direction to transmit a signal in a first state; and a component to transmit a second state signal, the component in transmitting the second state signal uses the signal along a second direction between the two bus conductors. The voltage difference transmits a signal in a second state. 17. For the device in the scope of claim 14, the signal transmission component further includes: a component for transmitting a first status signal, and the component for transmitting the first status signal is used between the two bus conductors and has a first A voltage difference of one quantity is used to transmit a signal of a first state; and -3- This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) --------- ^, — 4 — (Please read the notes on the back before filling in this page) Order 4 63 ⑽ ',. --- ~ --7, patent application scope ABCD e month Ι 4 The Ministry of Economic Affairs Central Ministry of Economic Affairs employee consumer cooperation prints Yundi 2 The component of the status signal, which transmits the second bear component using the voltage difference between the two bus conductors to transmit the second status signal. 1 18. For example, please refer to the device in the scope of patent No. 14 and also include: a component for providing a device for providing connection to a child-enhanced PCI bus with differential driving assistance. Several devices. 19. The device according to item 14 of claim 2, further comprising: a component for providing a device for providing a plurality of devices connected to the enhanced PCI bus having a plurality of consumers. 20. The device according to item 14 of the scope of patent application, further comprising: a data segmentation component 'for performing data segmentation on each data transaction on the enhanced m bus. 1. If the device in the scope of application for patent No. 14 further includes: a data transaction speeding component, which is used to perform speeding on data transactions between data sections on the enhanced PCI bus. 2. The equipment of item 14 in the scope of the patent application also includes: for the enhanced PC; [a pipelined read transaction on the bus and a component that supports split data transactions. 23. The device in the scope of application for patent No. 14 further includes: a component that uses a synchronization command for a data transaction on the stubborn PCI bus. 24. If the device under the scope of patent application (1), it also includes: A component that uses a bank order for a data transaction on the enhanced PCI bus β -4-Chinese National Standard (CNS) Α4 ^ (210X297) (%) (Please read the notes on the back before filling this page) 1%-Order A8 —-----, _ Λίζ ~ ίγ '(D B8 C8 > year (month 5 ^ amendment D8 supplement, patent application scope 25 · = Apparatus No. 14 in the scope of patent application, in which the connection component uses a slow wire longer than 丨 0 feet for stubborn PCI buses and buses. 26 · If patent is applied. Apparatus in scope No. i 4 The connection assembly further includes: at least four interface card slots connected to the enhanced PCI bus. 27 · —An enhanced PCI bus in a data processing system, which is included in the data processing system. Differential drivers in a PCI main bridge; several differential receivers in an interface card in the shell processing system; and a plurality of differential drivers connected to the differential receivers Conductor pair Both carry signals of the same voltage, but carry these signals in the opposite direction. The data processing system includes an enhanced PCI bus that can perform high-frequency and high-bandwidth operations. The enhanced PCI bus of item 27 further includes: a plurality of differential receivers in the #HAIPCI main bridge; and a plurality of differential drivers in the interface card, wherein the plurality of conductor pairs connect the PCI main The differential receivers in the bridge are connected to the differential drivers in the interface card. 29. If _ please patent the enhanced PCI bus of item 27 of the patent, where the differential drivers include: A logic circuit that supports split data transactions for each pipelined read transaction on the enhanced PCI bus. -5- This paper size uses the Chinese National Standard (CNS) A4 specification (210X297 public director) (Please read first Note on the back, please fill out this page again) i " Printed by the Consumers' Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 4 63 03 6 Scope of patent application 30. For example, the enhanced PCI sink of the scope of patent application No. 27 Row, where these differential drives also include: logic circuits that support data segmentation for each data transaction on this enhanced PCI bus. (Please read the precautions on the back before filling this page) ¥, βτ The paper size of the printed paper of the employees' cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs adopts the Chinese National Standard (CNS) Α4 specification (210X297 mm)