TW461031B - Method for producing isolation trench - Google Patents

Abstract

A method for producing isolation trench comprises forming a first layer on a semiconductor substrate, patterning the first layer to form an insulator island to protect active areas in the semiconductor substrate, forming a second layer on the insulator island and the other part of the substrate, anisotropic etching the second layer to form spacer on the side walls of the insulator island, thermally treating the substrate to form thermal oxide mask at areas not covered by the insulator island and side wall spacers, removing selectively the side wall spacers to expose the substrate between insulator island and thermal oxide, and etching the exposed substrate to form an isolation trench using insulator island and thermal oxide as masks. The width of the isolation trench produced is not limited by the resolution of photolithography process.

Description

461031

The characters are related to V. Description of the invention (1) The present invention is related to a method of making a trench structure in a semiconductor substrate. When the integration of integrated circuits is increasing, and-strains. More. Fine. How to reduce the structure used to isolate the main frame also becomes the isolation area, which becomes more and more important. The isolation area that is opened between the two transistors such as the transistor will determine the active area: (the one by one's need to reduce the silicon area oxidation method (10c0s) is widely used in The isolation area is made by lightning. The manufacturing process of L0C0S is very simple, but in the ancient second component such as 256 MB DRAM device, when the impurity F a accumulates -r ^ ^ m ^ ^ The field width is reduced. Time 'may cause punchthough because of "bird, beak" formed during the oxidation process. This will reduce the f-degree of the field oxide' and reduce the size of the active area . Another conventional method is to use trenches as the isolation method. In this method, a trench is formed on the integrated circuit component, and the trench is filled with an insulating material such as an oxide. In order to form a smaller isolation area than those using the L0C0S method. Furthermore, both the problems of the L0C0S method and the problems caused by the thermal oxidation method can be controlled by the trench isolation method.

Trench Isolation Process for Deep Submicron DRAMs, IEDM Tech. Digest, pp. 57-60, 1993, by P. Fazann et al., In which a pad oxide layer and a silicon nitride layer are formed on a substrate of a integrated circuit And patterned. Next, the patterned silicon nitride layer and the pad oxide layer are used as a mask to etch the integrated circuit substrate to

0516-5661TWF-ptd Page 4 461031 V. Description of Invention (2) --- Form a trench. The sidewall of the trench is then thermally oxidized 'and an oxide layer is formed in the trench by chemical vapor deposition. The chemical oxide polishing (CMP) is performed to planarize the oxide layer. Next, the silicon nitride layer is removed, and a spacer is formed on the sidewall of the oxide f. Finally, the pad oxide layer is wet-etched to complete an isolation layer, and a gate oxide layer and a gate electrode are formed. For the microelectronics industry, in order to shrink electronic components, making more electronic components on one die 'must use an isolation trench (— "ο: Two. However, according to the conventional trench isolation method, the isolation area = The reduction of the width is limited by the lithography resolution. Therefore, if the width of the isolated area can be reduced, it will no longer be limited by the resolution of the operation, which will be a major advancement in this technology. In view of this, the purpose of the present invention is to provide a method for making isolation = so that the width of the isolation trench is not limited by the lithography resolution. In order to achieve the above purpose, the present invention provides a production isolation The trench structure method forms a first layer on the material, and the first 22 layers pattern the dielectric layer to form an island of insulation (Insulat〇r Island) to protect half of Mozambique taxis. ^ Active area in the conductor substrate. Connected to the clip, less insulation islands and other parts of the substrate form an " non-isotropic ㈣ ... second layer 'and form heat on the location of this second layer Oxide cover . ',, = /, side spacers rear cover soil ,,,' is selectively removed between the sidewall Bu Gu Ken Jie a rancid both a "& _ & in ten thousand to one hundred first conductor group oxidized at + Cloth

〇516-5661TWF'Ptd Page 5 4 6 1031 Five 'invention description (3), 5 to expose the substrate between the island and the thermal oxide mask. An insulating oxide mask was used as the mask to etch the isolation trenches on the exposed substrate. According to the invention, because the width of the trench is sacrificed by the width of the spacer: 22; resolution of the lithography, so the isolation trench can be made narrower without being restricted by the lithography example.眚: Second, a schematic embodiment of a method for manufacturing an isolation trench according to the present invention will be illustrated. Brief Description of the Drawings The second isolation diagram is a cross-sectional view illustrating the trench separation method according to an embodiment of the present invention. Example A SU1 / 9 diagram is prepared, which shows a method of first leaving an area in the method according to the embodiment of the present invention. As shown in FIG. 1, the method of the present invention includes a shape material 1 = t material 10. In this manual, "" Si substrate "is round! The components and layers covered on the wafer, such as the surface soil and insulation layer of Shixi, include the uppermost layer exposed on the Shixi wafer. For example, a first layer is formed on the semiconductor substrate 10. «Eight: Layers, 'for example-oxide layers. Next, use Figure 1 and: Λ isotropic etching to selectively remove a portion of the first layer: to protect the non-semiconducting insulator Mishima II during formation. (Zhongji Erdao) 2 can be used in subsequent isolation trenches (i) in part of the active area (not shown). Read the second picture in April, and form sidewall spacers on the side walls of the insulation 1 9 AA know '' island 1 2

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° A second layer is deposited on the exposed portions of the insulating island 12 and the substrate ι. J. Use an electrically destroyed neodymium etch to perform anisotropic engraving on the second layer, and j widely expose the surface of the substrate. As a result, the remaining portion of the second layer forms a sidewall spacer 14 on the sidewall of the insulating island 12 3. The above-mentioned second layer can be formed by a method such as plasma enhanced chemical vapor deposition (PECVD) for depositing a nitride, such as non-standard fossils. If the sidewall spacer 丄 4 is formed of a nitride, the insulating island ^ is formed of a different material such as an oxide. The use of essentially different materials makes it easier to selectively remove the spacers 14 (as described in conjunction with Figure 4). Referring to FIG. 3, after the spacer 14 is formed, the oxide mask a is formed on the other portion of the substrate 10. It can be fabricated by thermally oxidizing the silicon substrate ι to form an oxide mask 16 at a location not covered by the insulating island 2 and the side wall spacers 4. After the oxide mask 16 is formed, the sidewall spacers 4 and 4 are selectively removed so as to expose the substrate between the insulating island 12 and the oxide mask 16 as shown in FIG. 4. The method is to use a wet etch or a dry etch to selectively remove the rhenium spacers 14, such as the nitride spacers, relative to the insulating island 12 and the oxide mask 16. In order to make the etching more consistent, the insulating island 12 and the oxide mask 16 are preferably formed of the same material. Please refer to FIG. 5, and then use the insulating island 12 and the oxide mask 16 as the engraved mask to perform anisotropic etching on the substrate 10 so as to form at least one trench 18. When having a width w. For isolation of trenches, use the _gen touch-based processing program (halogen_based | etch recipe), which can be used to select insulation islands 12 and oxide masks 16

4 6 1 0 3 1 V. Description of the invention (5) A single etching process program is completed. As mentioned above, it is clear that the trench width w is determined by the vertical space of the spacer 14, and the vertical space of the spacer 14 is determined by the thickness of the second layer forming the spacer, not by the lithography. The resolution of the operation. Therefore, the trench width W can be reduced by reducing the thickness of the second layer without being limited by lithography. Thus, the isolation trench 18 of the present invention can be made narrower, and the active area formed in the substrate can be made wider. Please refer to Figure 6 'Insulation Island 12 and Oxide Mask 16. Oxide stone etching solution can be used, such as buffered oxide solution (buffered 〇x 丨 de etchant' BOE) or hydrotonic acid (HF ) To remove. Referring to FIG. 7, an insulating layer 20 having a predetermined thickness is formed on a substrate 10 having a trench 18, and the trench is buried. The above-mentioned insulating layer 20 may be formed of undoped silicon glass (USG) by a chemical vapor deposition method using a two-density plasma. Alternatively, if the insulating island 12 is formed of silicon oxide, the insulating island 2 and the oxide mask 6 may be planarized and removed before or after the insulating layer 20 is formed. According to another feature of the present invention, before the insulating layer 20 is formed, 埶 with a thickness of about 50-20 mm can be formed on the entire surface of the substrate 10 (not shown in the figure). The thermal oxide layer can remove defects and stresses that may be generated in the substrate 10 during the formation of trenches and during the post-polymerization process. Please refer to Fig. 8. Next, a dry etch back (CMP) step can be used to flatten the insulation layer 20. ^ Dryer G

461031 Jade, description of the invention (6) The isolation area 22 of the trench 18 is buried. FIG. 9 shows a step for selectively etching the surface 10 of the semiconductor substrate to make the substrate concave. It uses wet etching to use an etching solution that can only etch the substrate, such as a mixed solution of ammonium fluoride (Nh4F) and hydrofluoric acid, to selectively etch the substrate 10 to a predetermined depth. Thus, the surface of the substrate 10a is recessed below the surface of the isolation region 22. A step is formed between the substrate and the isolation area. Carrying out the remainder of the substrate helps to eliminate the stress generated during the CMP, while also removing defects and / or the slurry particles used in the CMP process. Although the present invention has been disclosed as above with a preferred embodiment, Rigan = invention 'anyone skilled in this art, without departing from: the spirit of the invention π consumption range, when you can make a few changes and maintenance, protection range should be Subject to the scope of the attached patent application. Invention guarantee

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Claims (1)

461031 VI. Patent Application Scope— 1. A method for making an isolation trench structure on a semiconductor substrate 1 includes the following steps: Method, forming a first layer on the semiconductor substrate; patterning the first layer 'To form an island on the substrate; to form a spacer on the side wall of the island; to thermally oxidize the substrate to form an oxide mask at a location not covered by the island and the spacer; R Remove the sidewall spacers to expose the substrate between the island and the oxide mask; and use the island and the oxide mask as a mask to etch the exposed substrate to form a trench. 2 The method according to item 1 in the scope of patent application, wherein 'the first layer is a dielectric layer. 3. The method according to item 2 in the scope of patent application, wherein' the first layer is an oxide layer. 4. The method according to item 1 of the scope of patent application, wherein the step of forming the spacer includes the following steps: forming a second layer on the substrate and the island; and anisotropically etching back the second layer 5 'Method as described in item 4 of the scope of patent application , Where the 'second layer is formed of a material branch that is substantially different from the first layer. 6. The method described in item 5 of the scope of the patent application, wherein' the second layer is formed of a nitride stone. 7. The method described in item 1 of the scope of patent application, wherein 'in the above Q516-5661TWF-Md After the step of etching the trench, the following steps are performed: ^ forming an insulating layer in the trench; and flattening the insulating layer described in 71 to form an isolation region in the trench. 8. The method according to item 7 of the scope of patent application, wherein before the step of forming an insulating layer in the trench, perform the following steps: Remove the island and the oxide mask from the substrate. 9. The method according to item 7 of the scope of patent application, wherein, after the step of planarizing the above-mentioned insulating layer, the following steps are performed: the substrate is engraved to form a recess 10 on the substrate with respect to the isolation region. A method for fabricating an isolation trench structure on a semiconductor substrate, including the following steps: forming an oxide layer on the semiconductor substrate; patterning the oxide layer to form an oxide island on the substrate; Silicon nitride spacers are formed on the sidewalls of the islands; the substrate is thermally oxidized to cover the oxide mask without the islands and the spacers; and the sidewalls are selectively removed to expose the islands and the oxides A substrate between the spacers; and using the oxide island and the oxide as the substrate to form a trench. Worm exposure 11. The method as described in claim 10 of the patent application, wherein after the step of etching the trench, the following steps are performed: forming an insulating layer in the trench; and 0516-5661TWF'ptd VI. Patent Application Fan Park The above insulating layer is planarized to form an isolation area in the trench. 1 2 · The method as described in item 11 of the patent application scope, wherein before the step of forming an insulating layer in the trench, perform the following steps: Remove the island and the oxide mask from the substrate. 1 3. The method according to item 11 of the scope of patent application, wherein after the step of flattening the above-mentioned insulating layer, the following steps are performed: The remaining substrate is used to form four places on the substrate with respect to the isolation region. 0516-5661TWF'ptd Page 12