TW460969B - A method for reducing the cracks resulted from CMP of low-K material - Google Patents

Abstract

The present invention provides a method for reducing the cracks resulted from CMP of low-K material comprising the following steps: forming a low-K material layer on the rough surface on the semiconductor substrate; remove part of the low-K dielectric layer to form an opening in the low-K dielectric layer; forming a metal film on the low-K dielectric layer, and fill into the opening; polishing the metal film by CMP to form metal lines; and etching back the low-K dielectric layer by plasma etching back technique without O2 to remove the micro-scratch and reduce dishing and erosion structures on the surface of the low-k dielectric layer and metal lines.

Description

4 6 Ο 9 6 9 V. Description of the invention (1) Field of the invention: The present invention relates to a method for reducing cracks generated by chemical mechanical polishing, especially a method for reducing cracks generated by chemical mechanical polishing of low dielectric constant materials. Background of the Invention: With the advancement of semiconductor technology, 'interlayer dielectric layers (eg, Inter-Mediate Dielectrics' IMD) in the current CMOS process are usually smaller in dielectric constant than oxides. The low dielectric constant (1 ow-k) materials (such as Si LK, FLARE, black diamond, nanoglass, etc.) to replace the original oxide (such as: the dielectric constant of about 3.9 oxidation (Chopped.), In order to reduce the coupling capacitance between the metal interconnects, so as to reduce the resistance-capacitance hysteresis, because in some processes (such as: single copper damascene process or double copper damascene process, etc.), use As a low dielectric constant (10wk) material used as an interlayer dielectric layer, it is usually necessary to continue to deposit a film layer thereon, so in order to enable subsequent film layers to be successfully deposited on this low dielectric constant (low-k) ), A flattening process step is usually applied to the low dielectric constant (10wk) material. '· At present, there are two planarization process methods: spin-on glass (spin-on g 1 ass) method and chemical mechanical polishing (chemical mechanical P 0 1 i sh i ng) method. Traditionally use chemical mechanical grinding (chem i ca 1

4 6 096 9 V. Description of the invention (2) Mechanical pol ishing method for flattening low dielectric constant (iwk) materials can refer to "Taiwan Semiconductor Manufacturing Co., Ltd." "王"Mr. Ying Lang" disclosed in the Republic of China Patent Application No. "871141 33" |, a chemical mechanical polishing process with a low dielectric constant soG 丨 丨 "However, due to the low dielectric constant (| ow-k) The hardness and strength of the material are smaller than those of the oxide. When the low-k material is chemically and mechanically ground, the low-k material will easily cause fine seams (mi cro-scratch), discoid (di sh i ng) or eros on (eros i on) structure, etc. This phenomenon will make subsequent film layers can not be deposited smoothly, so if we can solve the problem because of low dielectric When the constant (low-k) material is subjected to chemical-mechanical grinding, such as micro-scratch, dishing, or erosión structure, the subsequent film layers can be successfully deposited on Above this low-k material ............. .... ................. _:. '...... The purpose of the present invention is to perform plasma (P 1 asma) etchback of the low dielectric constant material after chemical mechanical polishing' to remove the low dielectric constant material because Micro-scra1: ch surface and dishing or errosion structures produced by chemical mechanical polishing.

Page 5 460969 V. Description of the invention (3) The method proposed by the present invention includes the following steps: (1) forming a low dielectric constant dielectric layer on the upper surface of a semiconductor substrate to produce an insulating effect. The surface is undulating. (2) Use the lithographic technique to remove part of the low-k dielectric layer to form an opening in the low-k dielectric layer. (3) A metal thin film is formed on the low dielectric constant dielectric layer and filled into the opening. (4) The metal thin film is polished by chemical mechanical polishing (CMP) to form a metal wire. (5) Use plasma etch-back technology to perform silver etch back on the low dielectric constant dielectric layer to remove the micro-scratch on the surface of the low dielectric constant dielectric layer and the metal wire and reduce the disk Phenomena such as fishing or erosion structure, in which the electro-cracking does not contain 02 to prevent the metal film from being oxidized. ...--... Wherein, before forming the above metal thin film, it further comprises forming a barrier layer of materials such as Ta, TaN, TiN, TiW, Ti or any combination thereof in the trench, so as to Diffusion artifacts of the dielectric layer and the semiconductor substrate and the metal thin film are prevented, and the spike effect is caused by the rain. In addition, after forming the barrier layer, it further includes forming a seeding layer 'of the same material as the metal film on the upper surface of the barrier layer to strengthen the adhesion of subsequent electrical bonds. The material of the metal wire includes copper. The method for forming the low dielectric constant dielectric layer includes chemical vapor deposition (CVD) or spin on. The material can be selected from one of the following clusters: Si LK, FLARE, black diamond, nanoglass or Any combination. The above plasma

460969 V. Description of Invention (4)

Contains N2-H2, He-H minus NH3, approximately 2. 6 ~ 3.1, which uses -H Ron NH3 0 and the material of the dielectric constant of the low-dielectric constant dielectric layer is SiLK, then the electrical equipment Contains n. Detailed description of the invention: The purpose of I ^ 发 ^ is to perform plasma (PlaSma) etch-back on the low dielectric constant 151 4 after chemical mechanical polishing to remove low dielectric constant materials. The resulting surface cracks (miCr0_SCratCh) have a dishing or corrosion structure. .. ............................ The method of reducing cracks generated by chemical mechanical polishing of low dielectric constant materials is as follows:..-.... '...';... ^ Refer to the first figure 'Firstly provide a semiconductor substrate 10, where The semiconductor 1 & 10 may be a &lt; 10 0 &gt; or <111 &gt; crystal orientation single crystal silicon or other kind of 10-body material such as gallium arsenide (GaAS), germanium (Ge), etc., and the semiconductor The surface of the substrate is undulating, and various active and passive components, and peripheral circuits required for integrated circuits have been fabricated thereon. A low-k dielectric layer 12 is then formed on the semiconductor substrate 10 to

460969 V. Description of the invention (5) Insulation effect is generated 'then' a contact hole (or trench, contact hole, dielectric hole) is formed on the low dielectric constant dielectric layer 12 by traditional lithography and etching techniques. , Contact / via hole)) to expose the upper surface of the semiconductor substrate 10. Usually, a photoresist can be formed on the low-k dielectric layer 2 first to define a connection hole pattern, and a contact hole is formed on the low-k dielectric layer 12 by performing lithography and etching steps. Then, by using chemical vapor deposition, or physical vapor deposition such as a sputtering process, or electro-chemical method, _ __ • metal (eg, copper) thin films with a low dielectric constant dielectric are formed. Above the layer 12 and filled into the contact hole, the metal thin film is polished by using a chemical mechanical polishing method (C hemica 1 Mechanica 1 P ο 1 ishing; CMP) to form a metal wire 14. Due to the low hardness and strength of the material of the low dielectric constant dielectric layer 12, after the chemical mechanical polishing, the low dielectric constant dielectric layer 12 and the metal wire 14 are easy to produce ... .... Phenomenon of micro-scratch, dishing or erosion structure. ....: '..... Dielectric layer 12 is etched back to remove the low-k dielectric layer 12 and the surface of the metal wire 14.... (Micr 〇- scr at ch) and reduce the disc shape (dishing ) Or erosi (erosi ο η) structure. Here, the plasma contains, for example, Hr He-H2, NH reducing gas (reducing ga s), but it cannot contain 0 2 ', because the metal thin film will be oxidized. In addition, plasma plasma is not limited by the surrounding pressure of the environment in which it is used.

460969 V. Description of the invention ⑹ ~~~ ---- The implementation conditions of plasma etchback are related to the material of the low dielectric constant dielectric layer. For example, if the low dielectric constant dielectric layer 12 is used as = SiLK 'is better for plasma etch back using LH and NH beds. These materials include the above-mentioned metal thin film, which further includes a barrier layer such as τ TaN, TiN, TiW, Ti, or any combination thereof before forming the cover film. U, said to prevent the dielectric layer, semiconductor substrate, and metal thin film from occurring. The "diffusion" phenomenon, and M has a spiking effect. In addition, after the barrier layer is formed, it also includes forming an alpha seed layer (seeding layer O ') of the same material as the metal film on the upper surface of the barrier layer to strengthen subsequent plating Adhesiveness. Wherein, the material of the above-mentioned metal wire 14 includes copper. The method for forming the low-level eight layer 12 includes chemical vapor deposition (CVD) or spin-on (sp in on), and the material can be selected from One of the following clusters: 'SiLK, FLARE, black diamond, nan0glas ^ any combination thereof. Now taking another preferred embodiment as an example, a detailed description will be given of the mechanical reduction of the low-k dielectric material of the present invention. The method of cracking is as follows: Reduction * ---.-. '....... -..... ....... Base 30, 1 The main base 30 may be a <! 〇〇 &gt; or &lt; 11 & gt Single crystal n + conducting f conductor material in crystal orientation, such as gallium arsenide (GaAs), germanium (Ge), etc., and various semiconductor circuits required for integrated circuits have been fabricated on the semiconducting circuit. And so on. Λ ^ Breaking το pieces, and weeks

460969 V. Description of the invention (7) '-Of course, a dielectric layer 32 is formed on the semiconductor substrate 30 to produce an insulating effect. Next, the conventional lithography etching technique is used to form a contact hole 'on the dielectric layer 32 and a conductive plug 3 is formed by using a chemical vapor deposition method or a physical vapor deposition method such as a sputtering process. In the hole. Subsequently, 'form a low dielectric constant dielectric layer 36 on top of the dielectric substrate 32 and the conductive plug 3 4', and then use lithography and etching techniques to form trenches in the low dielectric constant dielectric layer 36. To expose part of the upper surface of the conductive 'plug 34'. Next, a chemical vapor deposition method, or a physical vapor deposition method such as a sputtering process, or an electroplating method is used to 'form a metal (eg, copper) film on the low dielectric constant dielectric layer 36' and fill in In the trench, the metal thin film is then polished by chemical mechanical polishing (CMP) to form a metal wire 40. Due to the low hardness and strength of the material of the low dielectric constant dielectric layer 36, micro-scratch and disk-like shapes are easily generated in the low dielectric constant dielectric layer 36 and the metal wire 40 after chemical mechanical polishing. (Dishing) or corrosion (errosion) structure. ................, Please refer to the fourth figure 'Using plasma etch-back technology to describe the low-k dielectric layer 3 6 Carry back the last name to remove the micro-scratch on the surface of the low-dielectric constant 1 electrical layer 36 and the metal wire 40 and reduce the phenomenon of dishing or erosion structure ... Electrical destruction includes: N2-H2, He-H2, NH # reducing gas (reducing gas)

4 6 0 9 6 9 V. Description of the invention (8) gas), but 02 cannot be included because the metal film will be oxidized. In addition, plasma etchback is not limited to the surrounding pressure of the environment in which it is used. The implementation conditions of the plasma etchback are related to the material used for the low dielectric constant dielectric layer 36. For example, if the material used for the low dielectric constant dielectric layer 36 is Si LK, then N 2- It is better to use the Nong Nong to perform the electric name return. Wherein, before forming the metal thin film, it further includes a forming material such as Ta,

The barrier layer of TaN, TiN, TiW, Ti, or any combination thereof is in the trench to prevent the dielectric layer, the semiconductor substrate and the metal film from diffusing, and a spike effect (s p i k i n g e f f e c t) occurs. In addition, after the barrier layer is formed, the formation of a seed layer (s e e d i n g 1 a y e r) of the same material as the metal thin film on the upper surface of the barrier layer is further included to strengthen the adhesion of the subsequent power ore. The material of the metal wire 40 includes copper. The method for forming the low-k dielectric layer 36 includes chemical vapor deposition (CVD) or spin coating (sp i n on), and the material can be selected from one of the following clusters:

SiLK, FLARE, black diamond, nanoglass or any combination thereof. As for the material of the dielectric layer 32, nitride is included. The above description is only the preferred embodiments of the present invention, and is not intended to limit the scope of the patent application of the present invention; any other equivalent changes or modifications made without departing from the spirit disclosed by the present invention should be It is regarded as the protection scope of the present invention. The scope of patent protection of the present invention should be determined by the scope of the attached patent application and its equivalent fields.

46〇969 Brief description of the drawings Using the following description and the combination of the following drawings, the content and advantages of the present invention can be more clearly understood, where: The first diagram is a cross-sectional view of a semiconductor wafer, showing an embodiment according to the present invention A step of sequentially forming a low dielectric constant dielectric layer with a contact hole, a metal thin film on a semiconductor substrate, and then polishing the metal thin film with a chemical mechanical polishing method (Chemical Mechanical Polishing; CMP) to form a metal wire; The figure is a cross-sectional view of a semiconductor wafer, showing the use of plasma etch-back technology to perform an electrical masking #etching on a low dielectric constant dielectric layer according to an embodiment of the present invention to remove the low dielectric constant dielectric layer. The step of mi cro-scrat ch on the surface; the third figure is a cross-sectional view of a semiconductor wafer, showing a low dielectric constant dielectric with contact holes is sequentially formed on a semiconductor substrate according to another embodiment of the present invention Layer, metal thin film, and then use the mechanical mechanical polishing method (Chemical Mechanical Polishing; CMP) to the metal thin film-grinding 'to form the metal wire And the fourth row is a cross-sectional view of a semiconductor wafer, which shows that a low-dielectric layer is subjected to plasma etch-back using a plasma rebate technique according to an embodiment of the present invention to remove the low-dielectric layer. Step of permittivity dielectric mire 0-scratch. Part number of a face:

4 6 096 9 Schematic illustration of semiconductor substrate 10; low dielectric constant dielectric layer 12; metal wire 14; semiconductor substrate 30; dielectric layer 32; conductive plug 34; low dielectric constant dielectric layer 36; metal Wire 4 0.

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Claims (1)

460969. Sixth, the scope of patent application 1. A method for reducing cracks generated by chemical mechanical polishing of a low dielectric constant material, the method includes at least the following steps: forming a low dielectric constant of about 2.6 to 3.1 The dielectric layer is on the upper surface of a conductive plug to generate insulation, wherein the conductive plug is located in the dielectric layer of a semiconductor substrate; using a lithographic etching technique, a portion directly above the conductive plug is removed. A low dielectric constant dielectric layer to form an opening and expose a part of the upper surface of the conductive plug; forming a metal film on the low dielectric constant dielectric layer and filling the opening; using chemical machinery Grinding (Chemical Mechanical P ο 1 ishing; C M P) grinding the metal thin film to form a metal wire, and using a plasma etch-back technique to etch back the low dielectric constant dielectric layer, In order to remove the micro-scratch on the surface of the low-k dielectric layer and the metal wire, and reduce the phenomenon of dishing or erosion structure. 2. The method according to the first patent application, wherein the material of the metal thin film includes copper. 3. The method according to item 1 of the patent application, wherein before forming the metal thin film, it further comprises forming a barrier layer in the opening to prevent the metal thin film from diffusing with the dielectric layer and the semiconductor substrate, Spike effect Page 14 4 6 0 96 9 VI. Patent application scope should be (spiking effect) 0 4. The method of patent application scope item 1, wherein the above plasma contains N2-H2, He-H2, NH3. 5. The method according to item 1 of the patent application, wherein the material of the above-mentioned low-k dielectric layer can be selected from one of the following clusters: Si LK, FLARE, black diamond, na η og 1 ass, or any combination thereof . 6. The method according to item 1 of the scope of patent application, wherein if the material used for the above-mentioned low-k dielectric layer is SiLK, the electropolymer includes N2_li and NH3. 7. The method according to item 1 of the scope of patent application, wherein the method for forming the above-mentioned low-k dielectric layer includes a chemical vapor deposition method (CVD) or a spin-on method (sp in on). The method according to item 1, wherein the method for forming the metal thin film includes a chemical vapor deposition method, a physical vapor deposition method, or a plating method. 9. The method of claim 3, wherein the material of the barrier layer can be selected from one of the following clusters: Ta, TaN, TiN, TiW, Ti, or any combination thereof. Page 15 460969 VI. Application scope of patent 10. The method of item 3 of the scope of patent application, wherein after forming the barrier layer, it further comprises forming a seeding layer on the upper surface of the barrier layer to Strengthen the adhesion of subsequent keys. 1 1. The method according to item 10 of the scope of patent application, wherein the material of the seed layer includes the same material as the metal thin film. 1 2. A method for reducing cracks generated by chemical mechanical polishing of a low dielectric constant material, the method includes at least the following steps: forming a low dielectric constant dielectric layer on an upper surface of a semiconductor substrate to generate an insulating effect, wherein The surface of the semiconductor substrate is undulating; ′ utilizes a lithographic etching technique to remove a portion of the low dielectric constant dielectric layer to form an opening in the low dielectric constant dielectric layer; forming a metal thin film on the The low-k dielectric layer is filled with the opening; the metal thin film is polished by a chemical mechanical polishing method (Chemical P ο 1 ishing; C M P) to form a metal wire, and a plasma ( plasma) etch-back technology to etch back the low-k dielectric layer to remove the low-k dielectric layer and the metal conductor (micro-scratch on the surface of the wire) and reduce the disk shape ( dishing) or rotted money (er ο si ο η) structure, etc. 1 3, such as the method of claim 12 in the scope of patent application, wherein the above-mentioned metal thin film Page 16 460969 VI. Scope of patent application Material contains copper. 14. The method according to item 12 of the scope of patent application, wherein before forming the metal thin film, it further comprises forming a barrier layer in the opening to prevent the metal thin film from diffusing with the dielectric layer and the semiconductor substrate. Phenomenon, resulting in a spiking effect. 15. The method according to item 12 of the scope of patent application, wherein the above-mentioned plasma contains N 2 -Η 2. 1 6. The method according to item 12 of the patent application, wherein the above-mentioned plasma contains He-H2; 1 7. The method according to item 12 of the patent application, wherein the above-mentioned plasma includes NH3. 1 8. The method according to item 12 of the scope of patent application, wherein the material of the low-k dielectric layer can be selected from one of the following clusters: SiLK, FLARE, black diamond, na η 〇g 1 ass or random combination. 19. The method according to item 12 of the scope of patent application, wherein if the material used for the above-mentioned low-dielectric-constant dielectric layer is SiLK, the plasma contains N2-H NH Page 17 460969 VI. Application for patent scope 20. For the method according to item 12 of the patent scope, wherein the method for forming the above-mentioned low dielectric constant dielectric layer includes a chemical vapor deposition method (CVD) or a spin coating method (sp in on) ° 2 1. The method according to item 12 of the scope of patent application, wherein the dielectric constant of the above-mentioned low dielectric constant dielectric layer is about 2.6 to 3.1. 2 2. The method according to item 14 of the scope of patent application, wherein the material of the above barrier layer may be selected from one of the following clusters: Ta, TaN, TiN, TiW, Ti, or any combination thereof. _ 2 3. The method according to item 14 of the scope of patent application, wherein after forming the barrier layer, it further comprises forming a seed layer on the upper surface of the barrier layer to strengthen the adhesion of subsequent electroplating. 2 4. As the second supplementary method of the scope of patent application, wherein the material of the seed layer includes the same material as the metal thin film. Page 18