經濟部智慧財產局員工消費合作社印製 4 60876 3901pif2-doc/008 A? ___B7______ 五、發明說明（1) 本發明是有關於一種積體電路記憶體元件，且特別是 有關於一種包括主字兀線與次字兀線的有階層式子兀線架 構之積體電路記憶體元件。 具有主字元線與次字元線之有階層式字元線結構是必 須的，對於具有256Mb或以上之大容量之動態隨機存取記 憶體(DRAM)適用。因爲主字元線與次字元線分別驅動， 電源消失能夠降低。也就是主字元線間距不能太挾窄’以 有利於大型元件之製造。像一字元結構揭露’例如在美國 專利字號 5,416,748 ; 5,596,542 ; 5,764,585 以及 5,781,498 ’ 以上所有揭露在此納入參考。 在DRAM元件，電源供應電壓例如正電壓Vcc荷參考 接地電壓Vss要求固定無關於在溫度與雜訊之變化β在記 憶體元件電壓Vcc典型由內部電壓產生器所產生。供應電 壓參考如內部Vcc(IVC)。IVC具有惟一 DC準位，例如IVC 爲 5V,3.3V,2_8V 或 2V。 —些在DRAN元件之電路要素要求一抬昇(Boosted)電 壓VBST大於IVC準位。例如，一字元線元件器必須提供 .一抬昇電壓在儲存記憶胞電晶體之閘極（見美國專利字號 5,673,225)。抬昇電壓大於IVC準位藉由記憶胞電晶體兩 倍之臨界電壓。 ' 參考第1圖繪示一種傳統DRAM元件具有階層式字元 線架構。DRAM元件具有典型”四分之一間距(Quarter pitch)” 佈局於4次字元線荷4位元線作記憶胞陣列之間距。一主 位元線MWL連接於四個次字元線SWL1~SWL4，其中 SWL1〜SWL4耦接記憶體記憶胞之陣列10。一主字元線 3 未紙張尺玉適用中國國家標準（CNS)A4規格（210x297公楚^ " II----II--- II 丨訂--------梦 ί. (請先閱讀背面之注意事項再填寫本頁) 4 60876 A7 B7 ,901pif2.doc/008 五、發明說明（1) (請先閲讀背面之注意事項再填寫本頁) (MWL)解碼器20使用一晶片上抬昇電源供應電壓vbst和 產生一主字元解碼器信號MD以回應到列位址之部分 A3〜An。主字元解碼器信號MD懸擺在接地電壓Vss與抬 昇電壓Vbst之間，一次字元線(SWL)預先解碼器30回應 列位址之其他部分A1和A2，並產生四個次字元預先解碼 信號PX1~PX4。當在等待狀態時，所有次字元預先解碼信 號PX1-PX4保持在Vss準位(也就是邏輯低準位），但在啓 動狀態期間，只有其中一個保持在Vbst準位(也就是邏輯 高準位）。 四個SWL解碼器40-1至40-4，分別達接到次字元預 先解碼信號Ρ)Π〜PX4，並供應給IVC和Vbst。每一個SWL 解碼器40-1至40-4產生兩個次字元解碼信號WDi和 WDiB(在此i=l，2,3或4)，以回應對應之次字元預先解碼信 號PX1〜PX4之一。在等待狀態，所有次解碼信號 WDi，WD2，WD3和WD4保持在Vss準位，但在啓動狀態期 間，次解碼信號WD1,WD2,WD3和WD4之一個電晶體在 Vbst準位。所有次解碼信號WD1B，WD2B,WD3B和WD4B .在等待狀態保持在IVC準位，直到啓動狀態在Vss準位。 經濟部智慧財產局員工消費合作社印製 四個SWL驅動器50-1至50-4分別連接到次字元線40-1至40-4(或SWL解碼器之SWL1~SWL4)。每一SWL驅動 器50-1包括三個N通道MOS電晶體Mil，Mi2，Mi3(在此 i=l，2,3或4)。每一 SWL驅動器50-1產生一次字元驅動信 號SDi對應到主字元解碼信號MD，和它所對應次字元解 碼信號WDi和WDiB，和提供次字元驅動訊號Sdi到它連 接次字元線SWLi。次字元線一般抬昇高於Vcc+Vt(在此Vt 4 本紙張尺度適用中國國家標準（CNS)A4規袼（21(U 297公釐）Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 60876 3901pif2-doc / 008 A? ___B7______ V. Description of the Invention (1) The present invention relates to an integrated circuit memory element, and in particular, to a device including a main word The integrated circuit memory element of the hierarchical sub-line structure of the line and the sub-line. A hierarchical character line structure having a primary character line and a secondary character line is necessary, and is applicable to a dynamic random access memory (DRAM) having a large capacity of 256 Mb or more. Because the main character line and the secondary character line are driven separately, power disappearance can be reduced. That is, the pitch of the main character lines should not be too narrow to facilitate the manufacture of large components. One-character structure disclosures' are for example disclosed in U.S. Patent Nos. 5,416,748; 5,596,542; 5,764,585 and 5,781,498. All of the above disclosures are incorporated herein by reference. In DRAM devices, the power supply voltage such as the positive voltage Vcc and the reference ground voltage Vss are required to be fixed regardless of changes in temperature and noise β. The memory device voltage Vcc is typically generated by an internal voltage generator. Supply voltage reference is internal Vcc (IVC). IVC has a unique DC level, for example, IVC is 5V, 3.3V, 2_8V or 2V. Some circuit elements in the DRAN element require a boosted voltage VBST greater than the IVC level. For example, a word line device must provide a gate voltage to the memory cell transistor (see US Patent No. 5,673,225). The lifting voltage is greater than the IVC level by twice the threshold voltage of the memory cell transistor. '' Referring to FIG. 1, a conventional DRAM device has a hierarchical character line architecture. DRAM devices have a typical "Quarter pitch" layout with 4 word lines and 4 bit lines as the spacing between memory cell arrays. A main bit line MWL is connected to four sub-word lines SWL1 to SWL4, and SWL1 to SWL4 are coupled to the array 10 of the memory cells. One main character line 3 unprinted ruler jade applies Chinese National Standard (CNS) A4 specification (210x297 Gongchu ^ " II ---- II --- II 丨 order -------- dream). ( (Please read the precautions on the back before filling this page) 4 60876 A7 B7, 901pif2.doc / 008 V. Description of the invention (1) (Please read the precautions on the back before filling this page) (MWL) Decoder 20 use one The chip raises the power supply voltage vbst and generates a main character decoder signal MD in response to the portion A3 ~ An of the column address. The main character decoder signal MD is suspended between the ground voltage Vss and the boost voltage Vbst The primary word line (SWL) pre-decoder 30 responds to the other parts A1 and A2 of the column address and generates four secondary character pre-decode signals PX1 ~ PX4. When in the waiting state, all secondary characters pre-decode the signal PX1-PX4 are held at the Vss level (that is, the logic low level), but during startup, only one of them remains at the Vbst level (that is, the logic high level). Four SWL decoders 40-1 to 40 -4, which respectively receives the pre-decoded signals P) Π ~ PX4 of the sub-characters, and supplies them to IVC and Vbst. Each SWL decoder 40-1 to 40-4 generates two sub-character decoded signals WDi and WDiB (here i = 1, 2, 3 or 4) in response to the corresponding sub-character decoded signals PX1 ~ PX4 one. In the waiting state, all the secondary decoding signals WDi, WD2, WD3, and WD4 remain at the Vss level, but during the startup state, one of the transistors of the secondary decoding signals WD1, WD2, WD3, and WD4 is at the Vbst level. All the secondary decode signals WD1B, WD2B, WD3B and WD4B. In the waiting state, they remain at the IVC level until the starting state is at the Vss level. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Four SWL drivers 50-1 to 50-4 are connected to the sub-word lines 40-1 to 40-4 (or SWL1 to SWL4 of the SWL decoder). Each SWL driver 50-1 includes three N-channel MOS transistors Mil, Mi2, Mi3 (here i = 1, 2, 3, or 4). Each SWL driver 50-1 generates a character drive signal SDi corresponding to the main character decode signal MD, and its corresponding sub character decode signals WDi and WDiB, and provides a sub character drive signal Sdi to it to connect the sub characters. Line SWLi. The sub-character line is generally raised above Vcc + Vt (here Vt 4 This paper size applies the Chinese National Standard (CNS) A4 Regulations (21 (U 297 mm)
A ^0876 A7 B7 3S01pif2.doc/008 五、發明說明（i ) 爲一 MOS電晶體之臨界電壓），增加雜訊邊緣和消除記憶 胞捷徑電晶體之啓始損失。 (請先閱讀背面之注意事項再填寫本頁) 在啓動狀態，主位元線MWL驅動到Vbst準位，藉由 MWL解碼器20，所以節點Ni在每一 SWL驅動器50-i上 升到Vbst-Vt(在此Vt爲每一 MOS電晶體之臨界電壓）。 此後，當一選擇SWL解碼器40-i之次字元解碼信號WDi 和WDiB分別達到Vbst和Vss準位。依靠列位址A1和A2， 節點Ni開始抬昇，由於提升(Pull-up)電晶體Mil之閘極到 汲極靜電容量，所以電晶體Mi2截止和提供分離於主字元 線MWL和節點Ni如一本身抬昇(self-boosting)效應致能於 連接次字元線SWLi到驅動次解碼訊號Wdi之全高電壓(也 就是Vbst準位），下拉電晶體Mi3動作如一電流槽(Current Sinker)，對所對應之次字元線SWLi放電，直到主字元線 MWL和次解碼信號WDiB分別保持在Vss和IVC準位。 閘極氧化層式一重要M0S電晶體之要素。此間非導體 層能貫穿(Break down)，由於在閘極短路，在一長或強電 廠使用下透過氧化層。氧化層貫穿一般認爲造成正電荷聚 .集。 經濟部智慧財產局員工消費合作社印製 由上所述，傳統DRAM具有階層式字元線架構，因爲 主位元線解碼器20和次字元線驅動器50-1至50-4供應抬 昇電壓Vbst或以上，在此能有一較高可能，對M0S電晶 體將有較差閘極氧化層可靠度。 爲解決上述問體，MWL解碼器和SWL驅動器使用內 部電源供應電壓IVC，如第2圖繪示目的。請參考第2圖， 傳統DRAM元件具有如第1圖繪示相同排列，除了提供內 5 本紙張尺度適用中國國家標準（CNS)A4規格（210x297公釐） 經濟部智慧財產局員工消費合作社印製 4 80876 3 9 0 lpif2 . d〇c/〇〇8 五、發明說明（w) 部電源電壓IVC之MWL解碼器20a和SW驅動器50a-l至 50a-4外。在第2圖相同於第1圖的部分’具有相同的參 考號碼和相同功能’因此省略再次說明。 第2圖結構可以提供閘氧化層可靠度改善’但另一問 題可能會發生，當它使用於一運用低電源電壓之記憶體元 件，例如2V或更低。這些問題將在下面解釋。 請再參考第2圖’再主動狀態’主字元線MWL由IVC 準位驅動；藉由MWL解碼器20a ’所以節點Ni在每一SWL 驅動器50a-I上升到IVC-Vt。當一選擇SWL解碼器40-1 之次解碼信號WDi和WDiB分別上升到Vbst和Vss ’節點 Νι最後上升到IVC-Vt+Vbst=2IVC+Vt準位，由於本身抬昇 效應。 例如假定IVC和VT分別爲3V和6V，節點Ni將上升 到6.6(=2*3+0.6)伏特電壓，所以提昇電晶體Mil能夠完全 驅動連接之次字元線SWLi提高到4_2(=3+2*0.6)伏特之vBST 準位。 然而IVC設定爲2V，此時節點Ni將上升到4.6伏特 電壓，此電壓不足以驅動連接之次字兀線SWLi提高到3 2 伏特之Vbst準位，造成增加預先充電時間延遲和降低雜 訊邊緣。更進一步在低電源供應電壓，造成更嚴重之售效 應。因此在第2圖之字元線驅動結構可能具有限制在低電 壓運作下。 本發明想解決上述問題，並根據本發明的目的提供_ 低電壓DRAM兀件以階層式子兀線架構’該結構能夠提昇 它的字兀線足夠去讀取/儲存一完全電源供應電壓準位從/ 6 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） — 111 — !! I i -I1III11 » — — — 1111— (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 460876 五、發明說明（t ) 到它的記憶體記憶胞。 爲達到上述目的，本發明一種動態隨機存取記憶體積 體電路，包括：一主字元線解碼器、一次字元線預先解碼 器、複數個次字元線解碼器以及複數個次字元線驅動器。 主字元線解碼器回應一列位址之一第一部份和產生一主字 元解碼訊號去驅動該主字元線。主字元線解驅動提高到一 抬昇電壓(VBST)大於一電源供應電壓(Vcc或IVC)藉由主字 元解碼器、。次字元線預先解碼器，用以回應該列位址之一 第二部份和選擇產生複數個次字元預先解碼信號。每一該 次字元線解碼器以回應連接該些次字元預先解碼信號之 一，並產生一次字元解碼信號。當啓動時，次字元解碼信 號到抬昇電壓（Vbst)。每一該次字元線驅動器以回應該主 字元解碼信號與該次字元解碼信號，並產生一次字元驅動 信號去驅動連接之該些次字元線，該些字元線驅動器每一 個包括:一 N通道MOS提升電晶體，和一 N通道MO.S預 先充電電晶體，其中上述兩者臨界電壓爲彼此不同。提升 電晶體傳導路徑耦接在次字元解碼信號和連接次字元線 .間。預先充電電晶體具有一傳導路徑耦接在主字元線和提 升電晶體之控制電極。預先充電電晶體之控制電極耦接在 抬昇電壓（Vbst) 〇抬昇電壓比電源供應電懕大抬昇電晶體 >_臨界電壓的雨倍。預先充電電晶體之臨界電壓小於提升 電晶體之臨界電壓。 爲讓本發明之上述目的、特徵、和優點能更明顯易懂， 下文特舉一較佳實施例，並配合所附圖式，作詳細說明如 下： 7 本纸張尺度適用中國國家標準（CNS)A4規格（210x297公釐） 1丨|1!|!|丨 —ίί' _ 1 I I I 丨 I 1 訂 _1 — 1!11_ 键ί (請先閱讀背面之注意事項再填寫本頁) 4 60876 A7 39〇lpif2.doc/008 __ B7__ 五、發明說明（& ) 圖式之簡單說明： 第1圖繪示習知DRAM元件之電路圖形； 第2圖繪示另一個習知DRAM元件之電路圖形； <請先閱讀背面之注意事項再填寫本頁) 第3圖繪示依照本發明一較佳實施例的DRAM元件之 電路圖形； 第4圖繪示第3圖之個別SWL解碼器的詳細電路圖 形；以及 第5、圖繪示圖形描繪次字元線抬昇電壓準位對預先充 電電晶體之通道寬度，與對預先充電電晶體之起始電壓 Vt 0 實施例 本發明之較佳實施例將伴隨參考圖形作詳細描述，在 所知電路顯示於區塊圖形型式，並非模糊本發明。 請參照第3圖，其繪示依照本發明一較佳實施例的一 種DRAM元件之電路圖形。DRAM元件具有階層式字元線 架構包括主字元線與次字元線和它具有四分之一間距佈局 再該4個次字元線和4位元線作記憶胞陣列之單位間距。 經濟部智慧財產局員工消費合作社印製 .一主字元線MWL連接到四個次字元線SWL1-SWL4，上述 四個次字元線SWL1-SWL4耦接記憶體記憶胞之陣列1〇〇。 MWL解碼器200使用一晶片上提昇電源供應電壓Vbst和 產生一主字元解碼信號MD，以回應列位址部分A3~An。 主字元解碼信號MD懸擺在接地電壓Vss和提昇電壓 Vbst。SWL預先解碼器300回應到列位址之其它部分A1 和A2，並產生四個次字元預先解碼信號ρχι〜PX4。當在 等待狀態時，所有次字元預先解碼信號PX1-PX4保持在Vss 8 本紙張尺度適g中國國家標準（CNS)A4規格（210_X 297公餐)" d60876 3901pif2.doc/008 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明ο ) 準位(也就是邏輯低準位），但在啓動狀態期間，只有其中 一個拉升到Vbst準位(也就是邏輯高準位）。 四個SWL解碼器400-1至400-4，分別連接到次字元 預先解碼信號PX1〜PX4,並都供應IVC和Vbst。每一個SWL 解碼器400-1至400-4產生兩個次字元解碼信號WDi，WDiD 和WDiB(在此i=l，2,3或4)，以回應對應之次字元預先解 碼信號PX1〜PX4之一。 第4、圖繪示個別SWL解碼器400-1，400-2,400-3以及 400-4之的詳細電路圖形。每一個SWL解碼器400-1包含 耦接串聯之兩反向器II和12與另外兩串聯耦接反向器13 和14。兩反向器II與12提供提昇電壓Vbst，直到另外兩 個反向器13和14提供電源供應電壓IVC。反向器II與13 提供連接次字元預先解碼信號Pxi。次字元解碼信號Wdi 由反向器12提供。另一次字元解碼信號WDiB和WDiD分 別從反向器13和14輸出。次字元解碼信號WDi懸擺在接 地電壓Vss和提昇電壓Vbst，但是次字元解碼信號WDiB 和WDiD懸擺在接地電壓Vss(較低電源供應電壓)和IVC(較 .高電源電壓）。 在等待狀態，所有次解碼信號WDi，WDiD和WDiB分 別保持在Vss，Vss和IVC準位，在啓動狀態期時，只有 ’選擇1個SWL解碼器400-1至400-4之次解碼信號 WDi，WDiD 和 WDiB 變成 Vbst，WC 和 Vss 準位。A ^ 0876 A7 B7 3S01pif2.doc / 008 V. Description of the Invention (i) is the threshold voltage of a MOS transistor) to increase the noise edge and eliminate the initial loss of the short circuit transistor. (Please read the notes on the back before filling this page) In the starting state, the main bit line MWL is driven to the Vbst level. With the MWL decoder 20, the node Ni rises to Vbst- at each SWL driver 50-i- Vt (here Vt is the threshold voltage of each MOS transistor). Thereafter, when the sub-word decoded signals WDi and WDiB of the SWL decoder 40-i are selected to reach the Vbst and Vss levels, respectively. Relying on column addresses A1 and A2, the node Ni starts to rise. Because the gate-to-drain electrostatic capacitance of the pull-up transistor Mil is lifted, the transistor Mi2 is cut off and separated from the main word line MWL and the node Ni If a self-boosting effect is enabled to connect the sub-word line SWLi to the full high voltage (that is, the Vbst level) that drives the sub-decoding signal Wdi, the pull-down transistor Mi3 acts like a current sink. The corresponding secondary word line SWLi is discharged until the main word line MWL and the secondary decoding signal WDiB remain at the Vss and IVC levels, respectively. The gate oxide type is an important element of the MOS transistor. During this time, the non-conductor layer can break down. Because of the short-circuit at the gate, it penetrates the oxide layer in a long or strong power plant. The oxide layer is generally thought to cause the accumulation of positive charges. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs As mentioned above, traditional DRAM has a hierarchical word line architecture because the main bit line decoder 20 and the second word line driver 50-1 to 50-4 supply the boost voltage Vbst or above, there is a high possibility here, and the reliability of the gate oxide layer will be worse for the MOS transistor. To solve the above problem, the MWL decoder and SWL driver use the internal power supply voltage IVC, as shown in Figure 2. Please refer to Figure 2. The conventional DRAM components have the same arrangement as shown in Figure 1, except that the 5 paper sizes provided are applicable to the Chinese National Standard (CNS) A4 specification (210x297 mm). Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 4 80876 3 9 0 lpif2. Doc / 〇〇8 V. Description of the invention (w) MWC decoder 20a and SW driver 50a-1 to 50a-4 of the power supply voltage IVC. In FIG. 2, the same portion ′ as that in FIG. 1 has the same reference number and the same function, and therefore the description is omitted. The structure of Fig. 2 can provide improved reliability of the gate oxide layer ', but another problem may occur when it is used in a memory element using a low power supply voltage, such as 2V or lower. These issues are explained below. Please refer to FIG. 2 again in the “reactive state”. The main word line MWL is driven by the IVC level. With the MWL decoder 20a, the node Ni rises to IVC-Vt at each SWL driver 50a-I. When the decoded signals WDi and WDiB of the SWL decoder 40-1 are selected, they rise to Vbst and Vss' nodes, respectively, and finally rise to the IVC-Vt + Vbst = 2IVC + Vt level, due to the effect of self-lifting. For example, assuming IVC and VT are 3V and 6V, respectively, the node Ni will rise to 6.6 (= 2 * 3 + 0.6) volts, so the boost transistor Mil can fully drive the connected secondary word line SWLi to 4_2 (= 3 + 2 * 0.6) vBST level of volts. However, the IVC is set to 2V. At this time, the node Ni will rise to a voltage of 4.6 volts. This voltage is not enough to drive the connected secondary word line SWLi to the Vbst level of 3 2 volts, causing an increase in the precharge time delay and a reduction in noise edges. . Furthermore, the power supply voltage is lower, resulting in more serious sales effects. Therefore, the zigzag line driving structure in Fig. 2 may be limited to low voltage operation. The present invention intends to solve the above-mentioned problems, and according to the purpose of the present invention, a low-voltage DRAM element is provided with a hierarchical sub-line structure. This structure can improve its word line to read / store a complete power supply voltage level. From / 6 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) — 111 — !! I i -I1III11 »— — — 1111— (Please read the precautions on the back before filling this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 460876 V. Description of invention (t) to its memory cell. In order to achieve the above object, the present invention provides a dynamic random access memory volume circuit, including: a main word line decoder, a primary word line pre-decoder, a plurality of sub word line decoders, and a plurality of sub word lines. driver. The main character line decoder responds to a first part of a list of addresses and generates a main character decode signal to drive the main character line. The main character line de-driving is increased to a lift voltage (VBST) greater than a power supply voltage (Vcc or IVC) by the main character decoder. The sub-word line pre-decoder is used for responding to the second part of a column address and selecting to generate a plurality of sub-word pre-decoding signals. Each of the sub-word line decoders responds to one of the pre-decoded signals connected to the sub-words, and generates a single-word decoded signal. When activated, the secondary character decodes the signal to a boost voltage (Vbst). Each secondary word line driver responds to the primary character decoded signal and the secondary character decoded signal, and generates a primary character drive signal to drive the connected secondary word lines. Each of the secondary word line drivers Including: an N-channel MOS boost transistor and an N-channel MO.S pre-charged transistor, wherein the threshold voltages of the two are different from each other. The boost transistor conduction path is coupled between the sub-character decoding signal and the sub-character line. The pre-charged transistor has a conductive path coupled to the main word line and a control electrode of the boost transistor. The control electrode of the pre-charged transistor is coupled to the lifting voltage (Vbst). The lifting voltage is larger than the power supply voltage. The lifting transistor > The threshold voltage of the pre-charged transistor is less than the threshold voltage of the boost transistor. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below and described in detail with the accompanying drawings as follows: 7 This paper size applies to the Chinese National Standard (CNS ) A4 size (210x297 mm) 1 丨 | 1! |! | 丨 —ί '' 1 III 丨 I 1 Order_1 — 1! 11_ key (Please read the precautions on the back before filling this page) 4 60876 A7 39〇lpif2.doc / 008 __ B7__ 5. Brief description of the invention (&) diagram: Figure 1 shows a circuit diagram of a conventional DRAM element; Figure 2 shows another circuit of a conventional DRAM element Figures; < Please read the notes on the back before filling this page) Figure 3 shows the circuit diagram of a DRAM device according to a preferred embodiment of the present invention; Figure 4 shows the individual SWL decoders of Figure 3 Detailed circuit pattern; and Figure 5, the graphic drawing depicts the channel width of the sub-character line lifting voltage level to the pre-charged transistor and the initial voltage Vt 0 of the pre-charged transistor. The example will be described in detail with reference to the figure, and the known circuit is shown in The pattern of block graphics does not obscure the present invention. Please refer to FIG. 3, which shows a circuit pattern of a DRAM device according to a preferred embodiment of the present invention. The DRAM device has a hierarchical character line structure including a main character line and a sub character line, and it has a quarter pitch layout. The 4 sub word lines and 4 bit lines are used as the unit pitch of the memory cell array. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. One main character line MWL is connected to four sub-character lines SWL1-SWL4, which are coupled to an array of memory cells 100. . The MWL decoder 200 uses a chip to boost the power supply voltage Vbst and generate a main character decoding signal MD in response to the column address portions A3 ~ An. The main character decoding signal MD is suspended on the ground voltage Vss and the boost voltage Vbst. The SWL pre-decoder 300 responds to the other parts A1 and A2 of the column address and generates four sub-character pre-decode signals ρχι ~ PX4. When waiting, all the pre-decoded signals PX1-PX4 of all sub-characters remain at Vss 8 This paper is suitable for Chinese National Standard (CNS) A4 specifications (210_X 297 meals) " d60876 3901pif2.doc / 008 A7 B7 Economy Printed by the Consumer Cooperative of the Ministry of Intellectual Property Bureau. 5. Description of invention ο) level (that is, the logic low level), but during the startup state, only one of them was pulled up to the Vbst level (that is, the logic high level). Four SWL decoders 400-1 to 400-4 are connected to the sub-characters respectively, and the signals PX1 to PX4 are decoded in advance, and all of them supply IVC and Vbst. Each SWL decoder 400-1 to 400-4 generates two sub-character decoded signals WDi, WDiD and WDiB (here i = 1, 2, 3 or 4) in response to the corresponding sub-character pre-decoded signal PX1 ~ One of PX4. Fig. 4 shows detailed circuit diagrams of individual SWL decoders 400-1, 400-2, 400-3 and 400-4. Each SWL decoder 400-1 includes two inverters II and 12 coupled in series and two other inverters 13 and 14 coupled in series. The two inverters II and 12 provide the boosted voltage Vbst until the other two inverters 13 and 14 provide the power supply voltage IVC. The inverters II and 13 provide the pre-decoded signal Pxi of the connected sub-character. The sub-word decoded signal Wdi is provided by the inverter 12. The other character decoding signals WDiB and WDiD are output from the inverters 13 and 14, respectively. The sub-character decoded signals WDi are suspended on the ground voltage Vss and the boosted voltage Vbst, but the sub-character decoded signals WDiB and WDiD are suspended on the ground voltage Vss (lower power supply voltage) and IVC (higher power supply voltage). In the waiting state, all the secondary decoded signals WDi, WDiD and WDiB are kept at the Vss, Vss and IVC levels respectively. During the start-up state, there is only 'select one SWL decoder 400-1 to 400-4 secondary decoded signals WDi. , WDiD and WDiB become Vbst, WC and Vss levels.
再回到第3圖，四個SWL驅動器500-1至500-4分別 連接到次字元線400-1至400-4(或SWL解碼器之 SWL1〜SWL4)。每一 SWL驅動器500-i包括四個N通道MOS 9 本纸張尺度遶用中國國家標準（CNS)A4規格（21〇x 297公釐） ---111--HI ϋ in! (請先閱讀背面之注意事項再填寫本頁) il 訂----- 鱗.. 經齊卽智慧財產局員工消費合作杜印製 460876 3901pif2-doc/〇〇8 幻 — _______ B7_____ 五、發明說明（？） 電晶體 Mil,Mi2，Mi3 和 Mi4(在此 i=l，2,3 或 4)。每一SWL 驅動器500-i產生一次字元驅動信號SDi對應到主字元解 碼信號MD，和它所對應次字元解碼信號Wdi,WDiD和 WDiB，和提供次字元驅動訊號SDi到它連接次字元線 SWLi。 每一次字元線驅動器500-i包括四個N通道MOS電晶 體Qil至Qi4(i=l，2,3或4)。第一電晶體Qil具有它源-汲 極通道耦接在次字元解碼信號MDi間和連接到次字元線 SWLi。第二電晶體Qi2具有它源-汲極通道耦接在主字元 線MWL和第一電晶體Qil之閘極間。第二電晶體Qi2之 閘極耦接到Vbst 〇亦ff：卜，枱舁電壓Vbst最好比IVC大第一 雷晶體之臨界雷懕的雨倍。在第三電晶體Qi3之源-汲極通 道耦接連接的次字元線SWLi與Vss，閘極在此耦接到次 字元解碼信號MDiB。第四電晶體Qi4具有它源·汲極通道 耦接在主字元解碼信號MWL和連接到次字元線SWLi間。 它的閘極耦接到次字元解碼信號MdiD。第三和第四電晶 體Qi3和Qi4提供用以對次字元線SWLi放電。 此外，爲降低節點Nil預先充電時間，第二電晶體Qi2 之起始電壓最好作成小於其他電晶體Qil，Qi3和Qi4。 在啓動狀態，主字元線MWL驅動到Vbst準位，藉由 MWL解碼器200，所以節點Ni在每一 SWL驅動器500-1 上升到VBST-VTQi2(在此VTQi2爲預先充電電晶體Ql2之起 始電壓），因此，當選擇SWL解碼器之次解碼信號WDi和 WDiD分別到達Vbst和IVC準位，依靠列位址A1和A2， 節點Nil開始提昇，由於拉升電晶體Qil之閘汲極電容， 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -------------,( Μ — (請先閱讀背面之注意事項再填寫本頁) 訂·_ 460876 9〇lpif2 .doc/008 A7 B7 五 經濟郎智慧財產局員工消費合作社印製 發明說明（θ ) ^ χ 所以電晶體Qi2截止並提供分離在主字元1鱗MWL和節點 Nil。此時’雖然IVC使用於開關電晶體Qi4 ’電晶體 保持在斷電狀態，因爲主和次字元線提舁到Vest準位高 於IVC準位。 由於本身提昇效應，節點Nil最後上升到一準位:V BST-VTQi2+V BST。因爲 VTQi2<VT，在此 VT 爲典型 NMOS 電 晶體如 Qil，Qi3,和 Qi4 之臨界電壓，¥351'-\^(3丨1+乂351>¥的·]'- Vt+V bst=2 Vbst-Vt=2(IVC+2 Vt)- Vt=2 IVC+3 Vt。 例如，如果IVC和Vt分別呈現爲2伏特和6伏特， 此時節點Nil將提昇到約5.8伏特電壓。因此’連接次字 元線SWLi能夠驅動次解碼信號WDi全部高電壓準位(也 就是VBST準位爲3.2V)。因此雖然IVC爲2V或更低，連 接次字元線SWU能夠驅動到完全Vbst準位，允許預先充 電時間延遲和雜訊干擾降低。 第5圖圖形描繪關係在次字元線上昇電壓準位對預先 充電電晶體Qi2之通道寬度，與對預先充電電晶體Qi2之 起始電壓Vt。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明’任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 請 先 閱 讀 背 意 頁 訂 線 11 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱）Returning to FIG. 3 again, the four SWL drivers 500-1 to 500-4 are connected to the sub-word lines 400-1 to 400-4 (or SWL1 to SWL4 of the SWL decoder), respectively. Each SWL driver 500-i includes four N-channel MOS 9 This paper is scaled around the Chinese National Standard (CNS) A4 (21 × 297 mm) --- 111--HI ϋ in! (Please read first Note on the back, please fill out this page again) il Order ----- Scale: Printed by the consumer cooperation of Qizhi Intellectual Property Bureau Du printed 460876 3901pif2-doc / 〇〇8 Magic — _______ B7_____ 5. Description of the invention (?) Transistors Mil, Mi2, Mi3 and Mi4 (here i = 1, 2, 3 or 4). Each SWL driver 500-i generates a character drive signal SDi corresponding to the main character decode signal MD, and its corresponding sub character decode signals Wdi, WDiD, and WDiB, and provides a sub character drive signal SDi to its connection time. Word line SWLi. Each time the word line driver 500-i includes four N-channel MOS transistors Qil to Qi4 (i = 1, 2, 3, or 4). The first transistor Qil has its source-drain channel coupled between the sub-word decoding signals MDi and connected to the sub-word line SWLi. The second transistor Qi2 has its source-drain channel coupled between the main word line MWL and the gate of the first transistor Qil. The gate of the second transistor Qi2 is coupled to Vbst. Also, the voltage Vbst of the stage voltage is preferably greater than the critical lightning voltage of the first thunder crystal. The secondary word lines SWLi and Vss are coupled to the source-drain channel of the third transistor Qi3, and the gate is coupled to the secondary word decoding signal MDiB. The fourth transistor Qi4 has a source-drain channel which is coupled between the main character decoding signal MWL and the secondary character line SWLi. Its gate is coupled to the sub-word decoding signal MdiD. The third and fourth electric transistors Qi3 and Qi4 are provided to discharge the secondary word line SWLi. In addition, in order to reduce the pre-charging time of the node Nil, the starting voltage of the second transistor Qi2 is preferably made smaller than the other transistors Qi1, Qi3, and Qi4. In the starting state, the main word line MWL is driven to the Vbst level, and with the MWL decoder 200, the node Ni rises to VBST-VTQi2 at each SWL driver 500-1 (here, VTQi2 is the pre-charged transistor Ql2 Starting voltage), so when the SWL decoder's second decoded signals WDi and WDiD reach the Vbst and IVC levels, respectively, relying on the column addresses A1 and A2, the node Nil starts to rise, due to the gate-drain capacitance of the transistor Qil ， This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) -------------, (Μ — (Please read the precautions on the back before filling this page) Order · 460 876 9〇lpif2 .doc / 008 A7 B7 Wujinglang Intellectual Property Bureau employee consumer cooperative printed a description of invention (θ) ^ χ so transistor Qi2 cuts off and provides separation in the main character 1 scale MWL and node Nil. At this time, 'although IVC is used for the switching transistor Qi4', the transistor remains in a power-off state because the primary and secondary word lines are raised to the Vest level higher than the IVC level. Due to its own lifting effect, the node Nil finally rises to one Level: V BST-VTQi2 + V BST. Because VTQi2 < VT, VT is typical here The threshold voltage of NMOS transistors such as Qil, Qi3, and Qi4, ¥ 351 '-\ ^ (3 丨 1+ 乂 351 > ¥' s]]-Vt + V bst = 2 Vbst-Vt = 2 (IVC + 2 Vt )-Vt = 2 IVC + 3 Vt. For example, if IVC and Vt appear as 2 volts and 6 volts, respectively, the node Nil will increase to about 5.8 volts. Therefore, 'connecting the sub-word line SWLi can drive the sub-decoding signal All WDi high voltage levels (that is, VBST level is 3.2V). Therefore, although the IVC is 2V or lower, the connected sub-word line SWU can be driven to the full Vbst level, allowing precharge time delay and noise interference to be reduced Figure 5 depicts the relationship between the rising voltage level of the sub-word line to the channel width of the pre-charged transistor Qi2 and the starting voltage Vt of the pre-charged transistor Qi2. Although the present invention has been disclosed in a preferred embodiment As above, however, it is not intended to limit the present invention. 'Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be regarded as the attached patent. The range is subject to definition. Please read the back page guide 11 paper rulers Degree applicable to China National Standard (CNS) A4 specification (210 X 297 public love)