664 1 A7 *---- B7 五、發明說明（1) [發明領域] 本發明係有關於一種半導體封裝技術，特別是有關於 一種直接铁入式覆晶型（Direct-Downset Flip-Chip，DDFC) 半導體封裝技術’其特點在於將所封裝之半導體晶月以一 直接嵌入方式安置於基板之中，藉此可使得整體之封裝製 程不需要進行除銲（solder deflux)及覆晶底部填勝（flip-chip underfill)程序， 以使得整體之封裝製程更為 簡化。 [發明背景] 覆晶型（F丨ip Chip)半導體封裝技術為一種先進之半導 體封裝技術’其與一般習知之非覆晶型封裝技術的最主要 不同點在於其所封裝之半導體晶片係以正面朝下之倒置方 式女置於基板上’並藉由複數個銲·塊（solder bumps)而電性 銲結至基板。由於覆晶型封裝結構中不需要使用較佔空間 之銲線（bonding wires)來將半導體晶片電性連接至基板， 因此可使得整體尺寸作得更為輕薄短小。 以下即配合所附圖式之第1A至1C圖及第2圖，以圖 解方式簡述一種習知之覆晶型半導體封裝技術。 請首先參閱第1A圖’此習知之覆晶型半導體封裝技 術係用以將一半導體晶片10封裝至一基板2〇上（註：此處 之第1A至1C圖為簡化之示意圖式，其僅顯示一小數目之 輸出入銲墊以及與本發明有關之元件；其具體實施之元件 數目及佈局形態可能更為複雜）。 半導想晶片10具有一電路面10a和一非電路面 l〇b(註：此處所謂之"電路面”係指半導體晶片1〇上形成 (諝先閲讀背面之注意事項再填寫本頁) 裝--------訂---- n f It 1 經濟邹智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 1 16160 A7 A7664 1 A7 * ---- B7 V. Description of the Invention (1) [Field of Invention] The present invention relates to a semiconductor packaging technology, and more particularly to a Direct-Downset Flip-Chip, DDFC) Semiconductor packaging technology 'is characterized by placing the packaged semiconductor wafers in a substrate in a direct embedding manner, thereby making the overall packaging process unnecessary for solder deflux and flip-chip bottom filling. (Flip-chip underfill) procedure to make the overall packaging process more simplified. [Background of the Invention] Fip ip semiconductor packaging technology is an advanced semiconductor packaging technology. The main difference between it and the conventional non-flip-chip packaging technology lies in the fact that the semiconductor chip it packages is front-facing. The female is placed on the substrate in a downward facing manner and is electrically bonded to the substrate by a plurality of solder bumps. Since the flip-chip package structure does not need to use a relatively large space of bonding wires to electrically connect the semiconductor wafer to the substrate, the overall size can be made thinner and shorter. The following is a diagrammatic description of a conventional flip-chip semiconductor packaging technology in conjunction with Figures 1A to 1C and Figure 2 of the drawings. Please refer to FIG. 1A first. The conventional flip-chip semiconductor packaging technology is used to package a semiconductor wafer 10 onto a substrate 20 (Note: Figures 1A to 1C here are simplified schematic diagrams, which are only Show a small number of I / O pads and components related to the present invention; the number of components and the layout of the specific implementation may be more complicated). The semiconducting wafer 10 has a circuit surface 10a and a non-circuit surface 10b (Note: The "circuit surface" referred to here means the semiconductor wafer 10 is formed. (Please read the precautions on the back before filling in this page ) Packing -------- Order ---- nf It 1 Printed by Zou Intellectual Property Bureau Staff Consumer Cooperatives Paper size Applicable to China National Standard (CNS) A4 (210 X 297 mm) 1 16160 A7 A7
五、發明說明（2 ) 體電路元件和輸出入銲墊之正面：而"非電路面"則係指半 導體晶片ίο上未形成積體電路元件和輸出入銲墊之背 面）。半導體晶片10的電路面10a上形成有複數個輸出入 銲墊U;其中每一個輸出入銲墊π上均預先形成有—個 圓球狀的銲塊（solder bump)30 = 基板20具有一正面20a和一背面20b ;其中正面2〇a ，為一平坦之平面，且其上形成有對應至半導體晶片1〇上之 鲜塊30的複數個表面型銲塊墊（s〇lder_bump pads)2l。此 些表面型銲塊墊21係分別連接至基板2〇上的導電跡線（未 顯示）° 如第2圖所示’上述之習知覆晶型半導體封裝製程包 括以下五個主要製程步驟： (51) 置晶程序（Die Bonding, D/B); (52) 迴銲程序（Solder Reflow); (53) 除銲程序（Solder Deflux); (54) 覆晶底部填膠程序（Flip-Chip Underfill);以及 (55) 植球程序（Solder Ball，S/B)。 請接著參閱第1 B圖，於置晶程序（步騍S丨）中，係首 先將半導體晶片10安置於基板20的正面20a上，並使得 各個銲塊3 0分別對齊至其對應之銲塊墊2 i。 當主導體晶片1 0安置於定位後，接著即進行迴輝程 序（步驟S 2)’藉以將备個銲塊3 0迴銲於對應之銲塊整2丨 丄使浔迴銲後之銲塊30即可將丰導體晶片丨丨）銲結戈雷 性藕接至基板20。 ------- - ____________ | _ . _______- m _________τι,------------------- 一 - ,| :· - c:··：：·：：.,： ^ 1 1 m Hr _ · 口、M- 4kl ^^1 ^i— I (請先閱請背面之注意事項再填寫本頁}V. Description of the invention (2) Front side of the body circuit components and the input / output pads: "Non-circuit surface" refers to the back surface of the semiconductor wafer where integrated circuit components and the input / output pads are not formed). A plurality of input / output pads U are formed on the circuit surface 10a of the semiconductor wafer 10; each of the input / output pads π is pre-formed with a spherical solder bump 30 = the substrate 20 has a front surface 20a and a back surface 20b; wherein the front surface 20a is a flat plane, and a plurality of surface-type bump pads 2l corresponding to the fresh blocks 30 on the semiconductor wafer 10 are formed thereon. These surface-type pads 21 are connected to conductive traces (not shown) on the substrate 20 respectively. As shown in FIG. 2 'the conventional flip-chip semiconductor packaging process described above includes the following five main process steps: (51) Die Bonding (D / B); (52) Solder Reflow; (53) Solder Deflux; (54) Flip-Chip Underfill); and (55) Solder Ball (S / B). Please refer to FIG. 1B. In the crystal setting procedure (step S 丨), the semiconductor wafer 10 is first placed on the front surface 20a of the substrate 20, and each solder bump 30 is aligned to its corresponding solder bump. Pad 2 i. After the main body wafer 10 is positioned, the return-to-glow process is then performed (step S 2) ', so as to re-solder a soldering block 30 to the corresponding soldering block 2 丄 丄 to make the soldering block after soldering At 30, the high-conductance wafer 丨 丨) can be soldered to the substrate 20 by soldering. --------____________ | _. _______- m _________ τι, ------------------- a-, |: ·-c: ·· :: · ：:.,: ^ 1 1 m Hr _ · Mouth, M- 4kl ^^ 1 ^ i— I (Please read the notes on the back before filling this page}
經濟部智慧財產局員工消費合作、吐.7. K 457664 A7 B7 經 濟 部 智 慧 財 產 局 消 費 合 社 印 製 五、發明說明（3 ) 然而於上述之迴銲程序中，有少量之銲料可能會濺溢 至銲塊墊21以外的區域上；因此迴銲程序完成之後，便必 須進行一除銲程序（步驟S3)，以將基板2〇的正面2〇a的濺 溢銲料清洗掉。 當半導體晶片10銲結於基板20上之後，由於銲塊 的分隔作用’因此半導體晶片10與基板2〇間會存在有一 覆晶底部間隙12。若不將此覆晶底部間隙ι2填以絕緣性 之膠質填料’則由於半導體晶片與基板2〇二者具有不 同之熱膨脹係數（Coefficient of Thermal Expansion CTE)，因此於高溫處理時，將易導致半導體晶片l〇及基 板20因熱應力之影響而造成結構破裂及電性失能。 請接著參閱第1C圖，上述問題的解決方法即為進行 一覆晶底部填膠程序（步驟S4)，以將一絕緣性之膠質填 料’例如為環氧樹脂，填入至覆晶底部間隙12中，藉此而 形成一覆晶底部填膠層1 3。 目前已有許多不同的覆晶底部填膠方法可用來形成上 述之覆晶底部填膠層13。然而由於大多數之覆晶底部填膠 方法的程序步驟極為繁複，因此實施上非常費時費力，並 不符合成本效益。 最後即進行一植球程序（步驟S5)，藉以將一銲球陣列 (solderballs)40植置於基板20的背面20b。此銲球陣列4〇 係連接至基板20中連接至銲塊墊21的導電跡線（未顯 示）’以作為半導體晶片10的外部電性連接點。此即完成 一覆晶型半導體封裝單元之製程。 ί猜先閱讚背面之注意事項再填寫未頁)Consumer cooperation and vomiting of employees of the Intellectual Property Bureau of the Ministry of Economic Affairs. 7. K 457664 A7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (3) However, during the reflow process described above, a small amount of solder may be splashed Spilled onto the area other than the solder pad 21; therefore, after the reflow process is completed, a solder removal process must be performed (step S3) to clean the spilled solder on the front surface 20a of the substrate 20. After the semiconductor wafer 10 is bonded to the substrate 20, there is a flip-chip bottom gap 12 between the semiconductor wafer 10 and the substrate 20 due to the separation effect of the solder bumps. If the bottom gap ι2 of the flip-chip is not filled with an insulating colloidal filler ', since the semiconductor wafer and the substrate 20 have different coefficients of thermal expansion (CTE), it will easily cause semiconductors during high temperature processing. The wafer 10 and the substrate 20 cause structural cracks and electrical disability due to the influence of thermal stress. Please refer to FIG. 1C. The solution to the above problem is to perform a flip-chip underfilling procedure (step S4) to fill an insulating gel filler such as epoxy resin into the gap of the flip-chip bottom 12 In this way, a flip-chip underfill layer 13 is formed. There are many different methods of flip-chip underfilling to form the above-mentioned flip-chip underfill 13. However, since most of the flip-chip underfill methods are very complicated, they are very time-consuming and difficult to implement and are not cost-effective. Finally, a ball implantation process is performed (step S5), so that a solderball array 40 is planted on the back surface 20b of the substrate 20. The solder ball array 40 is connected to conductive traces (not shown) 'of the substrate 20 connected to the pad pad 21 as external electrical connection points of the semiconductor wafer 10. This completes the process of a flip-chip semiconductor packaging unit. (guess first read the notes on the back of the praise, then fill in the page)
« n n 一51， I I* n I n n I 本紙張&度適用中國國家標準（CNSM4規格（210 X 297公釐〉 3 16160 經濟部智慧时產咼員工消費，-:.'τϋ. A', ——__B7____ 五、發明說明（4 ) 然而於具體實施上，上述之覆晶型半導體封裝技術卻 具有以下之數項缺點。 第一項缺點為其中之除銲程序（步驟S3)和覆晶底部填 勝程序（步驟S4)的程序步驟頗為繁複，因此實施上非常費 時費力’極為不符合成本效益。 第二項缺點為其中所採用之表面型銲塊墊2〗的黏銲 面積較小，因此會使得銲塊30較不易有效地黏銲至詳塊墊 21上’使得半導體晶片10與基板2〇之間的電性藕接不易 達到較高的可靠度。 第三項缺點為不易將散熱塊穩固地整合至封裝結構體 中，使得所封裝之半導體晶片具有不佳之散熱效能a 第四項缺點為所完成之封裝單元的高度較大；這是由 於半導體晶片10係安置於基板2〇的正面2〇a的上方，使 得整體之封裝單元的高度大致等於半導體晶片10與基板 —者的南度總合。 第五項缺點為迴銲過锃φ 桎中熔化之銲塊30之間易於因 溢流而產生橋接現象，因而造 适成+導體晶片10之輪出入銲 墊〗1之間的短路現象。這是由 該些銲塊30之間的間隔 距離非常地小；且於進行迴钽 4鮮程序之前、該些銲塊30之間 並未有任何的隔離設施s 第六項缺點為丰導體晶片n 巧lu與基板20之間的藕合面 積較小，僅等於半導體晶片1 〇 、J電路面10a的面積.因此 二者之間的熱膨張係數差異ίΤ 、lt m arch丨易於對封裝结 構體產生熱應力破壞現象 Γ --------訂--------- {請先閱讀背面之注意事項再填寫本頁)«Nn a 51, II * n I nn I The paper & degree is in accordance with the Chinese national standard (CNSM4 specification (210 X 297 mm) 3 16160 Ministry of Economic Affairs wisdom production and employee consumption,-:. 'τϋ. A', ——__ B7____ V. Description of the invention (4) However, in the specific implementation, the above-mentioned flip-chip semiconductor packaging technology has the following disadvantages. The first disadvantage is the solder removal process (step S3) and the bottom of the flip-chip. The procedure of the filling procedure (step S4) is quite complicated, so it is very time-consuming and labor-intensive to implement. It is not very cost-effective. The second disadvantage is that the surface-type pad pad 2 used therein has a small welding area. Therefore, the solder bump 30 will be less easily and effectively adhered to the detailed pad 21, making the electrical connection between the semiconductor wafer 10 and the substrate 20 difficult to achieve a high reliability. The third disadvantage is that it is not easy to dissipate heat. The block is firmly integrated into the package structure, so that the packaged semiconductor wafer has poor heat dissipation performancea. The fourth disadvantage is that the height of the completed package unit is large; this is because the semiconductor wafer 10 is placed on the substrate 20 positive Above 20a, the height of the overall package unit is approximately equal to the sum of the south of the semiconductor wafer 10 and the substrate. The fifth disadvantage is that the melted solder bumps 30 in 锃 φ 桎 are liable to overflow due to reflow. This phenomenon results in a bridging phenomenon resulting in a short circuit between the wheels of the + conductor wafer 10 and the pads. This is because the distance between the solder bumps 30 is very small; Before the fresh procedure, there is no isolation facility between the solder bumps 30. The sixth disadvantage is that the bonding area between the high-conductor wafer n and the substrate 20 is small, which is only equal to the semiconductor wafer 10, J. The area of the circuit surface 10a. Therefore, the difference in thermal expansion coefficient between the two ίΤ, lt m arch 丨 is easy to cause thermal stress damage to the package structure Γ -------- order -------- -(Please read the notes on the back before filling this page)
Us 45?664 A7 ------ B7 五、發明說明（5)Us 45? 664 A7 ------ B7 V. Description of the invention (5)
目前已有許多不同的專利技術可以用來製造覆晶型半 導體封裝單元’例如美國專利第5,742,1 00號"STRUCTURE HAVING FLIP-CHIP CONNECTED SUBSTRATES”。然而此 專利技術於應用上’上述之缺點仍然存在。 [發明概述] 黎於以上所述習知技術之缺點，本發明之主要目的便 是在於提供一種新的覆晶型半導體封裝技術，其可免除習 知技術所必需之除銲程序和覆晶底部填膠程序，以使得整 趙之封裝製程更為簡化及符合成本效益。 本發明之另一目的在於提供一種新的覆晶型半導體封 裝技術，其可提供具有較大黏銲面積的銲塊墊，藉以使得 半導體晶片與基板之間的電性藕接具有更高的可靠度。 本發明的又一目的在於提供一種新的覆晶型半導艎封 裝技術，其可將散熱塊穩固地整合至封裝結構體中，使得 所封裝之半導體晶片具有更佳之散熱效能。 本發明之再一目的在於提供一種新的覆晶型半導體封 裝技術’其所製成之封裝單元可具有更小之高度。 本發明之再另一目的在於提供一種新的覆晶型半導體. 封裝技術，其可防止迴銲之銲塊之間產生橋接現象’以防 止半導體晶片之輸出入銲墊之間產生短路現象。 本發明之再另一目的在於提供一種新的覆晶型半導體 封裝技術，其可增加半導體晶片與基板之間的藕合面積， 以降低二者之間的熱膨脹係數差異（CTE mismatch)所導致 之熱應力破壞現象。 本紙張尺度適用中國國豕標準（CNS)A4規格（210 X 297公餐） (請先閲讀背面W注意事項再填寫本頁) - —r f) t4 n I n I n a^i I . 經濟部智慧財產局員Η消費合作社印製 16160There are many different patented technologies that can be used to fabricate flip-chip semiconductor packaging units, such as US Patent No. 5,742,100 " STRUCTURE HAVING FLIP-CHIP CONNECTED SUBSTRATES ". However, this patented technology is applied to the above-mentioned disadvantages [Summary of the Invention] In view of the disadvantages of the conventional technology described above, the main purpose of the present invention is to provide a new flip-chip semiconductor packaging technology, which can eliminate the soldering procedures and The flip-chip underfilling process makes the whole Zhao's packaging process more simplified and cost-effective. Another object of the present invention is to provide a new flip-chip semiconductor packaging technology that can provide a large bonding area. The solder pad pad makes the electrical connection between the semiconductor wafer and the substrate more reliable. Another object of the present invention is to provide a new flip-chip semiconductor package technology, which can stabilize the heat dissipation block. The ground is integrated into the package structure, so that the packaged semiconductor chip has better heat dissipation performance. Another object of the present invention is to improve A new flip-chip semiconductor packaging technology is provided. The packaging unit made of the new flip-chip semiconductor packaging technology can have a smaller height. Yet another object of the present invention is to provide a new flip-chip semiconductor packaging technology, which can prevent re-soldering. To bridge between the solder bumps to prevent short circuit between the input and output pads of the semiconductor wafer. Another object of the present invention is to provide a new flip-chip semiconductor packaging technology, which can increase the semiconductor wafer and the substrate. To reduce the thermal stress failure caused by the CTE mismatch between the two. This paper size applies to China National Standard (CNS) A4 (210 X 297 meals) ( Please read the precautions on the back before filling out this page)--rf) t4 n I n I na ^ i I. Printed by the Consumer Property Cooperative, Member of the Intellectual Property Bureau, Ministry of Economic Affairs 16160
經濟部智慧时產 a»;8x..-iif 乂.：：.7,.- P Λ： — _______B7__ 五、發明說明（6) 根據以上所述之目的，本發明即提供了 一種新穎之新 的覆晶型半導體封裝技術。 本發明之覆晶型半導體封裝技術所提供之封裝製程包 S以下步领-(〗）預製一半導體晶片和一基板；該半導體晶 片具有一電路面和一非電路面；該電路面上形成有複數個 輸出入銲墊；且該基板具有一正面和一背面；該正面上形 成有一置晶穴，且該置晶穴之底面上形成有複數個凹洞型 銲塊墊，其分別具有一預定之凹洞形狀；（2)設置複數個銲 塊於該半導體晶片上之複數個輪出入銲墊上；（3)將該半導 體晶片嵌入於該置晶穴之中，並使得各個銲塊分別植入於 對應之凹洞型銲塊墊；（4)進行一迴銲程序，藉以將各個銲 塊迴銲於對應之凹洞型銲塊墊上；以及（5)進行一植球程 序’藉以將一銲球陣列植置於該基板的背面上。 本發明之覆晶型半導體封裝技術所提供之封裝結構包 含以下構件：（a) —半導體晶片，其具有一電路面和一非電 路面；且該電路面上形成有複數個輸出入銲墊；（b)複數個 銲塊，其分別形成於該半導體晶片上之複數個輸出入銲墊 上，（c) 一基板，其具有一正面和一背面；該正面上形成有 一置aa八’且該置晶穴之底面上形成有複數個凹洞型銲塊 塾；（d) 一銲球陣列，其係植置於該基板的背面上；以及 (e ) —敖熱塊，其係安置於該置晶六之上·並接觸至該半導 體晶片之非電路面：其中該半導體晶片係嵌八於該基板 之置益穴中’且各悃銲塊係植Λ並迴銲於對憨之凹洞型鲜 塊给ρ 、以将該半導體晶g纟？结及電姓稹接至至該基板 裝--------訂---------線 (請先閱璜背面之注意事項再填寫本頁)8x ..- iif 部. ::. 7, .- P Λ: — _______B7__ 5. Explanation of the invention (6) According to the above-mentioned purpose, the present invention provides a novel and new Flip-chip semiconductor packaging technology. The package process package provided by the flip-chip semiconductor packaging technology of the present invention has the following steps-() prefabricating a semiconductor wafer and a substrate; the semiconductor wafer has a circuit surface and a non-circuit surface; and the circuit surface is formed with A plurality of input / output pads; and the substrate has a front surface and a back surface; a cavity is formed on the front surface, and a plurality of recessed solder pad pads are formed on the bottom surface of the cavity, each of which has a predetermined The shape of the cavity; (2) a plurality of solder bumps are arranged on the semiconductor wafer with a plurality of wheel in / out pads; (3) the semiconductor wafer is embedded in the cavity, and each solder bump is implanted separately On the corresponding cavity-shaped solder pad pad; (4) performing a re-soldering procedure to re-solder each of the solder bumps on the corresponding cavity-shaped solder pad cushion; and (5) performing a ball-planting procedure to thereby solder a solder The ball array is placed on the back of the substrate. The package structure provided by the flip-chip semiconductor packaging technology of the present invention includes the following components: (a) a semiconductor wafer having a circuit surface and a non-circuit surface; and a plurality of input / output pads are formed on the circuit surface; (B) a plurality of solder bumps, which are respectively formed on the plurality of input / output pads on the semiconductor wafer, (c) a substrate having a front surface and a back surface; on the front surface, an aa eight 'and an A plurality of recessed solder bumps 形成 are formed on the bottom surface of the cavity; (d) an array of solder balls, which are planted on the back surface of the substrate; and (e)-ao thermal block, which is disposed on the substrate Above the crystal six and contact the non-circuit surface of the semiconductor wafer: the semiconductor wafer is embedded in the Zhiyi cavity of the substrate ', and each of the solder bumps is planted and re-soldered in the opposite cavity type Give fresh ρ to the semiconductor crystal g 纟? Connect and connect to the base board to install -------- order -------- line (please read the precautions on the back of the page before filling in this page)
0 X 457664 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（7) 本發明之直接喪入式覆晶型半導體封裝技術具有以下 數優點：（一）可免除習知技術所必需之除銲程序和覆晶底 部填膠程序’使得封裝製程更為簡化及符合成本效益；（二） 可提供較大的黏銲面積，使得半導體晶片與基板之間的電 性藕接具有更高的可靠度；（三）可將散熱塊穩固地整合至 封裝結構體中’使得封裝單元具有更佳之散熱效能；（四） 所提供之封裝單元具有更小之高度；（五）於迴銲過程中， 可防止熔化之銲塊之間產生橋接現象，以防止半導體晶片 之輪出入銲墊之間產生短路現象；以及（六）可增大半導體 晶片與基板之間的藕合面積’因此可降低熱膨脹係數差異 (CTE mismatch)所導致之熱應力破壞現象。 [圖式簡述] 本發明之實質技術内容及其實施例已用圖解方式詳細 揭露緣製於本說明書所附之圖式之_。此些圖式之内容簡 述如下： 第1A至1C圖（習知技術）為剖面結構示意圖，其用以 顯示一習知之覆晶型半導體封裝結構； 第2圖（習知技術）為一流程圖，其中顯示第1八至工匸 圖所示之覆晶型半導體封裝結構的主要製程步驟； 第3A至3C圖為剖面結構示意圖，其用以顯示本發明 之覆晶型半導體封裝結構； 第4圖為一流程圖，其中顯示本發明之覆晶型半導體 封裝結構的主要製程步驟。 [圖式標號說明] -____ 1 I 11. . . II 1 1 I I · I I 1 1 I 一&，. ft H —ί — n I— (琦先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用令國國家標準（CNS)A4規格（210x 297公复） 7 16160 A7 A7 120a基板120之正面 121 置晶穴： 1 23 鲜料罩幕（solder mask) 140 銲球陣列（solder balls) 五、發明說明（8 ) j υ 平导體晶片 10a 半導體晶片10之電路面 10b 半導體晶片10之非電路面 11 輸出入銲墊 12 覆晶底部間隙 13 覆晶底部填膠層 20 基板 20a 基板20之正面 20b 基板2 0之背面 21 表面型銲塊墊 30 銲塊（solder bumps) 40 銲球陣列（solder balls) π 〇半導體晶片 110a半導體晶片110之電路面 Π Ob半導體晶片11〇之非電路面u 1 輸出入銲墊 120基板 120b基板120之背面 1 2 2凹洞型銲塊墊 130 銲塊（solder bumps) 150 散熱塊（heat sink) [發明實施例] 以下即配合所附圖式之第3 A至3 C圖及第4圖’詳細 揭露說明本發明之直接嵌入式覆晶型半導體封裝技術之一 實施例。 請首先參閱第3A圖，於此實施例中’本發明之覆晶 型半導體封裝技術係用以將一半導體晶片110封裝至一基 板120上(註：此處之第3A至3C圖為簡化之示意圖式’ 其僅顯示一小數目之輸出銲墊以及與本發明有關之元 件：其具體實施之元件數目及佈局形態可能更為複雜）1 半導體晶片I 1 0具有.電路面1 1 0a和一非電路面】丨()t 丨:註此處呤謂之‘電路面' 涤指本導體晶# M 0上形成積韻 S3 ίό 1 ---------------------訂---------線 (請先閱讀背面之注意事項再填窝本頁) 457664 A7 B7 五、發明說明（9) <請先閲讀背面之注意事項再填寫本頁> 電路元件和輸出入鋒墊之正面：而”非電路面I，則係指半導 體晶片110上未形成積體電路元件和輸出入銲墊之背 面）°半導體晶片110的電路面11 〇a上形成有複數個輸出 入銲墊1Π ;其中每一個輸出入銲墊111上均預先形成有 一個銲塊（solder bump) 130。 基板12 0例如為一陶製基板；但亦可為任何其它一種 適用於覆晶應用之基板。基板120具有一正面i2〇a和一背 面120b。本發明之技術要點即在於基板12〇之正面12〇a 上形成有一下凹之置晶穴121;且此置晶穴121之底面上 形成有複數個凹洞型銲塊墊122和一作為銲料罩幕（s〇ider mask)之絕緣層123。 此些凹洞型銲塊墊122之凹洞形狀為一向内漸窄之圓 錐形狀’其係分別對應至半導體晶片110上之各個銲塊13〇 而設置’且其尺寸正好可容納各個銲塊13〇。此外，此些 凹洞型銲塊墊122係連接至基板120上的導電跡線（未顯 示）。 經濟部智慧財產局員工消費合作社印製 如第4圖所示’本發明之覆晶型半導體封裝技術僅包 括以下三個主要製程步驟： (511) 置晶程序； (512) 迴銲程序；以及 (513) 植球程序。 請接著參閱第3B圖，於置晶程序（步驟S11)中，係首 先將半導體晶片110以覆晶方式嵌入於基板12〇的置晶穴 121中’使得半導體晶片11〇之電路面11〇a緊密地貼置於 本紙張尺度適用中國國家標準（CNS)A4規格（210x297公釐） 9 16160 Λ7 五、發明說明（w /置晶穴m的底面上，且使得其電路面】ι〇&上的銲塊i3〇 刀引植入於置晶穴121的底面上所形成的凹洞型銲塊墊 122之中。 當半導體晶片110安置於定位後，接著即進行—迴銲 程^ G驟S12)，藉以將各個焊塊13〇迴辉於對應之四洞 θ鬼墊122上，使得迴銲後之銲塊】即可將半導體晶 片π〇銲結及電性藕接至基板12〇α 於上述之迴鲜過程中，由於各個銲塊130係被植入於 對應之凹洞型辉塊塾122之中' 且半導體晶片η〇之電路 = "〇a係緊密地貼置於置晶以21的底面上，因此熔化之 銲塊130不會滅溢至凹洞型鲜塊塾122以外之區域上，亦 即不會使得溶化之銲塊13〇之間產生橋接現象。此外，各 個凹洞型銲域塾m之下凹結構可使其提供一更大之黏辉 面積。 請接著參閱第3C圖，下一個步驟為進行一植球程序 (步驟S5) ’藉以將-輝球降列（solder balls)刚植置於基板 120的背面120b上。此銲球陣列14〇係連接至基板丨2〇中 連接至凹洞型銲塊墊122的導電跡線（未顯示），以作為半 導體晶片Π 0的外部電性連接點a 此外，可進而將-散熱塊（heat s!nk)150安置於基板 丨20的正面i 20a上使其接觸至丨導體晶片丨丨〇的非電路 面Π Ob，藉以使得封裝後之半導體晶片π 〇可具有更佳之 散熱效能由於基板丨20可到散熱塊提洪支撐作用 因此散熱塊丨#可穩固地藕合g;導體晶片u 〇 裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 457664 A7 B7 五、發明說明（11) (請先閱讀背面之注意事項再填寫本頁) 綜而言之’本發明提供了一種直接嵌入式覆晶型半導 體封裝技術’其特點在於將半導體晶片以直接嵌入方式安 置於基板之置晶穴之中，並採用圓錐形狀之凹洞型銲塊墊 來將半導體晶片銲結至基板。 相較於習知技術，本發明之覆晶型半導體封裝技術具 有以下之數項優點。 第一項優點為本發明之覆晶型半導體封裝製程可免除 習知技術所必需之除銲程序和覆晶底部填膠程序，因此可 使得封裝製程更為簡化及符合成本效益。 第二項優點為本發明所採用之凹洞型銲塊墊122的黏 銲面積大於習知技術所採用之表面型銲塊墊的黏銲面積， 因此可使得銲域130更為易於有效地黏銲至此凹洞型銲塊 墊122’使得半導體晶片11〇與基板12〇之間的電性竊接 具有更高的可靠度。 第三項優點為本發明可將散熱塊150穩固地竊合至半 導體晶片110’使得所封裝之半導體晶片11〇具有更佳之 散熱效能。 經濟部智慧財產局員工消費合作社印製 第四項優點為本發明所製成之封裝單元具有更小之高 度’這疋由於半導體晶片110係欲入於基板12〇的下凹置 晶穴121之中’而非安置於基板表面上方，因此可使得封 裝單元的高度更為減小。 第五項優點為本發明所採用之凹洞型鮮塊塾可隔 離各個銲塊130:因此於迴銲過程甲，不會使得溶化之銲 塊I 3 0之間產生橋接現象’因此可防止半導體晶片11〇之 本紙張尺度適用中國固家標準（CNS)A4規格（2〗0 X 297公釐） 11 16160 A7 五、發明說明（12) 輸出入銲墊11 1之間產生短路現象。 第六項優點為本發明可增大半導體晶片110與基板 I 20之間的藕合面積（亦即除了半導體晶片1〗〇的電路面 II 0a之外，其側面亦與基板1 2〇之置晶穴i 2 1的側壁形成 接觸）’因此可降低半導體晶片110與基板120二者之間的 熱膨脹係數差異（CTE mismatch)所導致之熱應力破壞現 象。 由於具有上述之優點’因此本發明之覆晶型半導體封 裝技術較習知技術具有更進步之實用性。 以上所述僅為本發明之較佳實施例而已，並非用以限 定本發明之實質技術内容的範圍。本發明之實質技術内容 係廣義地定義於下述之申請專利範圍中。任何他人所完成 之技術實體或方法，若是與下述之申請專利範圍所定義者 為元全相同、或是為一種等效之變更，均將被視為涵蓋於 此專利範圍之中。 -------------裝---------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧5?產局i Μ消費今作社._:||於0 X 457664 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (7) The direct-wrap-type flip-chip semiconductor packaging technology of the present invention has the following advantages: (1) It can eliminate the need for conventional technology The de-soldering process and the flip-chip under-filling process make the packaging process more simplified and cost-effective; (2) It can provide a larger bonding area, making the electrical connection between the semiconductor wafer and the substrate higher. (3) The heat sink can be firmly integrated into the packaging structure, so that the packaging unit has better heat dissipation performance; (4) The provided packaging unit has a smaller height; (5) During the reflow process In order to prevent the bridging phenomenon between the melted solder bumps, to prevent the short circuit phenomenon between the wheel of the semiconductor wafer and the pad, and (6) the bonding area between the semiconductor wafer and the substrate can be increased. Thermal stress failure caused by CTE mismatch. [Brief Description of the Drawings] The essential technical content of the present invention and its embodiments have been disclosed in detail by means of illustrations in the drawings attached to this specification. The contents of these diagrams are briefly described as follows: Figures 1A to 1C (known technology) are schematic cross-sectional structure diagrams, which are used to show a conventional flip-chip semiconductor package structure; Figure 2 (known technology) is a process flow Figures, which show the main process steps of the flip-chip semiconductor package structure shown in Figures 18 to 28; Figures 3A to 3C are schematic cross-sectional structure diagrams for showing the flip-chip semiconductor package structure of the present invention; FIG. 4 is a flowchart showing the main process steps of the flip-chip semiconductor package structure of the present invention. [Illustration of drawing number] -____ 1 I 11... II 1 1 II · II 1 1 I &,. Ft H —ί — n I— (Please read the notes on the back before filling this page) The paper size is applicable to the national standard (CNS) A4 specification (210x 297 public copy) 7 16160 A7 A7 120a front side of the substrate 120 121 cavity setting: 1 23 solder mask 140 solder balls array V. Description of the invention (8) j υ flat conductor wafer 10a circuit surface 10b of semiconductor wafer 10 non-circuit surface 11 of semiconductor wafer 10 input and output pads 12 chip bottom gap 13 chip bottom underfill layer 20 substrate 20a substrate 20 Front surface 20b Substrate 2 0 Back surface 21 Surface-type solder pads 30 Solder bumps 40 Solder balls π 〇 Semiconductor wafer 110a Circuit surface of semiconductor wafer 110 Π Non-circuit surface of semiconductor wafer 110 u 1 I / O pad 120 Substrate 120b Back side of Substrate 120 1 2 2 Cavity type solder pads 130 Solder bumps 150 Heat sink [Invention example] Figures 3 A to 3 C and Figure 4 'illustrate in detail the invention An embodiment of a direct embedded flip-chip semiconductor packaging technology. Please refer to FIG. 3A first. In this embodiment, the flip-chip semiconductor packaging technology of the present invention is used to package a semiconductor wafer 110 onto a substrate 120 (Note: Figures 3A to 3C are simplified here. Schematic 'It only shows a small number of output pads and components related to the present invention: the number of components and the layout of the specific implementation may be more complicated) 1 Semiconductor wafer I 1 0 has. Circuit surface 1 1 0a and a Non-circuit surface】 丨 () t 丨: Note here that the “circuit surface” refers to the conductor crystal # M 0 forming a product rhyme S3 ίό 1 --------------- ------ Order --------- line (please read the precautions on the back before filling the page) 457664 A7 B7 V. Description of the invention (9) < Please read the precautions on the back Fill in this page again> Front side of circuit components and I / O pads: "Non-circuit surface I" refers to the backside of integrated circuit components and I / O pads on semiconductor wafer 110) ° Circuit of semiconductor wafer 110 A plurality of input / output pads 1Π are formed on the surface 11 〇a; a solder bump (solder bum) is formed on each of the input / output pads 111 in advance. p) 130. The substrate 120 is, for example, a ceramic substrate; however, it can be any other substrate suitable for flip chip applications. The substrate 120 has a front surface i20a and a back surface 120b. The technical point of the present invention is the substrate 12 A concave recess 121 is formed on the front surface 12a of 〇; and a plurality of recessed solder pad pads 122 and a solder mask are formed on the bottom surface of this recess 121. Insulating layer 123. The pit shape of these dent-type solder pad pads 122 is a tapered shape that narrows inwardly, which is provided corresponding to each of the solder bumps 13 on the semiconductor wafer 110, and its size is just enough to accommodate Each of the solder bumps 130. In addition, these recessed solder bump pads 122 are connected to conductive traces (not shown) on the substrate 120. The employee's consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs prints this book as shown in Figure 4. The invented flip-chip semiconductor packaging technology includes only the following three main process steps: (511) chip placement procedure; (512) reflow procedure; and (513) ball implantation procedure. Please refer to FIG. 3B for the chip placement procedure. In step S11, the semiconductor crystal is first 110 is embedded in the crystal cavity 121 of the substrate 120 in a flip-chip manner, so that the circuit surface 11a of the semiconductor wafer 110 is closely attached to this paper. The standard of China paper (CNS) A4 (210x297 mm) is applicable. 9 16160 Λ7 V. Description of the invention (w / the bottom surface of the cavity m, and the circuit surface of the cavity) i3 on the bottom surface of the chip is implanted on the bottom surface of the cavity 121 In the hole-shaped solder pad pad 122. After the semiconductor wafer 110 is positioned, the reflow process is followed by-step S12), so that each of the solder bumps 130 is returned to the corresponding four-hole θ ghost pad 122, so that the solder bumps after reflow] That is, the semiconductor wafer π〇 soldering and electrical connection to the substrate 12 〇 In the above-mentioned refresh process, since each solder bump 130 is implanted in the corresponding cavity-shaped glow bump 塾 122 'and The circuit of the semiconductor wafer η〇 = "〇a is closely attached to the bottom surface of the chip 21, so the molten solder bump 130 will not overflow onto the area other than the recessed fresh block 塾 122, that is, Does not cause bridging between the melted solder bumps 130. In addition, the recessed structure of each recess-type welding area 塾 m can provide a larger sticky area. Please refer to FIG. 3C. The next step is to perform a ball-planting process (step S5) 'so that -solder balls are just planted on the back surface 120b of the substrate 120. This solder ball array 14 is connected to the conductive traces (not shown) of the substrate 丨 20 connected to the recessed solder pad pad 122 as an external electrical connection point a of the semiconductor wafer Π 0. -Heat s! Nk 150 is placed on the front surface i 20a of the substrate 20 and contacts the non-circuit surface Π Ob of the conductor wafer 丨 〇, so that the packaged semiconductor wafer π 〇 can have better Due to the heat dissipation effect of the substrate, the 20 can reach the heat sink to support the flood, so the heat sink can be firmly coupled to the conductor chip. The conductor chip is installed. (Please read the notes on the back before filling this page) 457664 A7 B7 V. Description of the invention (11) (Please read the notes on the back before filling this page) In short, the present invention provides a direct embedded cover The crystalline semiconductor packaging technology is characterized in that a semiconductor wafer is directly embedded in a cavity of a substrate, and a conical recessed solder pad pad is used to bond the semiconductor wafer to the substrate. Compared with the conventional technology, the flip-chip semiconductor packaging technology of the present invention has the following advantages. The first advantage is that the flip-chip semiconductor packaging process of the present invention can eliminate the solder removal procedures and flip-chip under-filling procedures necessary for the conventional technology, so that the packaging process can be simplified and cost-effective. The second advantage is that the sticking area of the cavity type pad pad 122 used in the present invention is larger than the sticking area of the surface type pad pad used in the conventional technology, so that the welding area 130 can be more easily and effectively stuck. Soldering to the recessed solder pad pad 122 ′ makes the electrical tapping between the semiconductor wafer 110 and the substrate 120 more reliable. The third advantage is that the heat sink 150 can be securely stowed to the semiconductor wafer 110 'so that the packaged semiconductor wafer 110 has better heat dissipation performance. The fourth advantage printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs is that the packaging unit made by the present invention has a smaller height. This is because the semiconductor wafer 110 is intended to be inserted into the recessed cavity 121 of the substrate 120. Instead of being placed above the substrate surface, the height of the packaging unit can be reduced. The fifth advantage is that the cavity-shaped fresh block used in the present invention can isolate each solder bump 130: Therefore, during the reflow process, the bridging phenomenon between the melted solder bumps I 3 0 will not be caused, and thus the semiconductor can be prevented. The paper size of the chip 110 is applicable to the Chinese solid standard (CNS) A4 specification (2〗 0 X 297 mm) 11 16160 A7 V. Description of the invention (12) A short circuit occurs between the input and output pads 11 1. The sixth advantage is that the present invention can increase the bonding area between the semiconductor wafer 110 and the substrate I 20 (that is, in addition to the circuit surface II 0a of the semiconductor wafer 1), the side surface thereof is also disposed with the substrate 1 20. The side walls of the cells i 2 1 are in contact), therefore, the thermal stress failure phenomenon caused by the CTE mismatch between the semiconductor wafer 110 and the substrate 120 can be reduced. Because of the above-mentioned advantages, the flip-chip semiconductor packaging technology of the present invention has more advanced practicability than the conventional technology. The above descriptions are merely preferred embodiments of the present invention, and are not intended to limit the scope of the essential technical content of the present invention. The essential technical content of the present invention is broadly defined in the scope of the following patent applications. Any technical entity or method completed by others, if it is the same as that defined in the scope of patent application described below, or an equivalent change, will be deemed to be covered by this patent scope. ------------- install --------- order --------- line (please read the precautions on the back before filling this page) 5? Production Bureau i Μ consumer Jinsakusha ._: || 于