TW457655B - Method of packaging an integrated circuit device - Google Patents
Method of packaging an integrated circuit device Download PDFInfo
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- TW457655B TW457655B TW89106037A TW89106037A TW457655B TW 457655 B TW457655 B TW 457655B TW 89106037 A TW89106037 A TW 89106037A TW 89106037 A TW89106037 A TW 89106037A TW 457655 B TW457655 B TW 457655B
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457655 五、發明說明(1) 發明之領域 特別地,本發明係關於積體電 本發明係關於電子裝置。 路之封裝。 發明之背景 隨著電子工業中微形化及小型產品潮流的持續,緊要需 求更輕、更小、更薄、且更快的電子封裝。由於其高密度 及短信號傳播路徑,覆晶的使用具有其本身的優點,優於 其他電子封裝之方法。在覆晶技術中,積體電路(I C )晶 片是藉由一種回焊過程、而經由焊接凸塊電連接至基板的 輸出/輸入(10)墊。為了達到一種可靠的焊接互連,典 型地係施加一助熔劑(f 1 u X i n g a g e n t )到端子,以為其 除去氧化物。後續的適當焊接,藉由洗滌而將助熔劑移 除’在這之後,施加一填充材料,以填充IC裝置與基板之 間的縫隙,而形成一包封的封裝件。此種材料通常熟知為 底層填充材料。 底層填充材料一般係由填充有二氧化矽之環氧化物所製 成,其係設計成具有相對較低的熱膨脹係數(CTE )’接 近於焊接材料的熱膨脹係數。因此,將晶片組裝到有機基 板所產生的熱機械應力,可經由底層填充,而從易碎的焊 接凸塊轉移到更耐變形的基板。 、將底層填充材料流動至晶片與基板間之縫隙的過程是十 ^冗^的。為了免除此步鄉,已發展出非流動底層填充材 j如八中添加諸如有機酸等之助熔劑,使得底層填充材料 可控制熔化能力。以此種方式,回焊步驟與包封步驟結457655 V. Description of the invention (1) Field of invention In particular, the present invention relates to integrated electronics. The present invention relates to electronic devices. Road package. BACKGROUND OF THE INVENTION With the continuing trend of miniaturization and small products in the electronics industry, there is an urgent need for lighter, smaller, thinner, and faster electronic packages. Due to its high density and short signal propagation path, the use of flip-chips has its own advantages over other electronic packaging methods. In flip chip technology, integrated circuit (IC) wafers are electrically connected to the output / input (10) pads of the substrate via solder bumps through a reflow process. To achieve a reliable solder interconnection, a flux (f 1 u X n g a g e n t) is typically applied to the terminals to remove oxides from them. The subsequent appropriate soldering removes the flux by washing '. After that, a filling material is applied to fill the gap between the IC device and the substrate to form an encapsulated package. Such materials are commonly known as underfill materials. The underfill material is generally made of an epoxide filled with silicon dioxide, which is designed to have a relatively low coefficient of thermal expansion (CTE) 'close to that of the solder material. Therefore, the thermomechanical stress generated by assembling the wafer to the organic substrate can be transferred from the fragile solder bump to the more deformable substrate through the underfill. The process of flowing the underfill material into the gap between the wafer and the substrate is redundant. In order to avoid this step, non-flowing underfill materials such as organic solvents have been developed, such as organic acids, so that the underfill material can control the melting ability. In this way, the reflow step is combined with the encapsulation step
4 57 6 55 五、發明說明(2) 合,而清潔步驟被免除。此種縮短的過程,如美國專利第 5, 128’ 746號所述,包括在將晶片的凸塊側置於其上之 前’先將非流動底層填充材料直接施加至基板上。 行焊接凸塊的回焊。 然非流動底層填充材料具有簡化封裝過程的優點,其 通节不包含二氧化矽填充劑,且其CTE遠高於習知底層填 =材料。因此,使用此型材料之封裝件易產生焊接凸塊破 ,’特別是對於大型晶粒尺寸而言。為解決此問題,美國 ^利第5, 8 1 4, 4G 1號揭示-種選擇性填充熱硬化性黏性薄 Μ,其包含一中央内部區域及一邊界區域。 ==成:其,以一惰性填充劑而填充,以便ί小該 曰如、 邊界區域由一黏著劑及一助熔劑所組成。當 :技ΐ之焊接凸塊被回焊時,助熔劑移除基板或晶粒之可 逾,。i面上所存在的任何氧化物’因此不需要額外助熔 策腺f ΐ是用來將一晶片晶粒黏性地接合至-基板。黏性 ^膜的t央區域位於晶粒巾央不具有焊接鬼之處的下 ::在接合至基板後穩定晶粒。然巾,此種配置僅適用 且=周31具有焊接&塊的晶#,而不適用於整個表面均 2 Ϊ的覆晶。再者’薄臈的使用,通常需要-些壓力 持力,以在回焊過程中將晶片押壓至基板i,而碟保 ^备的焊接。此種需求不適合於表面安裝技術(smt)過 程。 ::圓階層封裝已提出可將一環氧材料施加至晶圓 、 側,以便在分離成晶片之前先包封晶圓,後隨直接 4 57 6 55 五、發明說明(3) 回谭至一£n r? t 要维持接^ 路板上。然而,包封材料的CTE ’仍然需 ^本待接近於焊接凸塊的CTE,以確保可靠性。 袭方2 本發明之目的在於提供一種可減少前述問題的封 曰,t i在—種樣態中,本發明提供一種具有凸塊之電子 r i ί有凸塊之晶圓的封裝方法’方法為使用二種不同 合。第一包封劑(低CTE包封劑)包含一黏著 )勺二真充有<:1^減小填充劑。第二包封劑(助熔包封劑 一 I 3 —黏著劑,其含有一助熔劑或一助熔劑先質。在另 種樣態中’直接將低CTE包封劑施加至凸塊表面上,同 時仍允許焊接凸塊的部分被暴露出,以供焊接至指定基板 之對應I /0墊上。焊接接點在助熔包封劑存在的情況下予 以回焊,以達成凸塊表面與基板之間的最終黏著。 。在較佳具體例中’助熔包封劑係呈液態狀態,如此使得 回=過程可在標準狀況下進行’而不需要一個握持力以在 回焊訏將晶片和基板維持在—起》液態助熔包封剤的使 用’提供一項重要的利益’即其可適用於SMT (表面安裝 技術)。 本方法可應用於各種半導體封裴技術。根據本發明之一 具體例,一具有凸塊之晶圓在分離成晶片之前被封裝,方 法為藉由施加並將低CTE包封劑硬化至晶圓的凸塊表面 上。然後,已分離之晶片可被焊接至適當電子元件之基板 上’例如印刷電路板(PCB ),方法為藉由施加助熔黏著4 57 6 55 V. Description of the invention (2) The cleaning step is eliminated. This shortening process, as described in U.S. Patent No. 5, 128 '746, involves first applying a non-flowing underfill material directly to the substrate before placing the bump side of the wafer thereon. Re-soldering the solder bumps. However, non-flowing underfill materials have the advantage of simplifying the packaging process. The joints do not contain silicon dioxide fillers, and their CTE is much higher than conventional underfill materials. Therefore, package bumps using this type of material are prone to solder bump cracking, 'especially for large grain sizes. In order to solve this problem, U.S. Patent No. 5, 8 1 4, 4G 1 discloses a kind of selectively filled thermosetting viscous thin film M, which includes a central inner region and a boundary region. == Cheng: It is filled with an inert filler so that the boundary area is composed of an adhesive and a flux. When the solder bumps of the technology are re-soldered, the flux can remove the substrate or the die. Any oxide ' present on the i-plane therefore does not require an additional flux. The gland fΐ is used to adhesively bond a wafer die to a substrate. Viscosity ^ The t-central region of the film is located below the center of the die pad without soldering ghosts :: The die is stabilized after bonding to the substrate. However, this configuration is only applicable and the crystals with welded & blocks on week 31 are not suitable for flip-chips with an entire surface of 2 mm. Furthermore, the use of thin slabs usually requires some pressure holding force to press the wafer to the substrate i during the re-soldering process, while the discs are prepared for soldering. This requirement is not suitable for surface mount technology (smt) processes. :: Round-level packaging has been proposed that an epoxy material can be applied to the wafer and the side so that the wafer is encapsulated before separation into wafers and then directly 4 57 6 55 V. Description of the invention (3) Back to Tan Zhiyi £ nr? T keep the connection board. However, the CTE of the encapsulation material still needs to be close to the CTE of the solder bump to ensure reliability. The objective of the present invention is to provide a seal that can reduce the aforementioned problems. In one aspect, the present invention provides a method of packaging a wafer with bumps, and a wafer with bumps. The method is to use Two different combinations. The first encapsulating agent (low CTE encapsulating agent) contains one adhesive, two spoons filled with <: 1 ^ reducing filler. The second encapsulant (flux encapsulant I 3 —adhesive, which contains a flux or a flux precursor. In another aspect, 'low CTE encapsulant is directly applied to the surface of the bump, while Parts of the solder bumps are still allowed to be exposed for soldering to the corresponding I / 0 pads of the specified substrate. The solder joints are re-soldered in the presence of flux encapsulant to achieve the distance between the bump surface and the substrate The final adhesion. In the preferred embodiment, the 'flux encapsulant is in a liquid state, so that the back-flow process can be performed under standard conditions' without the need for a holding force to bond the wafer and the substrate during the re-soldering process. The use of “Keep-in-the-Like” liquid flux encapsulation 'provides an important benefit' that it can be applied to SMT (Surface Mount Technology). This method can be applied to various semiconductor sealing technologies. According to one of the inventions, the For example, a wafer with bumps is packaged before being separated into wafers by applying and hardening a low CTE encapsulant to the bump surface of the wafer. The separated wafer can then be soldered to the appropriate Electronic component substrate 'Such as a printed circuit board (PCB), a method of adhesion by applying a fluxing
457655 五、發明說明(4) ~~ 劑至P C β的指定表面上,並回焊該組件。 在較佳方法中,低CTE黏著劑被硬化或部分地硬化至凸 塊表面上’而各凸塊之暴露端被清除掉任何黏著劑。在助 熔黏著劑存在的情況下,於凸塊的回焊之後,可進行 化。 嶸 其所產生的產物包含第一及第二電子元件’其係經由烊 接接點而電連接。焊接接點之間的空間被填充二層包封材 料。第一包封材料,直接接觸第一電子元件之凸塊表面, 其含有-低CTE黏著劑。第二包封材料,纟有―助嫁 係設置於第一&封層貞第二電子元 疋表面之間。焊接接點係埋置於第一和第二包封層中、; 橫跨於其間。 矛匕τ增〒、並457655 V. Description of the invention (4) ~~ agent to the specified surface of P C β and re-solder the component. In the preferred method, the low CTE adhesive is hardened or partially hardened on the surface of the bump 'and the exposed end of each bump is cleared of any adhesive. In the presence of a flux adhesive, it can be applied after re-soldering the bumps.嵘 The products it produces include first and second electronic components' which are electrically connected via 烊 contacts. The space between the solder joints is filled with a second layer of encapsulating material. The first encapsulating material directly contacts the surface of the bump of the first electronic component, and contains a low-CTE adhesive. The second encapsulating material is provided with a "assistant" system between the surface of the first & encapsulation second electron element. The solder joint is buried in the first and second encapsulation layers; Spear and dagger increase, and
^種方法將非流動助炼黏著劑與低CT 結合。此外,心步驟中為液態形式之助V包封 Π二需要額外的握持壓力以在回焊期間維 :凸鬼與•曰疋表面之端子間 適用於SMT,同時改善榦駚& + 此方法可 方法易適用於晶圓階善層= 步朝向製造現實。裝,使付此種形式之封震更進-1佳具體例之銳明 本發明結合良好包封劑 理方便’方法為在同一封 劑’各提供兩種預期特性 請專利範圍中,「包括 的二項重要特性,即低CTE及處 襄過程中使用兩種個別的包封 的其中一種。在下述的說明及申 、「包含」、「含有」等詞彙係^ A method to combine non-flowing adhesives with low CT. In addition, the auxiliary V encapsulation in the liquid form in the heart step requires additional holding pressure to maintain SMT during re-soldering: the terminal between the convex and the surface of the surface is suitable for SMT, and at the same time improves the dryness & + this The method can be easily applied to wafer-level good layers = step-by-step manufacturing reality. This makes the sealing shock in this form more advanced. The specific example is sharp. The present invention combines a good encapsulant to make it convenient. The method provides two expected characteristics for each in the same encapsulant. The two important characteristics of low-CTE and the use of one of two separate encapsulation in the process. In the following description and application, "including", "including" and other vocabulary systems
第8頁 457655 五、發明說明(5) 用作為-種開放型式,因此應被解人 於......」。「凸塊」-詞係指可被回焊而5 ::不限 之電互連的結構。凸塊的範例包# (但不電子元件間 接凸塊’及由焊接材料與其他材_ (例、铲丄,及鉛焊 合所製成之接點。 錄村料)之組 低CTE包封劑之CTE接近於焊接材料 有:黏著劑及-CTE減小填充劑。-種範例為含;= ::乍^真充劑之環氧化物黏著劑。另一種範例為;有氧亞化 魷鋁或亞硝酸硼作為填充劑之環氧化物黏著劑。 j 限制性的範例中,半導體晶片封襄用的低CTE包封劑具非 1 〇- 5 0ppm/ C的CT£。另一非限制性範例係為一且、 20-45ppm/ °C之CTE的低CTE包封劑。助熔劑包含黏著劑 及一可在回焊狀態下產生助熔能力之作用劑。黏著劑可 為,例如’聚矽氧或熱塑性塑膠。作用劑可為,例如,一 助熔劑或一助熔先質。助熔劑的範例包括具有移除氧化物 塗層能力的有機酸’如PCT申請案wo 99/03597、及美國專 利苐5128746號所揭不’併述於此以供參考!5助炼先質的 範例係為添加有酐之醇類。根據本發明之較佳具體例,當 施加至指定基板表面上時,助熔劑係呈液態形式。基板的 範例包括(但不限於)第二階封裝基板及印刷電路板。 表1及2分別顯示低CTE黏著劑及助熔黏著劑的範例。 成分 量(g ) 範例1 範例2 Epi kote 828 2 0 35Page 8 457655 V. Description of the invention (5) It is used as an open type, so it should be sacrifice to ... ". "Bump"-The word refers to a structure that can be re-soldered with 5 :: unlimited electrical interconnection. Examples of bumps # (but not indirect bumps of electronic components' and contacts made from soldering materials and other materials _ (eg, shovel, and lead bonding). Low CTE encapsulation) The CTE of the flux is close to the welding material: adhesive and -CTE reducing filler.-An example is containing; = :: Zhang ^ true charge of epoxy adhesive. Another example is: aerobic subchemical squid Aluminum or boron nitrite is used as an epoxy adhesive for the filler. J In a limited example, the low CTE encapsulant used for semiconductor wafer encapsulation has a CT of not less than 10-50 ppm / C. Another non-limiting A typical example is a low CTE encapsulant with a CTE of 20-45 ppm / ° C. The flux includes an adhesive and an agent that can produce fluxing ability in the reflow state. The adhesive can be, for example, ' Polysiloxane or thermoplastic. The agent may be, for example, a flux or a flux precursor. Examples of fluxes include organic acids having the ability to remove oxide coatings, such as PCT application wo 99/03597, and the United States Patent No. 5128746 does not disclose 'and is described here for reference! 5 An example of a precursor for refining is the addition of an anhydride According to a preferred embodiment of the present invention, when applied to the surface of a given substrate, the flux is in a liquid form. Examples of substrates include (but are not limited to) second-stage packaging substrates and printed circuit boards. Tables 1 and 2 Examples of low CTE adhesives and fluxing adhesives are shown separately. Ingredient content (g) Example 1 Example 2 Epi kote 828 2 0 35
89106037.ptd 第9頁 457655 五、發明說明(6) 四氫酿酐(Tetrahydrophthalic anhydride) 15 0 2E4MZ 0.3 1. 7 甲基乙基酮(Methyl ethyl ketone) 8 5 熔化二氧化矽 70 65 表1 :低CTE黏著劑 成分 1(g) EP0N 8281 30 ERL 4221 70 六氫-4-甲基酜酐(Hexahydro-4- methy 1 phtha1ic anhydride) 80 Co(II) acetylacetonate (ACAC) 0.72 甘油 4.5 表2 :助熔黏著劑 本發明之方法可在具有焊接凸塊22之晶圓20的設有凸塊 之表面23上進行。在最終產品中’凸塊具有一端焊接至晶 片20a的I/O墊上,而一自由端用於在封裝或組裝期間、焊 接至一基板28的指定表面25上。參照圖1 A至1D,低CTE包 封劑材料2 4被施加至晶圓2 0的設有凸塊之表面2 3上(圖1A 及1 B )。一項可使用的技術為液態低CTE包封劑的旋轉塗 佈’接著進行硬化(可為完全或部分),然後移除任何過 量的包封劑。硬化可經由加熱或化學方法。硬化之低CTE 包封劑的厚度較佳為小於凸塊,以使得凸塊的部分可暴露89106037.ptd Page 9 457655 V. Description of the invention (6) Tetrahydrophthalic anhydride 15 0 2E4MZ 0.3 1. 7 Methyl ethyl ketone 8 5 Fused silica 70 65 Table 1: Low CTE Adhesive Ingredient 1 (g) EP0N 8281 30 ERL 4221 70 Hexahydro-4- methy 1 phtha1ic anhydride 80 Co (II) acetylacetonate (ACAC) 0.72 Glycerin 4.5 Table 2: Help The method of the present invention can be performed on the bump-provided surface 23 of a wafer 20 having solder bumps 22. In the final product, the 'bump has one end soldered to the I / O pad of the wafer 20a, and a free end is used to solder to a designated surface 25 of a substrate 28 during packaging or assembly. Referring to FIGS. 1A to 1D, a low CTE encapsulant material 24 is applied to the bumped surface 23 of the wafer 20 (FIGS. 1A and 1B). One technique that can be used is spin-coating of a liquid low CTE encapsulant, followed by hardening (which can be complete or partial), and then removing any excess encapsulant. Hardening can be via heating or chemical methods. The thickness of the hardened low CTE encapsulant is preferably less than the bumps, so that portions of the bumps can be exposed
89106037.ptd 第10頁 457655 五、發明說明(7) 出來’如圖1 B所示。另一項可使用的技術為模製法,例如 半固態或固態(樹脂)。如有過量的包封劑,亦即,一個 或多個凸塊的自由端被硬化之低CTE包封劑所覆蓋,則進 行自由端的清潔,例如,使用電漿蝕刻或雷射技術。之 後’ as圓可被分離以獲得個別的晶片。為易於說明,圖1 a 及1 B中僅顯示晶圓的一部份。晶圓的其餘部分僅以虛線繪 製’而’藉由切割虛線箭頭3 0所指示之位置,可獲得分離 的晶片2 0 a。然後,將助熔黏著劑2 6施加至基板2 8的指定 表面25,於基板28上可見到用於與凸塊互連的端子(圖1C )。助嫁黏著劑較佳以一薄液態層施加於面向上方的基板 指定表面。可使用習知的施加方法,如配料、印刷或浸 潰°然後’具有低CTE包封劑之晶片20a被置於基板上,使 得凸塊22接觸基板28之對應端子(圖1D )。這可由習知的 才σ取與放置系統來完成。然後’晶片/基板組合被移轉至 一回焊爐進行回焊。視所使用的包封劑材料而定,可能需 要一後硬化步驟’如,在例如丨5 〇 °c的低溫加熱3 〇分鐘, 以使黏著劑完全硬化。 雖然本發明已特別參照圖1Α至1 D加以說明,應瞭解的 是’圖式僅用於舉例,而不應被視為本發明之限制。此 外’很清楚地,本發明之方法可適用於許多使用非流動底 層填充及其他形式之表面安裝元件的應用。熟習此項技術 者所做之各種變化及修改均不偏離本發明之精神及範圍。 &注_編號之說明89106037.ptd Page 10 457655 V. Description of the invention (7) It's shown in Figure 1B. Another technique that can be used is molding, such as semi-solid or solid (resin). If there is an excess of encapsulant, that is, the free end of one or more bumps is covered by a hardened low CTE encapsulant, clean the free end, for example, using plasma etching or laser technology. Thereafter, the 'as circle can be separated to obtain individual wafers. For ease of explanation, only a portion of the wafer is shown in FIGS. 1 a and 1 B. The remaining part of the wafer is drawn only with a dotted line 'and' by cutting the position indicated by the dotted arrow 30, a separated wafer 20a can be obtained. Then, a flux adhesive 26 is applied to a designated surface 25 of the substrate 28, and terminals for interconnecting the bumps are visible on the substrate 28 (FIG. 1C). The grafting adhesive is preferably applied as a thin liquid layer to a designated surface of the substrate facing upward. A conventional application method such as batching, printing or dipping can be used and then a wafer 20a with a low CTE encapsulant is placed on the substrate such that the bumps 22 contact the corresponding terminals of the substrate 28 (Fig. 1D). This can be done by a conventional fascia pick and place system. The 'wafer / substrate combination is then transferred to a reflow oven for reflow. Depending on the encapsulant material used, a post-hardening step may be required, such as heating at a low temperature of, for example, 50 ° C for 30 minutes to completely harden the adhesive. Although the present invention has been described with particular reference to Figs. 1A to 1D, it should be understood that the 'schematics' are for illustration purposes only and should not be construed as limiting the invention. In addition, it is clear that the method of the present invention is applicable to many applications using non-flowing underfill and other forms of surface mount components. Various changes and modifications made by those skilled in the art will not depart from the spirit and scope of the present invention. & note_number description
457655 五、發明說明(8) 2 0 a....晶月 22 .....凸塊 23 .....設有凸塊之表面 24 .....低CTE包封劑材料 25 .....指定表面 2 6.....助溶黏著劑 28.....基板 30.....虛線箭頭457655 V. Description of the invention (8) 2 0 a .. Crystal moon 22 ..... bump 23 ..... surface with bump 24 ..... low CTE encapsulant material 25 ..... Specified surface 2 6 ..... Solvent adhesive 28 ..... Substrate 30 ..... Dotted arrow
89106037.ptd 第12頁 45765589106037.ptd Page 12 457655
89106037.ptd 第13頁89106037.ptd Page 13
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SG200001665A SG97872A1 (en) | 2000-03-23 | 2000-03-23 | Method of packaging an integrated circuit device |
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US6169328B1 (en) * | 1994-09-20 | 2001-01-02 | Tessera, Inc | Semiconductor chip assembly |
US5892287A (en) * | 1997-08-18 | 1999-04-06 | Texas Instruments | Semiconductor device including stacked chips having metal patterned on circuit surface and on edge side of chip |
US6191952B1 (en) * | 1998-04-28 | 2001-02-20 | International Business Machines Corporation | Compliant surface layer for flip-chip electronic packages and method for forming same |
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2000
- 2000-03-23 SG SG200001665A patent/SG97872A1/en unknown
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