TW457655B - Method of packaging an integrated circuit device - Google Patents

Abstract

A method of packaging a bumped electronic chip or a bumped wafer by utilising a combination of two different encapsulants. The first encapsulant (low CTE encapsulant) contains an adhesive filled with a CTE-reducing filler. The second encapsulant (fluxing encapsulant) contains an adhesive containing a fluxing agent or a precursor of a fluxing agent. The low CTE encapsulant is applied directly onto the bumped surface of a wafer before singulation into chips. The fluxing encapsulant is applied onto the substrate. The chip and the substrates are then joined together to form a package.

Description

457655 V. Description of the invention (1) Field of invention In particular, the present invention relates to integrated electronics. The present invention relates to electronic devices. Road package. BACKGROUND OF THE INVENTION With the continuing trend of miniaturization and small products in the electronics industry, there is an urgent need for lighter, smaller, thinner, and faster electronic packages. Due to its high density and short signal propagation path, the use of flip-chips has its own advantages over other electronic packaging methods. In flip chip technology, integrated circuit (IC) wafers are electrically connected to the output / input (10) pads of the substrate via solder bumps through a reflow process. To achieve a reliable solder interconnection, a flux (f 1 u X n g a g e n t) is typically applied to the terminals to remove oxides from them. The subsequent appropriate soldering removes the flux by washing '. After that, a filling material is applied to fill the gap between the IC device and the substrate to form an encapsulated package. Such materials are commonly known as underfill materials. The underfill material is generally made of an epoxide filled with silicon dioxide, which is designed to have a relatively low coefficient of thermal expansion (CTE) 'close to that of the solder material. Therefore, the thermomechanical stress generated by assembling the wafer to the organic substrate can be transferred from the fragile solder bump to the more deformable substrate through the underfill. The process of flowing the underfill material into the gap between the wafer and the substrate is redundant. In order to avoid this step, non-flowing underfill materials such as organic solvents have been developed, such as organic acids, so that the underfill material can control the melting ability. In this way, the reflow step is combined with the encapsulation step

4 57 6 55 V. Description of the invention (2) The cleaning step is eliminated. This shortening process, as described in U.S. Patent No. 5, 128 '746, involves first applying a non-flowing underfill material directly to the substrate before placing the bump side of the wafer thereon. Re-soldering the solder bumps. However, non-flowing underfill materials have the advantage of simplifying the packaging process. The joints do not contain silicon dioxide fillers, and their CTE is much higher than conventional underfill materials. Therefore, package bumps using this type of material are prone to solder bump cracking, 'especially for large grain sizes. In order to solve this problem, U.S. Patent No. 5, 8 1 4, 4G 1 discloses a kind of selectively filled thermosetting viscous thin film M, which includes a central inner region and a boundary region. == Cheng: It is filled with an inert filler so that the boundary area is composed of an adhesive and a flux. When the solder bumps of the technology are re-soldered, the flux can remove the substrate or the die. Any oxide ' present on the i-plane therefore does not require an additional flux. The gland fΐ is used to adhesively bond a wafer die to a substrate. Viscosity ^ The t-central region of the film is located below the center of the die pad without soldering ghosts :: The die is stabilized after bonding to the substrate. However, this configuration is only applicable and the crystals with welded & blocks on week 31 are not suitable for flip-chips with an entire surface of 2 mm. Furthermore, the use of thin slabs usually requires some pressure holding force to press the wafer to the substrate i during the re-soldering process, while the discs are prepared for soldering. This requirement is not suitable for surface mount technology (smt) processes. :: Round-level packaging has been proposed that an epoxy material can be applied to the wafer and the side so that the wafer is encapsulated before separation into wafers and then directly 4 57 6 55 V. Description of the invention (3) Back to Tan Zhiyi £ nr? T keep the connection board. However, the CTE of the encapsulation material still needs to be close to the CTE of the solder bump to ensure reliability. The objective of the present invention is to provide a seal that can reduce the aforementioned problems. In one aspect, the present invention provides a method of packaging a wafer with bumps, and a wafer with bumps. The method is to use Two different combinations. The first encapsulating agent (low CTE encapsulating agent) contains one adhesive, two spoons filled with <: 1 ^ reducing filler. The second encapsulant (flux encapsulant I 3 —adhesive, which contains a flux or a flux precursor. In another aspect, 'low CTE encapsulant is directly applied to the surface of the bump, while Parts of the solder bumps are still allowed to be exposed for soldering to the corresponding I / 0 pads of the specified substrate. The solder joints are re-soldered in the presence of flux encapsulant to achieve the distance between the bump surface and the substrate The final adhesion. In the preferred embodiment, the 'flux encapsulant is in a liquid state, so that the back-flow process can be performed under standard conditions' without the need for a holding force to bond the wafer and the substrate during the re-soldering process. The use of “Keep-in-the-Like” liquid flux encapsulation 'provides an important benefit' that it can be applied to SMT (Surface Mount Technology). This method can be applied to various semiconductor sealing technologies. According to one of the inventions, the For example, a wafer with bumps is packaged before being separated into wafers by applying and hardening a low CTE encapsulant to the bump surface of the wafer. The separated wafer can then be soldered to the appropriate Electronic component substrate 'Such as a printed circuit board (PCB), a method of adhesion by applying a fluxing

457655 V. Description of the invention (4) ~~ agent to the specified surface of P C β and re-solder the component. In the preferred method, the low CTE adhesive is hardened or partially hardened on the surface of the bump 'and the exposed end of each bump is cleared of any adhesive. In the presence of a flux adhesive, it can be applied after re-soldering the bumps.嵘 The products it produces include first and second electronic components' which are electrically connected via 烊 contacts. The space between the solder joints is filled with a second layer of encapsulating material. The first encapsulating material directly contacts the surface of the bump of the first electronic component, and contains a low-CTE adhesive. The second encapsulating material is provided with a "assistant" system between the surface of the first & encapsulation second electron element. The solder joint is buried in the first and second encapsulation layers; Spear and dagger increase, and

^ A method to combine non-flowing adhesives with low CT. In addition, the auxiliary V encapsulation in the liquid form in the heart step requires additional holding pressure to maintain SMT during re-soldering: the terminal between the convex and the surface of the surface is suitable for SMT, and at the same time improves the dryness & + this The method can be easily applied to wafer-level good layers = step-by-step manufacturing reality. This makes the sealing shock in this form more advanced. The specific example is sharp. The present invention combines a good encapsulant to make it convenient. The method provides two expected characteristics for each in the same encapsulant. The two important characteristics of low-CTE and the use of one of two separate encapsulation in the process. In the following description and application, "including", "including" and other vocabulary systems

Page 8 457655 V. Description of the invention (5) It is used as an open type, so it should be sacrifice to ... ". "Bump"-The word refers to a structure that can be re-soldered with 5 :: unlimited electrical interconnection. Examples of bumps # (but not indirect bumps of electronic components' and contacts made from soldering materials and other materials _ (eg, shovel, and lead bonding). Low CTE encapsulation) The CTE of the flux is close to the welding material: adhesive and -CTE reducing filler.-An example is containing; = :: Zhang ^ true charge of epoxy adhesive. Another example is: aerobic subchemical squid Aluminum or boron nitrite is used as an epoxy adhesive for the filler. J In a limited example, the low CTE encapsulant used for semiconductor wafer encapsulation has a CT of not less than 10-50 ppm / C. Another non-limiting A typical example is a low CTE encapsulant with a CTE of 20-45 ppm / ° C. The flux includes an adhesive and an agent that can produce fluxing ability in the reflow state. The adhesive can be, for example, ' Polysiloxane or thermoplastic. The agent may be, for example, a flux or a flux precursor. Examples of fluxes include organic acids having the ability to remove oxide coatings, such as PCT application wo 99/03597, and the United States Patent No. 5128746 does not disclose 'and is described here for reference! 5 An example of a precursor for refining is the addition of an anhydride According to a preferred embodiment of the present invention, when applied to the surface of a given substrate, the flux is in a liquid form. Examples of substrates include (but are not limited to) second-stage packaging substrates and printed circuit boards. Tables 1 and 2 Examples of low CTE adhesives and fluxing adhesives are shown separately. Ingredient content (g) Example 1 Example 2 Epi kote 828 2 0 35

89106037.ptd Page 9 457655 V. Description of the invention (6) Tetrahydrophthalic anhydride 15 0 2E4MZ 0.3 1. 7 Methyl ethyl ketone 8 5 Fused silica 70 65 Table 1: Low CTE Adhesive Ingredient 1 (g) EP0N 8281 30 ERL 4221 70 Hexahydro-4- methy 1 phtha1ic anhydride 80 Co (II) acetylacetonate (ACAC) 0.72 Glycerin 4.5 Table 2: Help The method of the present invention can be performed on the bump-provided surface 23 of a wafer 20 having solder bumps 22. In the final product, the 'bump has one end soldered to the I / O pad of the wafer 20a, and a free end is used to solder to a designated surface 25 of a substrate 28 during packaging or assembly. Referring to FIGS. 1A to 1D, a low CTE encapsulant material 24 is applied to the bumped surface 23 of the wafer 20 (FIGS. 1A and 1B). One technique that can be used is spin-coating of a liquid low CTE encapsulant, followed by hardening (which can be complete or partial), and then removing any excess encapsulant. Hardening can be via heating or chemical methods. The thickness of the hardened low CTE encapsulant is preferably less than the bumps, so that portions of the bumps can be exposed

89106037.ptd Page 10 457655 V. Description of the invention (7) It's shown in Figure 1B. Another technique that can be used is molding, such as semi-solid or solid (resin). If there is an excess of encapsulant, that is, the free end of one or more bumps is covered by a hardened low CTE encapsulant, clean the free end, for example, using plasma etching or laser technology. Thereafter, the 'as circle can be separated to obtain individual wafers. For ease of explanation, only a portion of the wafer is shown in FIGS. 1 a and 1 B. The remaining part of the wafer is drawn only with a dotted line 'and' by cutting the position indicated by the dotted arrow 30, a separated wafer 20a can be obtained. Then, a flux adhesive 26 is applied to a designated surface 25 of the substrate 28, and terminals for interconnecting the bumps are visible on the substrate 28 (FIG. 1C). The grafting adhesive is preferably applied as a thin liquid layer to a designated surface of the substrate facing upward. A conventional application method such as batching, printing or dipping can be used and then a wafer 20a with a low CTE encapsulant is placed on the substrate such that the bumps 22 contact the corresponding terminals of the substrate 28 (Fig. 1D). This can be done by a conventional fascia pick and place system. The 'wafer / substrate combination is then transferred to a reflow oven for reflow. Depending on the encapsulant material used, a post-hardening step may be required, such as heating at a low temperature of, for example, 50 ° C for 30 minutes to completely harden the adhesive. Although the present invention has been described with particular reference to Figs. 1A to 1D, it should be understood that the 'schematics' are for illustration purposes only and should not be construed as limiting the invention. In addition, it is clear that the method of the present invention is applicable to many applications using non-flowing underfill and other forms of surface mount components. Various changes and modifications made by those skilled in the art will not depart from the spirit and scope of the present invention. & note_number description

457655 V. Description of the invention (8) 2 0 a .. Crystal moon 22 ..... bump 23 ..... surface with bump 24 ..... low CTE encapsulant material 25 ..... Specified surface 2 6 ..... Solvent adhesive 28 ..... Substrate 30 ..... Dotted arrow

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Claims (1)

SG.U7 -M- iE Μ Conductor crystal 'The convex 457655 Amendment __Case No. 891_々' / Wide order piece of electricity 丨 Month Amendment VI. Application for patent scope ~ '' 1. A method for packaging a semi-conducting error chip The wafer is paid by a semi-circle. The wafer has at least one surface block including a soldering block and a free end for electrical connection to a substrate having a designated surface with metal terminals. The metal The terminal is used for electrical connection with the bump, and the method includes: a) applying a low CTE encapsulant to the surface of the wafer provided with the bump; b) hardening the low CTE encapsulant; c ) Exposing the free end of the bump; d) separating the wafer to obtain a plurality of low CTE encapsulated wafers; e) applying a flux encapsulant to a designated surface of the substrate; f) applying The separated wafer is placed on the substrate so that the bump is in contact with the terminal on the specified surface; g) the solder bump is re-soldered so that the bump is soldered to the terminal. 2 ♦ The method for packaging a semiconductor wafer according to the scope of the patent application, wherein the step of exposing includes laser ablation or plasma etching. 3. The method of packaging a semiconductor wafer according to item 1 of the scope of patent application, wherein the application step uses a molding technique. 4. The method for packaging a semiconductor wafer as described in the first patent application, wherein the application step uses a spin coating technique. 5. For the method of packaging a semiconductor wafer according to the scope of claim 1, wherein the step of hardening may cause the low CTE adhesive to be completely hardened or partially hardened. 6. —An electronic package including: 457655 ___Room No. 89106037 Rev. 6th, patent application scope-a first electronic component, which has a surface provided with a bump, on which a first electrical terminal is provided: a second electronic component, which has a designation The surface is provided with a plurality of second electrical terminals, at least one of the first electrical terminals of the package is electrically connected to a designated second electrical terminal via a soldering contact; and a hardening encapsulant is filled in the The space between the surface of the bump and the designated surface. 'The encapsulant includes a first encapsulant layer that directly contacts the surface provided with the bump and the solder joint; and a second adhesive layer. , Which directly contacts the designated surface and the welding contact. 7. The electronic package of claim 6 in which the first encapsulant layer has a thermal expansion coefficient of 10-50 ppm / ° C. 8. The electronic package according to item 6 of the application, wherein the first encapsulant layer contains a silicon dioxide filler, and the second encapsulant layer contains an additive. 9. The electronic package according to item 6 of the patent application scope, wherein the second adhesive layer + active-acting J '纟 can be removed and oxidized before the welding is performed at the second point before the adhesive is hardened. Thing. The first, the first, the second, and the second 10. The electronic package according to item 6 of the patent application scope, wherein the component is a semiconductor wafer. 〃 11. If the electronic package of item 6 of the patent application, the adhesive layer contains epoxy resin and silicon dioxide filled: 12. For the electronic package of item 6 of the patent application, the adhesive layer Contains an epoxy resin and a flux. v. 13. If the electronic seal of item 6 in the scope of patent application ’ 4 5 7 6 5: 89106037.ptc Page 16