TW457444B - Media access control architectures and network management systems - Google Patents

Abstract

Disclosed is a media access controller for transferring data along a computer network. The media access controller includes a transmit media access controller that is configured to process out-going packet data received from an upper layer for transmission to a physical layer. A receive media access controller that is configured to process in-coming packet data received from the physical layer for transmission to the upper layer. A transmit multi-packet queue FIFO for receiving the out-going packet data from the upper layer before being passed to the transmit media access controller. A receive multi-packet queue FIFO for receiving the in-coming packet data that is received by the receive media access controller. The media access controller further including a media access controller manager interfacing with the transmit and receive media access controllers. The media access controller manager being responsible for managing the flow of packet data through the transmit and receive multi-packet queue FIFOs.

Description

4574 44 A7 B7 V. Description of the invention (1) Background of the invention: 1. Field of the invention: The present invention is generally related to the use of data processing via communication networks: integrated circuit devices, and more specifically And some equipment to process and manage the data flow in the high-speed network lane. 2. Description of related technologies: Ethernet LAN (LAN) is the most popular and widely used computer network in the world. Since the beginning of Aether was in the early 1970s, computer network companies and engineering experts continued to improve Aether products in terms of functionality, reliability and transmission speed. To ensure the compatibility and reliability of the new network product, the Electronics and Electrical Engineers Organization (I EEE) formed a work group B to define and improve the Industrial LAN standard. Today, the I EE E has various Ethernet working groups that are responsible for standardizing the development of new Ethernet protocols and products under the LAN standard known internationally as the "IEEE 802.3 Standard". ^ Part Printed by the Consumer Standards Cooperative of the Central Bureau of Standards

Today, there is a wide range of standards-compliant Ethernet products that are used to receive, process, and transmit data over the Ethernet network. For example, these network products are traditionally integrated into network computers, network interface cards (NICs), 'routers', switching hubs, bridges, and repeaters. Until recently, the average data transmission speed via Ethernet was 1 Mbps (Million Bits per Second (Mbps) «However, in order to meet the need for fast data transmission speeds • The IEEE -4-{谙 Read first and pay attention Please fill in the details on this page) This paper size is in accordance with Chinese National Standard (CNS) A4 format (210X297 mm) 457444 A? B7 V. Description of the invention (2) 8 0 2. 3 In May 2015, the "IEEE802.3U standard" was proposed. This standard is also known as the "100 Base T Fast Ether" standard because it can be implemented at data transfer rates up to 1000 Mb ps. Figure 1A is an open system interconnection (OS I) layer module 10 developed by the International Organization for Standardization (I SO) to describe the information exchange between the layers. The 0 S I level module 1 0 is particularly useful for separated technical functions1 and thereby modify and update the specified level without disrupting the function of adjacent levels *. At the lowest level, the 0 S I module 10 has a physical layer 12 which is responsible for encoding and decoding data into information transmitted via a special medium. As is known in the art, the physical layer 12 is also referred to as the "P Η Y layer". Printed by the Ministry of Defence Standards Bureau, Consumer Cooperatives ^ (Read the notes on the back and then fill in the β book I) The line is above the physical layer 12 and a data bond layer 14 is defined to provide Reliable transmission of data over the network implements appropriate interfaces with a physical layer 12 and a network layer 16. As shown, the data bonding layer 1 4 generally includes a logical bonding layer (L L C) 1 4 a and a medium access control layer 14 b. LLC level 14a—Generally a software function to connect control information with data transmitted from network level 16 to MAC level 1 4 b. On the other hand, MAC level 1 4b is responsible for scheduling. Send and receive data on one click. Therefore, the MA C level 1 4 b mainly controls the data flow on the network to ensure that the transmission error is detected to ensure that the transmission system is properly synchronized. As is well known in the art, MA C level 1 4 b—usually uses the well-known carrier-sensing multiple access with collision detection (C SMA / CD) algorithm to apply Chinese national standards (CNS) to actual paper sizes. ) Α4 specification (210 × 297 mm) -5- grams printed by the Central Bureau of Standards Consumer Consumption Cooperative Association 457444 A7 _ B7_______ V. Description of the invention (3) The access data of the body layer 12 is used for scheduling and control. The network layer 16 is responsible for setting a data path 'between nodes of the network,' initializing 'maintenance among users connected to these nodes, and terminating a communication link. The transmission layer 18 is responsible for performing data transmission at a different service quality level. For example, a traditional software protocol used to perform transport layer 18 functions can be TCP / IP, Novell IPX and NetBeui «session layer 2 0 is when a user can determine whether the user's function is full dual Full-duplex or half-duplex transmission to transmit and receive data for control. The presentation layer 22 is responsible for translating, converting, compressing and decompressing the data transmitted through the media. For example, the functions of the presentation layer 22 are generally performed by computer operating systems such as Unix, DOS, Microsoft Windows 95, Windows NT, and Macintosh 0S. Finally, the application layer 24 provides the user with an appropriate interface to access and connect to a network. Figure 1B is a diagram of a traditional Ethernet packet as a data transmission via the network. The packet generally contains a preamble 30, which is traditionally an 8-bit leader. The initial frame boundary (not shown) follows the last byte (or octet) of the preceding text. In the starting frame boundary octet, a destination position (DA) 3 2 which is traditionally one of 6 bytes is used as a node confirming that the Ethernet packet will be received. After DA 3 2, it is a source address (S A) 3 4 which is generally a 6-byte leader, and S A 3 4 is a transmission node that confirms directly on the transmission packet. After the SA34, a length / type column (L / T) 36 (generally 2 bytes) is generally used as a label to indicate the length of the next data field and the size of the paper scale. S ΚΪ ## · ( CNS) A4 ^ (210X297 ^) ΤβΊ '~ --------- k ------ IT ------ 0 (For details, please read the precautions of 16 and then the poor) The Ministry of Justice, the Ministry of Justice, and the TK Industrial and Consumer Cooperation Du printed 4 p 7 4 4 4 Α7 Β7 Five 'invention description (4) state. As is known in the art, if the length is known, the packet is classified into 802.3 packets, and if the type field is provided, the packet is classified as an Ethernet packet. Since the following data field also contains the information that can be edited by the L L C layer 1 4 a :: Code information ’, this field is identified as L L C data 38. As is well known in the art, if a given Ethernet packet is smaller than 64 bytes, most media access controllers add 1's and 0's after the LCC data to add ether. The size of the packet is increased to at least 64 bytes. Once charge 40 is added, if necessary, a 4-byte repeat check (CRC) column is added to the end of the packet to check for damaged packets at the receiving end. As used herein, a "framework" should be interpreted as a sub-portion of the data contained in a packet = as previously stated 'Because the MA C layer 1 4 b is responsible for controlling the data flow on the network, the MAC layer 1 4 b—Generally responsible for encapsulating the received LLC data 38 with an appropriate preamble 30, DA32, SA34, DFL36, Pad40, and CRC 42. A further 'inner packet gap (I PG) is used as an acknowledgement-a span of time between transmitted Ethernet packets. Conventionally, the IPG is a fixed frame defined by the 802.3 standard and placed by an appropriate MA C layer 14b. For further information on Ethernet communication technology, please refer to the equipment and method of full-duplex Ethernet communication with US Patent Nos. 5,3 ii '1 14 and 5,504,738. " These patents are here for reference. Figure 1C is a conventional Ethernet media access controller (MA C) 50 0 This paper size is applicable to China® Home Standard (CNS) A4 specification (210X297 public attack:> (讦 先Please read the notes on the back and fill in this page again). 457444 A7 iii. Printed by the Central Bureau of Standards, T.Bigong Consumer Cooperative ^ __B7_V. The system architecture of the invention description (5). As shown, MA C 5 0 Includes a transmit (Tx) MAC controller 54 as processing data received from an upper LCC layer, and a receive (Rx) MAC controller 56 to process Ethernet packets received from a physical media 84. By On the transmission side, the data: The material is generally received from the upper LCC layer via the system bus 78. As shown, all data transmitted to the MA C 50 is sent to a bus via a path 52. Interface controller 7 4. In addition, the control and command signals are generally also It is transmitted to MA C 50 0 in a serial manner by path 52. Once the data is transmitted to the bus interface controller 74, the data is transmitted to a TxFIF062, which is to be received from the upper LCC layer Buffers for data retention. — In general, both Tx FIFO 62 and Rx FIFO 64 have FIFO control blocks 66 and 68 to transmit control information to the MAC controller 54 and to be stored in TxFIF062 and The transfer of the data stored in RxFIF068 is triggered. Therefore, in the conventional MA C architecture, once a selected processing control is transmitted to the T xMA C controller 5 4 or RxMAC controller 56, the special control information will be It is still "set control" as the default number of Ethernet packets. Then, the processing operations performed by TxMA C controller 54 and R zMAC controller 56 can not be modified during each individual frame transmission ( It can only be modified between transmissions.) Further shown are the instruction status register 72 and the statistical counter 70, the 72 and 70. The conventional system is responsible and aligned on the I and III lines ( #Read the precautions on the back before filling the sheet.) This paper size applies to Chinese National Standards (CNS) A4 specifications (210X297 gong) -8- 4g7444 Printed by the Industrial Standards Bureau of the Ministry of Economic Affairs I7 Consumer Cooperatives (6) The processes performed by the T xMA C controller 54 and the R xMA C controller 56 are tracked. In this conventional MA C design, path 5 2 is generally used as both data transmission and control signals. However, when the information stored in the command status register 72 and the statistical counter 70 is accessed, any data or control signals that are being transmitted to the TxMA C controller 54 will be suspended (which must be Slow down the network). Next, the management of the instruction status register 72 and the statistics controller 70 will also be completed to be used by path 52. Although the conventional MA C architecture 50 can work well, further improvements in processing increased data traffic, processing important flow control events, and processing management and network diagnostic events have been required. This feature is especially needed when the network speed continues to increase. For example, in today's technology, Ethernet does not even attempt to control the flow of work, and most of the data transmission is performed by point-to-point dump through the two selected bonds. That is, once the transmission parameters are set to perform the required processing (that is, the packet architecture variables are set), the sender will continuously pour the packets through the network until the user wants to update the transmitted packets Structural variables. Therefore, if an update is required, the change to the process must be transferred from the LCC layer down to the MAC layer via the same transmission path. However, when both control and data are transmitted via a processing path, the data and control must compete for bandwidth and only one is processed at a time. Then, once a packet transmission or reception function is initialized, the processing variable may not be changed. Know-how of the processing of the Ethernet MA C layer (Notes for reading 5LW) (restructure 3 pages), va-thread paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) 457444 red ' -'· &Quot; Printed by the Industrial and Commercial Cooperatives of the Bureau of Standards and Decisions of the Ministry of Justice ^ A7 B7 V. Description of the Invention (7) A further disadvantage is that once an incorrect packet is transmitted, it is generally unavoidable or skipped. Therefore, the receiving side must handle more error-prone packet processing. Further, the Ethernet MAC layer of the conventional art is currently unable to process a large stream of packets when the receiving side of the MAC: layer. As is known in the art, the size of the buffer in the MA C layer was increased in previous attempts to solve the problem. Although increasing the size of the buffer can slow down the problems of the prior art 1 OMb ps and 1000Mb ps Ethernet systems, increasing the buffer size is no longer a reasonable answer to the need for increased data traffic. It is further pointed out that the ethernet system of this know-how currently does not have a network management program with a proper level of network execution diagnostic capabilities. For example, when network diagnostics and execution features are performed, network management programs typically perform expensive diagnostics and network detection equipment, which is too expensive to analyze for a normal-sized network. As a result, network management programs are generally selected to update the entire Ethernet system before attempting to resolve network performance errors and flow control restrictions. After observing the above, when the packet is transmitted or received, the media access control (MAC) layer processing method that allows online packet to packet data information and control information processing to modify the characteristics of a packet, and Equipment is required. In addition, a method and a device for the MAC layer processing that allow the user to manage the packet data stream transmitted and received through the network and correctly perform the proficient detection test are needed. < Read the review on the back; I will fill in this page first)) This paper size applies to China National Standard Car (CNS) A4 specification (210X297 mm) -10- 457444 α7 Β7 ¾ ^. ¾. Printing of the Central Standards Bureau Consumer Cooperatives V. Description of the Invention (8) Description of the Invention: In one embodiment, a media access controller will be disclosed. The media access controller includes a transmission media access controller. The controller is configured to process the output packet data received from the received data for transmission to the upper layer of the physical layer. A receiving media access controller is structured to process the input packet data received from the physical layer for transmission to the upper layer. A plurality of packets are transmitted to queue FIF0 to receive output packet data from the upper layer before transmitting to the transmission media access controller. A plurality of packet queues F I F0 are received to receive the input packets received by the receiving medium access controller. The media access controller further includes a media access controller management program that interfaces with the transmitting and receiving media access controllers. The media access controller management system is responsible for transmitting and receiving multiple packet queues FIF0. And manage the packet data stream. In another embodiment, a network interface system as a communication over a network will be disclosed. The network interface system includes a media access controller to process transmission data received from an upper layer and to transmit processed transmission data to a lower layer, and to receive data received from a lower layer to Process and transfer the processed received data to the upper layer. The media access controller is structured to monitor the data flow between the upper and lower layers. The network interface further includes a data bus to communicate with the data and data control information between the upper layer and the media access controller "-the management control bus is to be located at the upper layer and the media access controller Communication between management control information, the management control bus has nothing to do with the data bus. L --------------- 1Τ ------ ^ (诔 Please take note of the fleas first, then fill in the paper 莨) This paper size applies to China National Standard (CNS) Α4 specifications (210 × 297 mm) -11-457444 Λ7 Β7 Printed by the Consumers' Cooperative of the Central Standards Bureau of Shao Yin Ministry 5. Description of the invention (9) In another embodiment, a media access controller will be disclosed as processing data A method for transmitting requests, receiving data requests, and monitoring data flow to a media access controller. The media access controller is architected to communicate with upper and lower layers. The method includes integrating a first bus to transfer data to and from one of the media access controllers. When the data transfer is being performed, a second bus, which communicates management control requests, is integrated into the media access controller. The second bus is coupled to a parallel event processor, which contains A microprocessor as a filter for selected data to be transmitted via the first bus. In another embodiment, a transmission medium access controller is disclosed. The transmission medium access controller includes a transmission interface unit structured to receive packet data from an upper layer, transmit a control signal, and control information. A transmission controller processes the packet data based on the control information received from the upper layer. The transmission control block is coupled to the transmission interface unit in two directions. A transport public block is used for monitoring and processing events in the transport control block. A transmission loop repeat check unit is structured to receive packet data from the transmission interface unit. The transmission loop repeat check unit is in communication with the transmission control block. The transmission medium access controller further includes an interface unit, which is structured to receive packet data from the transmission cycle repeat inspection unit before being transmitted to a physical layer. In another embodiment, a media access controller that has been structured to communicate with an upper layer and a lower physical layer will be disclosed. The media access controller includes a transmission controller to receive and process data transmission requests from an upper layer, and output the received data to the physical layer. The method contains from above ---. ------------ 1Τ ------ 0 (诮 Please read the note on the back first, and then fill out this page) The paper size is in accordance with the Chinese national standard (CNS > Α4 size ( 210X297mm} -12- Central sample of the Ministry of Super-Shanghai " Printed by Bureau of Off-line Consumer Cooperatives ^ 457444 A7 __. _B7_ V. Description of the invention (10) The layer receives data and processes the received data through the transmission controller. The execution of the processing is based on the settings of a plurality of control registers attached to the transmission controller. A control signal is received to modify at least one of the plurality of control registers and the data is processed via the transmission controller. The method further includes changing the processed data in the transmission controller according to the modification of at least one of the plurality of control registers attached to the transmission controller and outputting the processed data. In another embodiment, a transmission medium access controller will be disclosed. The transmission medium controller includes a transmission interface unit, which is structured to receive packet data from upper layers, transmit control signals and control information. A transmission control block includes a state machine to process the packet data. The processing is based on the control information received from the upper layer * and the transmission control block is bidirectionally coupled to the transmission interface unit. A transmission public block is used for monitoring and processing events in the transmission control block. A transmission loop repeat inspection unit is structured to receive packet data from the transmission interface unit. The transmission control block is in communication with the transmission cycle repeat check unit. The transmission medium access controller further includes a transmission fiber channel and a gigabit medium independent interface unit, and is structured to receive the packet data from the transmission cycle repeat check unit before the packet data is transmitted to a physical layer. In another embodiment, a controller is used to control data transfer between the physical layer and the upper layer. The controller includes a transmitter for transmitting data packets between the upper layer and the physical layer. The transmitter is structured to selectively Insert gaps between sequence data packets. The controller further includes a delay period register, which can be selectively written to indicate that it will be transmitted to the actual {count the precautions on the back first and then fill the {page). National Standard (CNS) A4 specification (210X297 mm) -13- 457444 A 7 B7 Ministry of Justice Standards Bureau Shellfish Consumer Cooperatives Co., Ltd. Printing and V. Description of invention (11) Intermediate packets inserted between the body's sequence packet data Gap period D. The delay period register is modified when the transmitter transmits data packets between the upper layer and the physical layer. In another embodiment, a media access controller 'the controller' will be revealed Data transfer between the physical layer and the upper layer. The media access controller includes a transmitter to transmit data between the upper layer and the physical layer. The media access controller further includes a retry limit register. The register can selectively program the number of transfers of the media access controller before the upper layer and the physical layer skip data transfer. The advantage is that the number of transmission attempts by the media access controller can be adjusted upwards to avoid jumps during high traffic cycles. In another embodiment, it will be revealed that a media access controller has been structured to communicate with upper and lower physical layers. The medium access controller includes a receiving controller to process the transmission request from the upper layer and to process the received data from the physical layer. One method for receiving data processing modifications in the receiving controller includes processing the data through the receiving controller, which processing is performed according to the register settings contained in the receiving processor. When the data is processed by the receiving controller, the control signal as a modification register is transferred to the receiving controller. The method further includes changing processing of the data processed in the receiving controller according to the modification of the register included in the receiving controller. In a further embodiment, a receiving medium access controller will be disclosed. The receiving medium access controller includes a physical medium receiving interface unit for receiving packet data from a physical medium and permitting optical fiber channels. ¾. ^ Read the back of the book; 1 fill in the meaning of the β book.} The paper size of the book is applicable to the Chinese National Standard (CNS) A4 specification (2 丨 0X297 public cage). ^ A7 _B7 V. Packet information in one of the (12) format and one billion-bit media independent format will be received. A receiver cycle repeat checker is structured to receive the packet data from the physical media receiving interface unit. A receiving interface unit is structured to receive the interface unit from the physical medium and the receiver periodic repeat checker: receiving packet data. The receiver interface unit is structured to receive multiple transfer control signals and control information from the upper layer. The receiving medium access controller further includes a receiver control block to process the received packet data according to the received transfer control signal and the received control signal. The receiver control block communicates with the receiver interface unit and the physical medium receiving interface unit. It also contains a receiver block to monitor and handle events in the receiver control block. In another implementation, a computer-readable medium will be disclosed including program instructions to drive a media access controller that has been communicated with the upper and lower physical layers through the architecture. The media access controller includes a receiving controller To receive and process requests for received data from lower layers and transfer the received data to the upper layers. The computer-readable medium contains program instructions' to receive data from the lower layer and to process the received data via the receiving controller. The processing is executed according to the setting of a plurality of control registers incorporated in the transfer controller. The program instructions process the data through the receiving controller and are used as receiving control signals to modify multiple control registers. The program instructions change the processing of the data processed in the receiving controller according to the modification of at least one of the plurality of control registers incorporated in the receiving controller, and the program instructions are used to transfer the processing data. The paper size of the paper is in line with the Chinese national standard (CNS 丨 A4 specification (210X297 mm) • 15- Central Department of the Ministry of Standards of the People's Republic of China, Peigong Consumer Cooperatives Co., Ltd. Yinzi 4 5744 A7 _________B7_ V. Description of the invention (13) Another observation and advantages will be made clear by the following detailed description, which will be made clear through the illustration of an example of the principles of the present invention in conjunction with the accompanying drawings. A brief description of the figures: The present invention will be understood in the following detailed description in conjunction with the drawings, in which The reference number specifies the structural elements, and among them: Figure 1A is a diagram of an Open System Interconnection (0 SI) layer module developed by the International Standards Organization (ISO) to describe the exchange of information between layers. 1 β is a diagram of an example of an Ethernet packet, which is conventionally used to transmit data on the network. Figure 1 C shows a system architecture of a conventional Ethernet media access controller (MAC). Figure 2 The architecture diagram of a traffic-based medium access controller (MAC) according to an embodiment of the present invention. Figure 3 is a diagram of the transmission, management and reception functions performed by a logical core according to an embodiment of the present invention Detailed Block Diagram "Fig. 4 is a block diagram of the internal structure of a transmitter controller according to an embodiment of the present invention. Fig. 4A is a block diagram of functional blocks included in the transmission LLC interface of Fig. 4 according to an embodiment of the present invention. Detailed block diagram. Figure 4 shows an example of a control register, which can be included in a control register block according to one embodiment of the present invention. Figure 4C shows a number of suitable flags. The flag is enabled and (Xu's first read the notes on the back and then fill in 5 «:? this page} --- ° The size of the paper is applicable to the Chinese National Standard (CNS) Α4 specification (2〗 〇 × 297mm) * 16-ΛΌ / 4 44 Stomach piece ~: Patent application No. 87 10183 9 2.  ; ': I ;; Revised page of the Chinese manual, February 9th, Sept. V. Description of the invention (14) The processing function implemented in the SU P E R M A C T x controller according to the embodiment of the present invention is released. FIG. 4D is a more detailed representation of transmitting a C R C block according to an embodiment of the present invention. Figure 4E shows a common control / data path block to receive sixteen-bit wide data from a suitable multiplexer according to an embodiment of the invention. Figure 4F is a block diagram of the support logic and state machine according to an embodiment of the present invention, the logic and the machine being included in an Ethernet processing block. FIG. 4G is a block diagram showing more detailed functional blocks included in the transmission public block of FIG. 4 according to an embodiment of the present invention. FIG. 5A is a diagram illustrating four packets transmitted via a traffic-based MA C according to an embodiment of the present invention. Fig. 5 B is a state machine diagram, which is implemented in the transmission public block in Fig. 4 according to an embodiment of the present invention. "Fig. 6 is a flowchart showing a data path according to an embodiment of the present invention. The method steps combined in the processing of data. FIG. 7 shows a flowchart to illustrate the steps of the method in combination with control path processing according to an embodiment of the present invention. FIG. 8A is a carrier control state machine (F C S M) included in an Ethernet processing block according to an embodiment of the present invention. FIG. 8B is a frame control state machine (F C S M) included in the E T Η E R processing block according to an embodiment of the present invention. FIG. 9 is a diagram showing a functional block diagram included in a receiver SUPER MAC Rx controller according to an embodiment of the present invention. (Please read the notes on the back before filling in this page)-· I I I I I I Order-------- i? ? Zhang Yidu uses the China 0 standard (CNS) A- 丨 specifications (210 X 297 mm) -17- 457444 _____ B7__ 5. Description of the invention? 5) FIG. 9A is a more detailed block diagram of the L L C interface of the receiver of FIG. 9 according to an embodiment of the present invention. (Please read the precautions on the back before filling this page.) Figure 9B shows an example of a flag included in a receiver control register according to an embodiment of the present invention. FIG. 9C is a more detailed block diagram of the structure contained in the receiver F C / G Μ ϊ I of FIG. 9 according to an embodiment of the present invention. Fig. 9 D is a block diagram showing a more detailed functional block included in a receiving public block according to an embodiment of the present invention-Fig. 10 is a flow-based MAC according to an embodiment of the present invention Flow chart showing the data flow on the receiving side. Fig. 11 is a flowchart showing steps of a method of transmission control in parallel with data processing according to an embodiment of the present invention. Fig. 12 is a state machine for processing execution of the receiver control block of Fig. 9 according to one embodiment of the present invention. FIG. 13 illustrates a packet generator architecture user interface according to an embodiment of the present invention to construct packet data before transmission. Figure 14 shows an example of a packet definition user interface to define the packet characteristics of an embodiment of the present invention. FIG. 15A shows a user interface window as one of the states of transmitting and receiving according to an embodiment of the present invention. Figure 15B is a graphical architecture window shown as an architectural graphics attribute according to an embodiment of the present invention. FIG. 16 is a view showing a received data buffer window as one of the displayed packet data according to an embodiment of the present invention. FIG. 17 is a view showing the management of data received by a receiver according to an embodiment of the present invention. One packet processor rack with filtering function _ 乂 paper & degree applicable to China 阉 national standard (CNSM4 specifications (210 X 297 public "")-18-457444 A7 B7 ^^ printed by Bei Vi Consumer Cooperatives 5i V. Description of the invention ( 16) 1 1 Window □ 〇1 1 Figure 18 is a block diagram of a computer system according to the embodiment of the present invention—an embodiment 1 1 I Example computer system 〇1; '· * if 1 1 Main component comparison table; 1 1 0 1 Network data system bus power 1 ψ 1 1 5 0 Media access controller (Μ AC) • Λ 1 μ 1 1 0 4 Network data bus interface controller 1 1 0 TX Network flow management FIF 0 Controller Τί 1 1 1 0 6 Multiple packet series FIF 0 TX 1 i 1 0 8 Multi-packet Series FIF 〇RX 1 I 1 1 2 RX Network Traffic Management FIF 〇Controller 1 Order 1 1 1 4 a β — RISC Stream Processor 1 1 1 1 8 a TX Ultra M AC Controller 1 1 1 1 7 Ultra M AC Management 1! 1 2 0 RX Ultra M AC Controller Line I 1 4 0 Physical Media i 1 4 1 Physical Media ί 1 0 2 Management Control Bus 1 1 1 2 2 Flow Control Bus Interface Control 1 j 1 2 4 Parallel event processor (PEP) 1 I 1 2 5 Packet buffer 1 1 1 1 2 6 Instruction and status register 1 1 1 2 8 Statistics counter 1 1 f CNS Λ4 specification (210X2W mm). 19, 4574 44 Δ7 Α7 Β7:. -, i ''! 't subscript it1- Bureau κ-ΐ Consumption printed by Hezhusha V. Invention description (17) \ 1 1 3 0 Programmable counter 1 I 1 1 4 b β — RISC stream processor 1 1 -2 2 0 Transfer male 3 / L αχ jpp block 1 1 2 1 0 Transfer control block-: J · 1 2 1 2 Ether 1 1 2 1 6 Back off 1! 2 1 4 Delay term 1 Introduction Μ i 2 0 2 Teleport LLC plane XLLC — Ϊ FC η.  I 2 0 4 transmit CRCX mt — CRCH 1 1 2 0 6 transmit FC / G Μ 1 1 XFC — G Μ 1 1 1 I 2 0 8 decoder 1 I 2 5 2 transmit control register ΐ 1 block 1 Order I 2 5 0 Data transfer block 1 1 2 5 4 Area control logic 1 1 3 0 2 Instruction register 1 I 3 0 4 Delay period register line I 3 0 6 Slot register 1 I 1 3 0 8 Retry limit register 1 1 3 1 0 Programmable minimum / 1 = 1 Fetch large packet size register 1 1 2 5 8 CRC calculation U M X 1 I 2 5 6 Data path 1 1 2 6 0 Multiplexer 1 1 2 6 3 -9 6 3 1 0 Gigabit Media Independent-JL- > Interface (G M 1 1) 1 1 2 6 2, 9 6 2 Fiber Optic Ultra Far 1 1 1 Paper Size Applicable in ΚΚΐ: Standard Humble (CNS) Λ4 gauge (2〗 〇297297 mm). 20- β-y 4 7 4 44 A7 B7. --Central market only eliminates the printing of the bamboo company. 5. Description of invention ¢ 8) I! 2 6 1 Command control / data path 1 l 2 6 4 State machine support logic 1 I 2 6 5 Frame control S Μ (FCS Μ) 1 2 6 6 Carrier Control S Μ (CCS Μ) 1 I Please 1 2 8 4 9 8 4  Sigh computer-Ϊ and 1 1 2 8 2 9 8 2 latency and octal counter-¾ 1! 2 8 0 9 8 0 support logical block -f: 1 I 9 0 2 receiver LCC interface RLLC _ IFC ' r:! j.                     1 9 0 4 Receiver CRC check LCV — CRC Τί 1 1 9 0 6 Receiver FC / G Μ 1 1 RFC -G Μ 1 1 1 I 9 0 8 Decoder i 1 9 1 0 Receiver control block 1 Order I 9 2 0 Receiver public 1 block 1 1 9 5 4 Receiver public logic 1 f 9 5 0 Data transfer block 1 I 9 5 2 Receiver control register line 1 8 1 6 Microprocessor i! 1 8 2 0 RA Μ 1 1 8 2 2 R 0 Μ 1 1 8 1 8 Memory bus 1 I 1 8 2 6 KBC 1 1 I 1 8 2 4 Peripheral bus 1 i 1 8 1 4 key * n.  Tray 1 1 1 1 1 This paper is based on the standard in the Sichuan province. {CNS) A4 specifications {210/297 mm) A7 457444 B7 5. Description of the invention (I9) Detailed description of the preferred embodiment: The present invention is described as a High-speed Ethernet media access control layered circuit core and a method for processing packet data in a packet-by-packet manner * This method allows simultaneous processing of data information and combined control information. _ Also revealed a media access controller, which is particularly suitable for performing packet-to-packet traffic management and properly performing proficient network diagnostic tests. In the following description, many specific details are set to provide a complete understanding of the present invention. For those skilled in the art, however, the present invention can be carried out without some or these special details. In some cases, the well-known processing operations are unnecessary weirdness that makes the present invention unchanged and have not been described in detail. 0 Figure 2 is a flow-based media access controller (MA C) 1 5 0 According to the architecture diagram, the controller is used as a high-speed transmission according to an embodiment of the present invention. In a preferred embodiment, gigabit speed Ethernet transmission is considered. However, one noticeable advantage is that the architecture can be applied equally to other transmission protocols as well as both higher and lower speed transmissions. As shown in Figure 2, the system interfaces with a network data system bus 101 and a management / control bus 102. Among them, 101 processes both data and control information, and 102 transmits control. And management information. In terms of advantages, since the data is transmitted through the network data system bus 1101, it should be processed by various processing blocks based on the traffic MA C 150, and the control information can also be streamed through the network data system at the same time. Row 101 and pass. It is important to understand the type of parallel processing provided at any given time in L ------- I-- ^ 1.  I,-II --- _-I I-Ding 1 ^ 1 ^ 1. ---. . . .  Λν * ΐ Vo continued f.  . w ^. li'lrj. ; ί. 4-4ί. ^ 1Η 'this page) I. · '.  . --- 1--: Light " 9 industrial and consumer cooperation ^ print " this paper & standard SK family standard low (CNS) Λ4 now (210x29? Mm) -22- 7-144 A? B7 V. Description of the Invention 卯) The ability to change processing variables based on the traffic-based MAC within 150 (although the packet data is being processed). For example, suppose that data is being received from the upper L L C layer and that the data is being processed through various processing blocks. One of the antecedent columns and one CR C column are joined to form a packet. Because the traffic is based on the parallel processing characteristics of MA C 1 50, control information can be synchronized through the network data system bus 1 101 to modify the portion of the packet that has not yet been processed. Then, the parallel processing characteristics of the flow-based MA C 150 can transmit appropriate controls to change the designated processing variables while the data is still being processed. First refer to the transmitting side. When data starts to be initially received from the upper L L C layer through the network data system bus 1 0 1, the data is transferred to a network data bus interface controller (B I C) 104. In this embodiment, the network data B I C 1 04 may be any appropriate interface controller such as a slave interface and a direct memory access (DMA) onboard interface. As shown, a first data / control path 1 4 4 a and a second data / control path 1 4 4 b can be used when high-efficiency switching is required for traffic-based MAC 1 50. Connect the network data bus interface 101 to the network data BIC 104. For example, the first data / control path 1 4 4 a may be used to perform the transfer from the upper LLC layer to the traffic-based MA C 1 50 and the second data / control path 1 4 4 b may be used Use the execution-based traffic based on MAC 1 50 to transfer to the lower-level LLC layer. Of course, it is also considered that this single bidirectional data / control path can be used to perform the control and data transfer described later. This paper is used in the standard ^^: house standard 绛 ((:? ^) Six 4 specifications (210 ,;! 97 mm) -23-. . . ^^ '^^! 1'. , 'Of. ;1-*. ''-this. Item 4 > | * 1- :, large. 玎) Booking: · 457444 A7 B7 " f: printed by Aphibe K2 Consumer Cooperative; ^ V. Description of the invention) 1 1 — Once the data is transmitted to the network data by the white network data system bus 1 1 BIC At 14:00, the data can be appropriately transferred after the data is a multi-packet 1 1 I queue FIF 〇TX 1 0 6 —- In general * 1 JFIF 〇TX 1 0 6 plays — as a hold will be sent from the upper layer '•. 'Λ 1 1 LLC layer and the data transmitted via the network data system bus 1 0 1 bus iTt i C in this embodiment FIF 〇Τ X 1 0 6 1ST Take% 1 1 I have storage up to ten One or more packet data D. This is a significant improvement on the structure of the conventional single ϊ ϊ t 1 I packet FIF 〇 structure and the traditional structure of the conventional structure is too%! Gigabit speed (Ti 1 1 ie + 1 0 0 0 Μ b PS) Larger storage of increased traffic generated 1 1 Demand 0 1 I — Once an appropriate number of g of packets are buffered into FIF 0 1 Order Ding X 1 0 6 o'clock— 'Network traffic management FIF 〇TX controller 1 1 1 1 0 implemented to manage white FIF 〇TX 1 0 6 and fast stream 1 I in — micro RISC stream processor 1 1 4 a Packet 〇 at a higher level I 1 j network flow management FIF 〇 TX control 1 1 0 can be responsible for adjusting the sequence of the data such as audio jtas, video, graphics, and other forms of data being transmitted through the network. 0 In this way, based on traffic Μ AC 1 5 0 Can be at the same time at 1 The internal stream has multiple simultaneous 1 data streams via FIF 〇 丁 X 1 0 6 0 Among them — the feature is when the packet is being whitened 1 IFIF 〇 丁 X 1 0 6 Any — special packets can be received at 1 I It is skipped without reading the entire packet. 0 In another feature, a packet 1 1 can be whitened by keeping the designated packet for a stylized time 1 1 FIF 〇TX 1 0 6 Medium m transmission e Among the other features—> 1 1 1 This paper music scale is far away in the middle of China® family standard 3M CNS) 4 specifications (2 丨 0X29 "? mm) -24- 4574 44 A7 B7 ΟΛΙ. The medium-sized sample exemption β is eliminated in the cooperative printing " V. Description of the invention P-) 1 I- Once read into FIF 〇 丁 X 1 0 6 The packet can be transmitted to the 1 1 R IS C stream processor 11 4 a before > and 1 was taken out from 1 1 IFIF 0 TX 1 0 6 at a time. In another embodiment, the network flow management FIF 0 TX controller · +-'% 1 1 1 10 is suitable for — V * The bad sequence is coded by Φπη strategy and calculated in each frame received by the upper white layer LLC layer in IFIF 0 TX 1 0 6: i.  • δ 1 Ϊ (frame). The loop sequence numbering strategy is best assigned to the first box of "\ 1 I" with a "1 '", and up to all-a preset number (such as 1, 2, 3, too A 4, 5 , 6 t 7… 2 0) while referring to 71 1 1 in a sequential number-up manner, set a number to each—box 0. In this example, the preset number is “2 0”. 1 I — once as large as 2 When the frame of 0 is received at FIF 0 TX 1 0 6, the next received frame of 1 I will encode ηπΙΟ as »» 1 ”again. Then, the numbering strategy 1 is scheduled to be cycled 1 1 Therefore, when Tian transfers traffic to the receiving base 1 AC 1 50, the network traffic management F IF 0 D X controller 1 1 0 will retain the finger 1 t is set to the number of each frame and will therefore confirm the number of frames that may be offline I in the collision. For example, if the number of frames g "5" is related to one collision, frames 5-2 0 Can be directly stored (buffered) at-1 1 F IF TX 0 106 and directly transmitted. As a result, when the transmission is positive-1 1, the frame stored in F IF 〇TX 1 0 6 will be "not taken out by a large amount of 1" until it is marked with a confirmation of successful transmission (A ck). 1 1 C received by the receiving station. If a collision occurs > a standard backoff (1 1) operation is defined in the 80 2 * 3 standard. 1 1 In another embodiment, the control information can be combined in I 1 1 paper if, and the size is used: standard interpretation (CNS) Λ4 specification (210X 297 Gong) -25- 4574 4 A7 B? Ί; θ. ¾. In the ν 桴 汍 round, only -τ · consumer capital is combined. Printed by the press " V. Description of the invention p) FIFO Tx106 buffered in the packet. In this way, the processing variables can be modified on a pipeline-by-packet basis. For example ... the splice control information may include a confirmation of the modification of the processing variable and the information as a special packet to pick out a modification. The advantage is that it has an intelligent network traffic management FIFO Tx controller 11 and uses network management and combined with test protocols. Although it is rare to require processing variables that change for each successive packet, its advantage is that it is a powerful feature to have the ability to modify processing variables for a given packet in the packet stream. Once the network traffic management FIFO Tx controller 11 performs any requested processing based on the received control information, the micro RIS C stream processor 1 1 4 a performs various processing and data filtering tasks well. For example, the micro-RI SC stream processor 1 1 4a operates in a sequential manner to modify the data stream characteristics. Ideally, the micro-RISC stream processor operates on 32-bit characters based on the flow-based M A C 150 to efficiently process information to perform performance at gigabit speeds. Further, the instruction preferably triggers the byte stream. In this embodiment, the micro RIS C stream processor 1 1 4 a is adapted to operate in different addressing modes such as the related byte count mode. Internally, the micro RIS C stream processor 1 1 4 a preferably has a set of general purpose registers, data structure registers, and special function units. For example, the functional unit may include an ALU, a count accumulator, and a checksum calculation unit. Further, the micro RISC stream processor 1 1 4 a should preferably have the ability to provide additional flexibility and improved performance under conditions such as branching and loop mode. ”Finally, the processing means I ----, ------ Guang ------ Order ------ line (-, " wenu rvefIf! Ff " 3 million) This paper music scale applies to the prisoner S family standard rate () A4 specifications (2 丨 (V (〆297 公 漦) -26- A7 B7 V. Description of the invention 0) The micro RISC stream processor 1 1 4 a may include some inventive packet bar control. The control examples include: CUT, CLEAR, COPY, APPEND, INSEERT, AND, OR, XOR, etc. to confirm header generation, separate data and headers: IP_CHK S UM check and length calculation. Still referring to FIG. 2, once the appropriate data and control information is processed in the micro R Ϊ SC stream processor 1 1 4 a, the data is transmitted to a SUPERMAC Tx controller 1 1 8 via a data path 1 13 a The controller is preferably a state machine that is structured to process the packets received from the micro RISC stream processor 1 1 4 a and output the processed packets to a physical (PHY) medium 1 40. As will be described in detail below, the transmission SUPERMAC Tx controller 1 1 8 will mainly be connected as a proper hook to perform management tasks and handle the modification of the requested packet structure. In this way, various packet modification and management operations can be performed well using the traffic-based MAC 150. :-, ^ However, the Central Bureau of quasi-government has only eliminated 3 cooperative printing ii. w2iJL: '-*', r: 之 '; ί. δ · ίίterm -fi ^ ll-. vlj Benshi ') line For example, SUPERMAC Tx controller 1 18 is best adapted to be processed in a sequential packet-by-packet manner, such as "cancel enable" first append, " cancel enable "CRC append, modify (such as Customized city) Internal packet gap (IPG), and packet modification stylized to a minimum packet size (such as enlarging or reducing a standard 64-byte packet to any arbitrary number). In this embodiment, packet modification control Synchronous transmission from a micro RISC stream processor 1 14a to a SUPERMAC Tx controller via a control path 1 1 3 b 1 18 This paper size 14 uses the SK family standard CNS) Λ4 grid (210x297 mm) -27 -457444 A7 ____ V. Invention Description). As mentioned above, the ability to simultaneously transmit control information (such as path 1 1 3 b) while the packet data information (such as path 1 1 3 a) is being processed is allowed The SUPERMAC Tx is the opposite of the conventional system that transmits control and packet information in a sequential manner, and performs modification based on packet connection and packet-based processing. For example, the conventional technology MA C a control The device generally transmits the initial control information that is applied to the packet that is followed by the control information. Then, no change or modification to the packet processing is allowed in a MAC controller. Of course, when the control information is transmitted, the packet information will be Being queued, it will undesirably reduce the processing speed and transmission speed. However, the inventive SUPERMAC D X controller 118 processes packet data and modify processing based on any parallel received control information at the same time. The advantages and features of the controller 118 will be described later. · '. .  r,-屮 次 打 ^ 巧 · ^ -1'Moxibustion cooperation · t-India-Figure 2 also shows a SUPERMAC Tx management block 1 1 7 which is responsible for transmitting SUPERMAC Tx controller 1 18 and receiving Interface between SUPERMAC Rx controllers 120. The SUPERMAC management block 1 17 also interfaces between the network traffic management F I FO Tx controller 1 1 0, the network traffic management FIFO Rx controller 112, and the network data BIC 104. Generally speaking, the function of the SUPERMAC management block 117 is an interface for receiving flow control information, automatic coordination instructions, entity management instructions, and pause frame information (ie, the pause frame serves as a receiving unit to remind a transmitting unit to stop the paper size)迸 Use Chinese S standards (CNS) / \ 4 grid (2 丨 0 X297 mm). 〇8-457444 A7 V. Description of the invention 沣) Stop transmitting data until a receiving buffer is vacated). Another implementation in the SUPERMAC management block 117 is keying, initiation and architecture, synchronous collision, forced transmission, and keying monitoring. Moreover, the SUPERMAC management 1 1 7 is well adapted for self-exemption ... It is transmitted from the SUPERMAC Tx until the FIFO Tx 106 is properly loaded, or a preset time period elapses. The advantage is that this allows the rate at which packets are transmitted to the PHY medium 140 to be precisely controlled. In contrast, the SUPERMAC management block 117 can also be set to be transmitted while the packet is received by the FIFO Tx106. In this embodiment, the SUPERMAC Tx controller 1 1 8 and the SUPERMAC Rx controller 1 20 are shown and bonded to a second micro RI SC stream processor 1 1 4b, which is ideally comprised of a parallel event Processor (PEP) 124 »In this embodiment, appropriately processed events occurring within the SUPERMAC Tx controller 1 1 8 and the SUPERMAC Rx controller 1 20 can be converted into micro RISC stream processors 1 1 4b. In this way, the processing events that occur within the SUPERMAC can be stored in the appropriate statistical counter 128 of the PEP 124. On the receiving side, the micro RISC stream processor 1 1 4 a is also shown to be coupled to the micro RISC stream processor 1 1 4 b to monitor and record traffic that is processed inside and outside MA C 1 50 event. Traditionally, data is self-contained as one of the decoders that decodes the signal into appropriate packets to be received by Rx SUPERMAC J ---. ------ 广 ------ ir ------- ^ ... (^ ΐ ^ ΓΛΐ '·' '**. : '1 ·· 之 ：: is " Jfi, then e'lvJ this U) The paper size chasing the middle ^ pressure home line 4 *. (CNS) Λ4 ^ lattice (2) 0 乂 297 male f) -29- 4574 44 A7 B7 V. Description of the invention θ) Physical (PHY) medium 141. As will be described in detail below, the SUPERMAC Tx controller 120 is generally responsible for, for example, removing the precedence (if the precedence is attached to the transmitting side) from the incoming packet. . .  And, the SUPERMAC Rx controller 120 preferably has the ability to transmit a CRC field to the micro RIS C stream processor 1 1 4 a without performing the conventional removal function. If it occurs, the C R C removal can be performed by the micro RIS C stream processor 1 14a itself before transmitting the transmission packet data to the upper L L C layer. In addition, the SUPERMAC R x controller 12 can also perform IPG capture, stamped reception, and program a minimum and maximum packet size to avoid paddmg at gigabit or greater speeds. A short packet or an error was returned for a large packet. Of course, if desired, pad removal may be performed within the SUPERMAC Rx controller 120. Once SUPERMAC Rx receives a packet from the physical medium 141, the packet will be transmitted to the micro-RISC stream processor 1 1 4 for processing and then to the multiple packet queue F I FO Rxl 08. On the transmitting side, events executed in both the SUPERMAC Rx controller 1 2 0 and the micro RISC stream processor 1 1 4 a are connected to the micro RISC stream processor responsible for the events in the statistics counter 1 2 8 In 114b, it is preferable that the network traffic management FIFO Rx controller 112 further has a number designated to each packet received by the FIFO Rx 108. Because the FIFO Rx controller 112 knows the number assigned to each packet. In this paper scale, gg family standard (CNS) Λ4 specification (210X2 mm) -30- J--. --------- Λ. ------ ‘玎 ------ Μ (1 ?. ?-圮 Please-! ^ 'And irv-' ^^ vt'-M ^ r'i) 45744 4 at B7 5. Invention description), a control signal can be sent to the FI FO Rx controller 1 1 2 to request An individual number of packets stored in FI FO RX 108 will be transmitted (ie, to the LLC layer or PEP 124 for management). -Once the data is removed from the multiple packet queue FIF 0 RX · · 1 08 in a switching environment and transmitted to the network data BIC 1 04, the data will be transmitted to the network data system bus via path 1 1 4 b 1 0 1. Of course, a single two-way data path can be selectively used in paths 144a and 144b. As mentioned above, one advantage of the present invention is its parallel data and control processing architecture. In FIG. 2, the management / control bus 1 02 is generally used to transmit control signals and perform network management tasks through a dedicated full-time control bus interface controller (B I C) order 1 2 2. In this embodiment, the stream B I C 1 2 2 is preferably prepared to transmit control information and perform data management tasks. For example, when performing a network management task, it must pull (ie, filter) individual information packets of information from the packet path being processed via the network data B I C 104. Once the desired packet is confirmed, it can be filtered by the micro RIS C stream processor 1 1 4 b, which is set in the parallel event processor (PEP) 1 2 4. The micro RIS C stream processor 1 1 4 b is also preferably responsible for programming new events, filtering the desired packets and buffering the desired packets in an appropriate buffer. In addition, the micro RISC stream processor 114b has the capability of initial thresholding, alarm generation, and detection of traffic generated as matrix statistics. In addition, the basic paper size of a hardware counter is described in the state ^ 囡 house standard pedigree (CNS) Λ4 specification (2mx 297 mm) -31-457444 A7 B7 V. Description of the invention) Combinations can be provided to take charge of various Processing operations performed by the micro RISC stream processor 1 1 4 b. In this embodiment, the network management operation is generally used to determine the selected network statistics such as traffic, public use, number of collisions, traffic flow characteristics, etc. The advantage is that both Simple Network Management Protocol (SNMP) and Remote Monitoring (RMON) can be implemented via PEP 1 24 in Figure 2. Known for this skill, RMON's surveillance allows a network administrator to analyze various traffic statistics and network variables to understand network error diagnosis, planning, and performance estimation. -° line ί: ϋ. ψ " ^ "-. ι ^ Η-τ Consumer cooperation printing 54 Next, PEP 1 24 includes a creative packet buffer 1 2 5 to store the appropriate packets made by network management protocols such as SNMP and RMON. For example, if the user wants to monitor one of the data streams being processed via the network data BIC 104, the micro RISC stream processors 114a and 114b will filter out and store them in the packet buffer in order. 1 2 5 desired packet in the device. Also included in P E P 1 2 4 is an instruction and status register 1 2 6. For example, the instruction register receives the control signal from the management / control bus 1 102 via the flow control B I C 1 2 2. Also shown are responsible for storing individual events that can occur in the SUPERMAC Tx controller 1 18 'SUPERMAC management block 1 17, SUPERMAC Rx controller 120, micro RISC stream processor 114a, and micro RISC stream processor 114b. Then, when the packet is processed and an event occurs, the event information is streamed to the micro RIS stream processor 1 1 4 b and then stored in a statistical counter. <:? ^) / \ 4 Regulations (210/297 G $) -32- 4 5 ^ 44-4 a 7 B7 Line;-. In the Ministry, ¥ Sample Bureau β ΗConsumer Cooperative Press 1i V. Invention Explanation (30) 1 I 1 2 8 e and> multiple programmable counters 1 3 0 are located in PEP 1 1 I 1 2 4 to record the new event which is now defined but will be defined in the future 0 1 1 In short > The advantages of describing the architecture by referring to FIG. 2 are many. [In short »The ideal architecture has a parallel streamline processing of data and ·: 1¾ t I control information Q In addition» This parallel processing feature is a packet The data is being processed through the first-level data line and the 1 I line data path allows the user to perform the desired management work Λ 1 1 I. The parallel processing feature enables the packet structure to be packetized online and then 1 1 I. Modifications based on packets. However, this desired architecture is believed to be particularly good. The advantages of working well in this similar function can be Using other architectures, J! 1 1 is framed into 0 1 I. Figure 3 Series—- SUP Ε R Μ ACC 0 R Ε 1 1 6 Way 1 I Block Diagram The 1 1 6 contains SU Ρ ER Μ AC Τ X controller 1 Order I 1 1 8 SUPER Μ AC management block 1 1 7 and 1 1 RXSUPER Μ AC controller 1 2 0 Q In an embodiment '1 1 SUPER Μ ACTX controller 1 1 8 contains various state machines 1 I 1 Each is responsible for processing the data received by the upper LLC layer of S, and is responsible for transmitting the packets processed on the line to the physical layer and combining them with appropriate hooks. Similar > SUP ERR ACRX Controller 1 2 0 j 1 on the receiving side communicates with the physical medium 1 4 1 and the micro RISC stream processor 1 1 1 1 4 a and 1 1 4 b and the SUPER M AC management block 1 1 1 1 7 communication e 1 I is implemented here In the example, Su P ER Μ AC manages 1 1 7 and the 1 1 | SUPER Μ AC TX controller 1 1 8 and 1! SUPER Μ ACRX controller 1 2 0 interface for various transmission 1 1 1 This paper size is suitable for Sichuan SS home sample i (CNS) A4 size (210x297 mm) -33- 457444 A7 B7-Final award iv- Bureau RT- Eliminate cooperation printing ^: 5. Description of the invention) 1 1 and the received agreement are synchronized. For example, the t auto-negotiation agreement can be controlled in 1 I S U RP E MR AC management 1 1 7 to synchronize the transmission 11 and the speed of the receiving network to achieve the most efficient and fastest communication speed. For example, if a transmitter has a speed of 1 billion bits and should receive: 1 1 receiver can only receive at 100 M bps, then the transmitter will self = m -M II is set to the minimum speed of the receiver. 0 Auto-negotiation is also described here as 1! I for reference. I Ε E E 0 0 2 3 (U) Standard D 1 1 1 SU Ρ RMAC Management Block 11 7 is responsible for the control when the packet is transmitted from il \ Ben 1 SUPER Μ AC Τ x controller 11 8 to 1 1 P Η Y 14 0. For example, y SUP ERMA C 1 I management block 1 1 7 can communicate with network traffic management FIF 0 Τ X controller 1 1 11 0, the 1 1 0 is connected to multiple packet queue 1 order \ FIF 0 Τ X 1 0 6 When to send data to the micro RISC stream 1 1 processor 1 14a and when to send to SU PER Μ AC TX control 1 1 1 1 8 for transmission. The advantage is that the S UP E R M A C management 1 I 11 7 has control when multiple packet queues F I F 0 TX X 1 0 6 are transmitted by the line or to maintain data. Therefore, once SU PER Μ AC manages 1 1 7 refers to 1 1 FIF 0 TX controller 1 1 0 when the data transmission is appropriate (ie 1 1), a preset number of packets are stored in FIF 0 TX 10 After 6 1 1), the SU PER Μ AC management block 1 1 7 may notify the 1 | transmission is not permitted. On the other hand, the SU PER Μ AC management block 1 1 1 11 7 can also allow RIF 0 TX control 1 1 device 1 1 0 from multiple packet queues FIF 0 TX 1 0 6 when the packet is received. Will seal 1 1 1 this paper size back) 11 ES family standard twin (CNS) Λ4 specifications (2ΗΪ × 297 male t) -34--central *: "-bureau consumer cooperation · Η 印 ^ 4 6 7 4 4 4 A7 _____B? Fifth, the description of the invention) The packet is transmitted. The following is a detailed description of the execution function blocks and processing functions in the SUPERMAC Tx controller 118 (ie the transmitter side) and the SUPERMAC Rx controller 12 (ie the receiver side). · Transmission side Figure 4 is a block diagram of the internal structure of the S U P E RMA C Tx controller 1 1 8 according to an embodiment of the present invention. As shown, a 32-bit wide data path is displayed for transmission to a transmission L L C interface 2 0 2 (XLLC-IFC). In the transmission LLC interface 202, various processing operations can be performed on data to be received from an upper LLC layer. For example, the function of the register included in the transmission LLC interface 202 may include: (1) programming a desired delay period; (2) programming an ideal slot time (ie, Back unit); (3) stylized-retry limit; stylized-minimum and maximum size, etc. Also included in the transmitting L L C interface 200 is a plurality of instruction protocol registers 302 as flags for modifying packet processing according to one embodiment of the present invention. For example, the instruction protocol register 302 also includes flags, which are (1) enabling / disabling enabling a prior generation and appending; (b) enabling / disabling enabling-CRC calculation and addition: (C) Enable / disable enable a carrier expansion requirement (ie * the packet is at least 512 bytes long: (d) control a full duplex mode; (e) enable / disable enable an automatic padding function ; (F) Enable the sampling line function at the beginning; (g) Perform a forced transmission (ie, force a collision to divide ^ i ί line f " '-" Reading Weep -Ben.Jr!' Re-J11 · " This s) This paper size is suitable for Sichuan KSSi: Standard Tianjin (CNS) Λ4 specification (210 × 297 mm) -35 «5 ^-^ ';. 屮 " ^ quasi bureau $ 工 consuming cooperation_printing " ia, A7 B7 V. Description of the invention 垆) Analyze a network response): and (h) enable the transmission process. The data path is described next. According to an embodiment of the present invention, a 16-bit-wide data bus transmits packet information to a transmission CR C 204 (XMT — CRC). _ Once the data is transmitted to the transmission CRC 204, a CRC calculation is either performed or sent out, depending on the setting of the C R C flag contained in the instruction protocol register. It should be understood that while the packet information is being transmitted and the data path is processed downwards, the control information is transmitted synchronously to modify the packet processing at any time. For example, if a packet is being processed in the transmission CRC · 202, and the control information (that is, the flag is set to TRUE = NO CRC) is de-enabled, the CRC is transmitted before the CRC is added. At that time, no CRC will be appended to the transmission CRC 202. Once the data is processed through transmission 204, the 16-bit data should be transmitted to be responsible for processing the received packet information into an appropriate form for transmission through a physical medium. One transfers FC / GMI I 206 (XFC — GMI I) blocks. For example, the described high-speed, traffic-based MA C 1 50 preferably has synchronous transmission in the form of a gigabit media independent interface (GM I I) and in the form of a fiber channel. Of course, it should be understood that the one billion traffic-based MA C 150 is also backward compatible with 10 Mbps systems. For example, transmission is also performed in the form of a media independent interface (M I I), and transmission can also be performed in one form at a time. That is, although it may be synchronous transmission, GM II or fiber channel transmission can be in a range of -1 ^^^^: iv: c-4i.J'h re " '. ^ 本) line paper paper Λ degree in use KS Family Standard (CNS) Λ4 Specification (210X297 mm) -36- 4 5 7 4 4 -l. A7 B7;-'^ .. Ministry ^ 行 kit ^^-7-Consumer Cooperative Cooperative 4,1 Winter five, invention description 04) Time is executed a form. If the 'transmission is performed via a fiber channel, it must perform a suitable fiber channel encoded in the encoder 2008, which receives a 16-bit wide data line and the output-fiber channel special It is a 10-bit wide output. The advantage is that the function performed by the encoder 208 can optionally be performed in a medium-independent transmission F C / GMII 206 without a separate encoder unit. When data is transmitted via blocks 202, 204, and 206, a two-way communication link 2 0 3 is located in block 202 and contains three of these referred to here as Ethernet 112, BACKOFF 216, and DEFER 2 1 4 One of the processing blocks is transmitted between the control blocks 2 1 0 and maintained = further shown are two separate communication bonds 2 5 and 2 7. The 2 5 and 2 7 are individually used as self-transmission control areas. The block 2 10 communicates with the transmission LLC interface 204 and the transmission FC / GMII 206. Generally speaking, the communication bonds 205 and 207 are used to control and modify the processing operations in blocks 104 and 206 based on the following packets followed by packets. ETHER 212 is generally responsible for maintaining the integration of the frames being processed via traffic-based MA C 1 50 by ensuring that the appropriate Ethernet standards for the frames and packets are met. At a higher level, 'ETHER: (a) ensure that the frame is transmitted when the media system is not busy; (b) decide whether a collision occurs; (c) perform a congestion if a collision occurs; (d) decide whether it is needed Carrier expansion; and (6) resending the frame after meeting the delay and backing up. At the packet level, ETHER212 can also: (f) If necessary, generate a prior paper with a suitable heart (material ΰ, Ν5) _Λ 提格 (2mx 297 公 楚) ^ 37- J —— * ---- --A -------, π ----- 1 ^ (^, ^ ¾¾.¾ and then; iw®.Jn again ^-, ν-ΓTaiwan) 45744a A7 B? V. Invention Note (35) '(g) Generate CRC if needed: and (h) Collision check. In one embodiment, the work performed by the ETHER 2 12 is generally performed by a suitable state machine which will be described in more detail below. Of course, the processing performed by ETHER2 12 can be modified at any time in parallel with the data processing by transmitting control information. In some examples, the ability to instantaneously disable the advance and CRC generation can be allowed. Users perform various administrative diagnostics on the network. For example, when both antecedent and C R C are disabled, the traffic-based MAC 1 50 will completely transmit the original data without processing. With this architecture, important diagnostic tests and management operations can be performed on the transmitted data (ie, the data is transmitted without advance and C R C). In another embodiment, a user can load a one-bit pattern sequence to perform a phase-locked loop (PLL) inspection, as well as various laser optical inspections. In fact, the testing functions described above can be accomplished by meeting the appropriate software users who perform the various hooks enabled by SUPERMAC CORE 116. In addition, the above-mentioned tests can be performed without using expensive conventional test equipment.

As mentioned above, the 1 transmission control block 2 1 0 also includes the BACKOFF block 2 1 6. The 2 1 6 is preferably responsible for determining the time that the transmitter must wait after a collision occurs and before a retransmission occurs. Generally speaking | the back-off time is expressed in "back-off units", and the total elapsed time before the attempt to resend is a fixed number of back-off units ° To determine the certain number of "back-off units", the conveyor must wait until One transmission is resent, one IEEE paper size is sent to Kis S in the state: standard low (CNS) Λ4 specification i 2I0x public address) .38- ---''-------- P ------ π ------ Ml ------ I (^-. ν, ^ .- ϊ'ν-ϋΙΙν 之.; ia: ui-.Jf!. ^. ^-l-:,-i .. )) 4574 44 A7 B7 V. Description of the invention Gentry) Standard algorithms can be used to calculate the back-off unit. Although other suitable algorithms can be used to count the number of back-off units, it is best to implement a cut-off binary index BACKOFF (TBEB) algorithm. Further, it is very important that the "back-off unit" can also become a "time slot". Conventionally, the time slot is a fixed time period (that is, 5 1) for a transmission speed network of 10 and 100 Mb p S. 2 bit time). A particular advantage of the present invention is that the "time slot" can be programmed with any suitable number of bit times. For example, for a gigabit Ethernet transmission, a "time slot" can be any number of bytes up to one that can be an ideal number of bytes of 5 1 2 bytes of time And stylized. For example, after an unsuccessful attempt at transmission, the transmitter will back off and retry the transmission up to 16 times before the error is received (that is, the medium is very busy or cut off). The advantage is that the programmability of the retry limit further optimizes network traffic. The DEFER block 2 14 responsible for maintaining the internal packet gap (I PGs) according to an embodiment of the present invention is also shown. For example, when it is determined that the signal is on the medium (that is, the medium is busy), the transmission is performed. Shouldn't try for a while. In one embodiment, the time period will be calculated according to the IEEE standard algorithm called "2/3 rule". For the 2/3 rule, please refer to the IEEE 802.3 standard "Carrier Delay Section 4. 2. 3. 2.1 'Page 26" (IS0 / IEC 8802-3: 1996 (E) ANS / IEEE). Generally speaking, under the 2/3 rule, J --- r ------ of '------ subscription ------ line (^? 闻 ^' 背 5 & Note Read the matter again ||-:-'Bonishi' The guilt scale of this paper is in use (CNS) Λ4 specification (210 × 297 males) -39- ^ 57444 A7 B7: Jf ^ · Bureau M Hezhu: ^ 印 5 ^ 5 、 Invention 07) 1 PG carrier detection (for example, for decision-making when a collision occurs) is performed at a period of 2/3 of the internal packet gap (I PG), and no-carrier detection is at the last 1 / 3 is executed during the IPG cycle. Traditionally, the 2/3 rule followed when "receiving" was, and "transmitting". It was followed, and the IPG system was set to about 96 bit times or more. On the other hand, when "receiving" In the next "receiving", the IPG can be set to 96-bit time. In this embodiment, since the IPG can be made longer or shorter than the 96-bit time, the IPG can be preferably set to Stylized. Because the circulation can be increased by reducing 1 PG when fewer collisions are detected. A display will transfer the public block 2 2 0 and the transmission control block 2 1 via a two-way bond 211. "Communication 0" In this embodiment, the public block 2 2 0 is transmitted when appropriate control is transmitted to determine the state of the traffic-based MAC 1 50 at any appropriate time to maintain some status counters for consistent status reports. And, the transmission public block has a transmission latency (via an appropriate counter), which is defined as the length of "waiting time" that elapses before transmission is allowed on the network. The transmission public block is prepared to record an eighth Carry count, retry status Counting, a public factor that determines the percentage of network use, a bit of information, a uniform energy flag, a single collision flag (eg, determining whether a packet encounters a single collision), a multiple collision flag, A late collision flag (eg, a collision occurs after a specific time window has expired), a carrier induction error (which applies only to half duplex), and a flag indicating whether the upper LLC layer cannot provide any requested information One is the overflow flag.; N ^-nh and the note " remember this page again)

A order line This paper music scale is applicable to Chinese SS family standard interpretation (CNS) Λ4 specification (21 (1X 297 mm) -40- 5 4

Λ A A '' ^ A? __B7 V. Description of the invention The following table shows various status data, which is generated by transmitting the public block 2 2 0 in Figure 4 in the described embodiment. Of course, the transmission public block can be constructed to obtain other data. Generally speaking, common design devices are generally reloaded for short flows and overflows, and the best settings are ... Measured with 64 bytes. -^^-1 ^-., 71¾ Henry, fi-? RiA ···-'" Π)-· .τ · τ Line table I xmt2hst stat xmtEnabled The transmitter is enabled col Single One retry attempt colMultiplc multiple In a retry colLate collision occurred after the end of the collision window errorCRS Either the carrier sensor frame did not occur, or it came during transmission but disappeared errorllnderflow, hst2xmt _data_rdy 'RetryCnt when requested but retry count xmtLatency when transmitted The byte count is in this packet (the same is true for the latency counter) ctrO verflow counter overcurrent (can be applied to both the byte counter and the latency counter) U tilFactor public factor paper position 迖 + house mark CN (CNS) 8 4 specifications (210x297 mm) -41-A7 4 57 4 44 V. Inventive clock) A state machine diagram further shows some functions of transmitting the public block 2 2 0 as described below with reference to FIG. 5A. FIG. 4A is a more detailed block diagram of work and energy contained in the transmission L L C interface 200 of FIG. 4 according to an embodiment of the present invention. For example, a 32-bit wide L L C data path is rotated to the data transmission block 250, and the 250 also receives 4-byte control information from a control signal (X C S) bus. In addition, a control (CTL) bus 2 5 3 is used to transmit control information to a transmission control register block 2 from the multi-packet FIFO Tx106 and the micro RISC traffic processor 1 1 4 (Figure 2). 5 2. In this embodiment, the control bus 1 5 3 is best confirmed with “hsi2xmt_ctr. In this way, when the appropriate control signal is transmitted to a control register 2 5 2 via the control bus 2 5 3, The appropriate register in the register block 2 5 2 can be selected and set in the SUPERMAC Tx controller of Fig. 3 to enable the appropriate ideal processing function. Further shown is a 5-bit wide control signal XCS entry Control register block 2 5 2, the 2 5 2 is used as a selection register and set the number of latches of the selected register. This is also included in the transmission LLC interface 2 0 2 area control Logical block 2 54, which can receive a 2-bit wide XCS control signal that defines the boundary and packet transmission mode. The following is an example of Table 2 to show the various transmission control signals, which can be based on One embodiment of the present invention is executed. ------------ Two ί -------- Subscribe ------ Exercise jj (-'.''- "-" f: And. " " 宇 ^^} ϋ-; · '·-中 -V 标 ^^ Cooperation. 7i Printing and paper paper scale follow-up + ¾ ¾ Standard (CNS) Λ4 specification (210X29: / Mm) -42- 457444 A7 B7 Table 2 hst2xmt xcs testMode Put the transmitter into test mode-hstClk carries the host clock cmd Valid The instruction of hst2xmt_ctl bus is valid retCntValid retry counter is at hst2xmt_ctl bus slotTimeV alid to the slot The hst2xnu_ctl bus defPeriodValid delay period is hst2xmt_ctl bus pktValid The packet is valid and transmission can start idle Valid When the transmitter is interposed, the host must control TXD byteEnables The corresponding bit is in the hst2xmt_data bus. The valid klndex KGEN TX_EN or TX_ER output Source) "^ • κPlease ;: ν" "-. &Quot; 汔 事 ^ Jl1, Qiaoben ί) V. Description of the invention 妗 〇) S '!': Blowing n; i,-" i3c-T & quot 'fi ·' cooperation, shirt printing " In one embodiment, before performing data transmission, a handshake is matched between the traffic-based MA C 1 50 and the upper LLC layer. For example In other words, a suitable handshake can be a signal transmitted by the LLC layer to indicate that the data is prepared (eg, flag h 5 (2 and 1 ^ _. 13 _] * (17) and one by 1 ^ people based on .flow (150 paper size legacy in use ® S family standard (CNS) Λ4 specification (210X 297 mm) -43- 457444 " The work of the Central Conservation Bureau was cancelled by the combination of the right of the bamboo and the wooden seal A7 B7 5. The description of the invention 1) was transmitted and said that the 1 50 was a ready signal for the data. Once the appropriate flag has been set and the handshake has been confirmed (ie, the packet is valid) *, the data can be passed through the data bus between the upper LLC layer and the traffic-based MAC 1 50 (ie , ... hst2xmt_dat: a). For reference, FIG. 4A shows that the data leaves the transmission area 255 and the transmission CRC 204 as described in FIG. 4 and the control information system including the appropriate register selection performed in the area control logic 252. It is transmitted to the transmission control block 2 10 °. As described above, the control information block in the transmission control register block 2 5 2 is then used by ETHER 2 1 2 and is keyed by communication 2 0 3, 2 0 5 and 2 0 7 and sequentially return to the data processing traffic. For example, if the register in the transfer control register block 2 5 2 is set to avoid appending a data that is going to the SUPERMAC Tx controller 118 first, then the processing will be performed in ETHER 212 and afterwards It is transmitted back to the transmission LLC interface 202 via the communication link 203 »Then, the area control logic 2 5 4 also receives control from the transmission control block 2 10 • The 210 is from ETHER 212. In this way, the appropriately set execution of this bit in the control register block 252 is independent and is synchronized with the data being transmitted and processed through the data path. To further emphasize the advantages of this parallel processing control and data 'it is necessary to understand that while the data is being processed,' control information can be received to modify the data processing without waiting for the data to be fully processed. This paper is used by the prisoner S family standard (CNS) Λ4 specification (210 297 mm) -44-· .1¾¾ 汴 And " -Read this book item 4JA'1VV permanent page) ΛΤ · 457444 A7 ______ B, V. Description of the invention 啐) In this embodiment, the area control logic 2 5 4 has "to and from" the communication of the control block 210 to set the appropriate variables of the BACKOFF block 216 and the DEFER block 214. Other signals that can be used include, for example, "xmt2hst_abort", which can be transmitted directly to ETHER 212 to cut off any current transmission. Table 3 below shows an example of the control signal " xmt2hst_rsp ", which comes directly from the control bus 2 5 3. .--- r ------ " —— < Acuity.?-" " Behind the scenes, read the matter again .'- ':: Too ^)-" ^ 龙 " Only two elimination 纥 cooperation 印 印 ^ This paper scale into the middle of Sichuan Suppose. (CNS) Λ4 specification (2 | 〇y297 public 牦) -45- A? __ _B7 V. Description of the invention) Table 3 xmt2hst_rsp xmtClk Transmitter clock ... fdplx Full-duplex mode xmtOK Transmission completed (may have errors) ) XmtCol transmitter conflict (can be used to reset the FIF 0 indicator) latercy Valid The information of the bit counter is transmission potential) octs Valid The status bus (xmt2hst_stat (23: i3) carries the carry count information) (00) util Valid (01) (10) Counter work substream overcurrent loadData This signal can be used by the host operating at half the frequency and can optionally become xmt2hst_rdy4data (r-'^ K ^ 11: nlp; of ^- Henry Xiang replied with the present cigarette) line 4 ', ^ leather ^ negative ^ eliminated in cooperation /; 1 ^ ^ Figure 4B shows the control register described later, the register is according to an embodiment of the present invention Included in control register block 2 5 2 = as shown 'an instruction protocol register 3 0 2 and a delay period register 3 0 4' Time slot register 3 06, a retry limit register 3 0 8 and the paper scale (CNS) Λ4 specification (2IGX297 Gongchu) -46- 457444 A7 V. Description of the invention) A programmable The minimum / maximum packet size register 3 10 is included in the transmission control register block 2 5 2. Therefore, when the selected control signals C T L and X C S are transferred to transmit the transmission control register block 2 5 2, the properties of the selected register can be changed. In this way, the processing performed by SUPERMAC Tx can be modified. For example, if a user wants to program a custom retry limit, the retry limit register 308 can be selected by transmitting a control signal and an ideal gate time. Once gated, a new retry limit is programmed into the slave limit register 3 0 8 »In this embodiment, the retry limit register 3 0 8 can be a five-bit temporary register The register can be programmed to become any ideal "number" between 0 and 31. The programmable characteristics of the retry limit register 3 0 8 are special in performing network traffic management. useful. For example, if the "fixed" 802.3 standard retry limit "1 6" will cause too many packets to be dropped, the retry limit can simply be adjusted upwards to reduce the number of dropped packets. Similarly, the delay register 3 0 4 can be a 3-bit register (or any suitable size register). The register is preferably programmable for any number of times between about 32 bits and about The number between 1 0 2 4 bit times, and more preferably between about 3 2 bit times and about 5 1 2 bit times, and most preferably between about 32 bit times and g about 1 Between 2 and 8 bit times. In one example, the delay period register 3 0 4 can be programmed to approximately 96 bits. Because the delay period is generally the internal packet gap (IPG), when a user programs the delay period, the IPG that is being transmitted will be modified. For this IPG to change the size of this paper, use the KS Tsukasa Standard (CNS) Λ4 specification (210X297 male f > -47- I-: ------ R ------ ΪΤ ---- -^ (-• 1-'..?-| ( <:. Please 3 £ 'of': 1 ^ Yes. Item again ^ >-; 'Benwan') c " Ministry & Broadcasting Bureau Cooperatives' ^ 457444 A7 B7 _ V. Description of Invention 忡) As a result, the B-rate of the packet being transmitted can be increased or decreased. With this architecture, the time slot can be programmed to any number between about 2 bytes and about 5 10 bytes. In this embodiment, the 'time slot register 3 0 6 is preferably an 8-bit register 9 (or any appropriate-sized register'). For example, when the 8-bit register The registers are all one (that is, 1 1 1 1 1 1 1 1 1 1), then the total number of bits is 2 5 5 bits. When the 2 5 5 bit system is multiplied by 16 time slots 'The total number of bits will be 4080 bits or 510 bytes. Finally, the programmable minimum / maximum packet size register 3 1 0 allows the user to program the ideal size of the transmitted packet. For example' A conventionally defined packet has a fixed minimum size of 64 bytes. However, after considering that a packet transmitted over a high-speed network (eg, a gigabit speed or greater) may require a larger minimum Packet ruler In order to adapt to this possibility, a programmable minimum / maximum packet register is advantageously provided so that the user can modify the minimum packet size of the program. Figure 4C shows the contents of the instruction protocol register 3 0 2 * The 3 0 2 Contains some suitable flags to enable and disable the processing functions performed in the SUPERMAC TX controller 118. The example flags are as follows: (1) The Uniform Energy X Μ 3 2 0 flag is Data transfer processing: (2) —The full-duplex 322 flag enables the full-duplex function (in full-duplex, the carrier sensing is ignored); (3) —the autopad flag to set the extra bits The meta pad is packed in the packet to meet a minimum required size: (4) a non-CRC326 flag to deactivate the calculation that enables the CRC; (5) —the non-leading 328 flag ^^^^ 1 ^ mv l · ^ ϋ— —.1 t ^ i ^ t \ r < ”And .cfis ¥ '' ri4 ^ {VJ ^ i) KS Family Standard Net (CNS) Λ4 Specification (210 乂 297 mm) -48- 457444 A 7 B7 V. Invention Description It is marked with the deletion of the antecedent addition to the beginning of the packet: (6) —The non-carrier extension 3 3 0 flag is used to de-enable a minimum 5 1 2 byte carrier packet size, which is one billion bits The Yuan Ethernet standard is required under IEEE 802 · 3ζ; (7) —Initial sampling 'line 3 3 2 flag is used to start sampling the transmission line and generate statistics for block 2 2 0: and (8) — Forced transfer 3 3 4 flag as a forced transfer regardless of whether the medium is busy or not. The advantage is that when the appropriate register is set within the control register block 2 5 2 then the control register is being controlled. The ideal packet structure set in the memory block 2 52 can be manipulated while the data is being transmitted. Figure 4D shows a more detailed transmission CRC 2 0 4 (Figure 4) according to an embodiment of the present invention. As shown, a 16-bit wide data path is transmitted from the data transmission block 2 50 in FIG. 4A, and is synchronized via the CTC calculation unit 2 58 to The data path 2 5 6 is transmitted. In the CRC calculation unit 2 58, a standard periodic repetition check calculation is performed according to the IEEE 802.3 defining the algorithm. However, as mentioned above, if the CRC does not need to If the standard 3 2 6 is set to TRUE (as shown in Figure 4C), the non-CRC calculation will be performed or added to the packet being transmitted in the data transmission block 250. At this point • An appropriate CRC calculation After being executed and appended, if necessary, and the data is transmitted via the data path 2 5 6 | the packet information and CRC calculation unit via the data path will be transmitted to an appropriate multiplexer 2 60. Once Being multiplexed, a single _16-bit wide data path will lead to one of the shared control data paths J— '丨 _------ & ----- 1T-- ---- 0 The scale of this paper music is suitable for China ’s family inferiority (CNS) Λ4 specification (2.0 × 297 mm) -49-457444 Α7 Β7 βϋνΐ .-- 'ί'. ^ Ϊ́ί-. Bureau; Cooperation it printed ^ V. Description of the invention β) diameter 2 6 1. Figure 4 E shows a shared control / information that receives the 16-bit wide data from the multiplexer 2 60. Material path 261. When the data is received, the data is appropriately transcoded to one or two of the identified physical media interface units. For example, a media interface unit may be a billion-bit interface independent The interface (GM II) 2 6 3 and the other may be a fiber channel interface (FC-1) 262. As mentioned above, the MAC 1 50 based on the gigabit traffic in Figure 2 is completely backward compatible and can therefore be transmitted via a media independent interface (MI I). Therefore, it should be understood that the aforementioned media operations can be performed simultaneously or one at a time. Also shown is a shared control / data path 2 6 1 that transmits control block 2 10 and receives control information to confirm which operation mode is ideal. In general, FC-1, GMI I *, and MI I define this electronic standard and the mechanical interface required between flow-based MA C 1 50 and a selected physical medium. In this embodiment, the signal outputted via the optical fiber channel 2 62 preferably includes a txd_fc (16 bits wide), kgen (2 bits wide), and a transmission idle (flag). In general, txd_fc (data) and kgen (control) are mixed to generate the appropriate transmission symbol by the encoder 208. The signals output through GMI I are preferably tx_en (enable), tx_er (error), and ud (data). This information is then appropriately transmitted to the physical medium 140 as shown in FIG. 2. Further, the shared control data path 2 61 can receive an idle valid flag "signal from the area control logic 2 54. In one embodiment, J --------- A ----- -IT ------ 0 {T * :. tisf read t and then; ί.Μ.ώ Matters again M-1-: * 本 κ) SS home samples in the paper size tracking (CNS) / \ 4 specifications (210X 297 male f) -50- 457444 A7 ΒΊ 5. Invention Description Lang), when receiving a "idle valid flag", the appropriate symbol can be shot in the appropriate time (that is, in the packet between). This is especially useful when users want to send unique information without increasing the need for network attachment. For example, these special symbols may be transmitted when the network is uniquely known (i.e., an IPG cycle). This symbol can then indicate that there is a selected stylized idle symbol as defined by the 802.3 standard. In an embodiment, the symbol defined by the customized user may find a special use when a transmitting station needs to determine the response of a receiving station. That is, when a transmitting station propagates a modified user-defined symbol to the receiving station, the receiving station may or may not be able to process the modified user-defined symbol, thus providing the ability of a transmitting station with data at the receiving station. Figure 4F shows the support logic and state machines included in ETHER 212 according to one embodiment of the invention. As shown, a state machine support logic 264 is coupled to an air control state machine (FCSM) 265, and a carrier control state machine (CCSM) 266. State machine support logic 264 is generally used to support the combined state machine functions and to generate appropriate intermediate signals. In general, the processing performed by the disclosed state machine is modified on a packet-by-packet basis through parallel data and control processing paths. Therefore, when the individual registers contained in the transfer control register block 252 are modified, the processing variables of this bit in ETHER 212 will be executed sequentially and synchronously on the data being processed. . It should be understood that -51-SS family standard 4M CNS in the application of this paper standard) Λ4 圯 grid (210X297 mm) AR7 Α Δ Δ ι »" • " •-屮 " ^^ And, only the consumption竹 竹 社 印 " Α7 V. Description of the invention _) In the system of know-how, modification is allowed only between the entire packet transmission (not the middle packet). Generally speaking, FCSM 265 is responsible for processing data according to the flags set in the instruction protocol register 3 2 0. For example, if no antecedent is required, no antecedent is generated and added. The processing of the F CSM 2 65 is described in detail below with reference to FIG. 8B. Similarly, CCSM 266 is generally responsible for (a) determining whether to send packets without collision: (b) determining whether jamming is required; (c) determining whether the packet bursts and requires carrier expansion, etc. . The processing of the CCSM 266 is described in detail below with reference to FIG. 8A below. Still referring to FIG. 4F, a signal called “hst2xmt_abort” is directly displayed in ETHER 2.12. In one embodiment, 115 [2 \ 111 〖_31) 〇1 t is preferably marked as an immediate cut-off (even when an event box is being processed). The bounce function then allows the user to stop the transmission at any time during the packet transmission and "flush out" to keep a buffer of any untransmitted data. Advantages, this allows users to quickly and correctly remove any errors from the network and avoid sending unwanted data over the network. Fig. 4G is a block diagram showing a more detailed situation of the functional blocks contained in the transmission public block 220 (Fig. 4) according to an embodiment of the present invention. As shown, a support logic block 2 0 0 is preferably used as a support function performed in the transmission control block 2 10, which is responsible for setting the time slot and a minimum carrier packet size as About 5 1 2 bytes. In the middle block, the latency counter is responsible for transmitting I --.------ A ------, 玎 -------- 0 (^^^. Please ^ : And note ^ matters again ^^: too pages) This paper size is in use 1 ^: standard ( < ^ ’5) Eight 4 specifications (2 丨 0; < 297 mm) -52- A7 457444 B7 V. Description of the invention) The time before birth elapses, and the octal counter is used to confirm the number of bytes transmitted by each packet. In one embodiment, the latency is used as a time period from when a transmission is requested (for example, when a packet is valid to be received and a proper handshake is confirmed) to when an attempt is made to transmit. Therefore, if a collision occurs, a new latency period will be calculated. In addition, once this information is calculated, the information will be communicated via a bus 2 8 1 which transmits a control signal " xmt2hst_stat " and "xmt2hst_rsp". As described above, a proper handshake as an initial data transmission is generally a data preparation signal received from an upper LLC layer and a MA C signal indicating that the MA C layer is ready to receive data from the LLC layer. Layer (to the LLC layer) is ready for signal. Finally, a Cascadabie public computer 2 8 4 is used to calculate overflow and non-overflow variables. These variables use circuits added in accordance with the ideal "minimum C P U interrupt" waterfall method. For example · Once the minimum number of CPu interruptions is confirmed, the public computer circuit can be waterfall-type, that is, repeated and integrated to increase power to meet the requirements of ideal processing. Then, the number of hardware circuits can be adjusted according to the user's demand for performance. FIG. 5A is an illustration of four packets being transmitted via a traffic-based MA C 150 according to an embodiment of the present invention. To demonstrate the programmability within the parallel packets of the present invention, packets A 502, B B 504, C C 506, and D 508 are shown as being transmitted via the traffic-based MAC 1 50 in FIG. Because there is a separate data processing path and a separate control processing path, the pair-^-Ί -------- α · --------• --t-^ 'UCH consumer cooperation .71 Indian ^ ---- line. ------ This paper scale follows "China ^ Jiabiao Bei ([\ 5) 刎 Specifications (210/297 mm) -53- 457444 A7 B7 "-" `` Central ^^ Bureau Ordnance Industry ", &", company seal ^ V. Inventor 1) Data processing performed on event packets being transmitted via traffic-based MA C 1 50 Can be modified while the packet is being transmitted. To show this, for example, the transmission of packet A 502 is to have a look-ahead column, a destination address block, a source address column, and a length / type column (L / T). LLC information column, and a CRC column. Now suppose a user has to de-enable the CRC column of the next packet B 5 0 4 to be transmitted. In order to deactivate the C R C for the next transmission packet, the user does not have to wait for the next IPG as required by the conventional art embodiment. According to an embodiment of the present invention, the user can send a control signal of the packet B 5 04 to disable the CRC at any time after the CRC calculation for the packet A 50 2. As shown in the figure, the CRC may be de-enabled at any time between time t! (I.e., after the last packet CRC) and time t2 (i.e., before the next packet CRC). As mentioned above, having the ability to change the processing agreement for each packet instantaneously makes it possible to modify the processing of the packet and then the packet. This processing is not possible for systems of conventional skill. Therefore, the CRC may be de-enabled at any time when packet B 504 is transmitted upwards until the end of the L LC data or before any appropriate padding, which is not shown for simplicity. In another example, suppose that the user wants to disable the preemption of an upcoming packet. In one embodiment, if antecedent deactivation is desired, then control over deactivation must be transmitted before the appropriate antecedent is processed. For example, once packet C 5 0 6 begins to be transmitted, the antecedent cannot be de-enabled, but the antecedent can be between time t 4 (T ---------- A ------ . 玎 ------ 0 i ':,. · "^. &Quot; ^ 〆" And-read ^^^^^ Page) SS Family Standards (CNS) A4 specifications (210X297) 犮 -54- 457444 .¾ ^ .. ¾. Middle-level sample concentration bureau β ΗConsumer Hezhusha Yinfeng A7 B7 V. Description of the invention since 2) That is, 'in the generation of packet c 506 After) and time t5 (that is, 'before the generation of packet D 5 0 8 first) and the next packet is de-enabled. As shown * Once enabled between t 4 and t 5, the next packet D 5 0 8 does not include a look-ahead. The important advantage is that the packet D 5 0 8 does not include a CRC column because it is not enabled as described above and t2. Of course, If at any time a 'CRC or antecedent is needed again, an appropriate control signal may be transmitted on a packet-by-packet basis to trigger the combined generation and addition. In a further embodiment, it is assumed that a use Think Revision of a program displayed in one of 504 packets A 502 and B exist in the packet I P G "time X. "Into a longer period of time. In order to modify the IPG, the user can simply send an appropriate control signal to modify the IPG in any confirmed packet. In this example, the user can add a packet C The initial IPG between 506 and packet D 508. To complete the modification, the user must transmit between time t6 (ie, after packet B 504) and time t7 (ie, at the end of the LLC data or any packet C 5 0 6 before proper padding). Of course, if packet C 5 0 6 is included in a CRC field, t 7 is before the end of the appropriate CRC field. As shown, the IPG is programmable The characteristics have been implemented, and the short time range of the IPG is now "time X 0 + X 1". Once stylized t, the new IPG will be maintained until it is modified again according to this embodiment. The advantage is that it has modifications The ability of IPG enables a network management program. This paper uses the SS family standard (CNS) Λ4 Grid (2) (Vx 297 cm). 55-~ T, i order 11 lines (;? ·. --¾ • Read * ηΛ 之 .1 蹋 片 坨 '!-: 1 本 5 > Γί " 4Γφ. " "-: ΐ ·: ν · Bei Beigong disappeared in the cooperative seal-4 ^ 7444 A7 B7 V. Invention description) To modify the rate at which packets are transmitted through the media. For example, if IPG increases , Fewer packets are transmitted at another cycle time. On the other hand, if the IPG is reduced, more packets will be transmitted at the same time period. Figure 5 B is implemented according to one of the inventions For example, the state machine diagram executed in the transmission public block 220 (Figure 4). In this embodiment, the state machine always calculates the aforementioned public variables under the state 5 50. Then, it is processed in the transmission control block. When it is executed, the status counter of this bit in the transmission public block 210 area will always be updated. In this way, the counter included in calculating the public status 5 50 can be read at any time. If at any time At time, the initial sampling line flag 3 3 2 (Figure 4C) is set to be true under condition 5 5 2 and the state will jump to an initial state 5 5 4 where the register is erased And the calculation public status 5 5 0 is recalculated again The processing status in the scratch. If the "Start Sampling Line" flag of this status is not true, the calculation public status will be set according to the control register block 2 5 2 in Figure 4 A Continue to calculate the public settings. The advantage is that the state 5 5 2 is similar to a trigger effect, the effect is to eliminate these registers and start to recalculate public variables. FIG. 6 is a flowchart showing the processing steps combined with processing data via a data path according to an embodiment of the present invention. The method starts in step 601, which determines whether there are any packets to transmit. If no packet is to be transmitted, the method will wait until there is a packet to be transmitted. If there is a packet to be transmitted, the method will proceed to step 6 〇2, the paper wave inversion 遝 / f; Zhonggg Jiayoujing () Λ4 Regulations (public exemption) · 56 · ^ ---; --- ---------- IX ------ line i-vw. ^ Jin Erzhi ^-bamboo shoots and then repetitive ingenuity) 457444 ο. Ministry of Central Rongdaiben and ϋ-χ ^ Cooperative cooperative seal-V. Description of the invention P4) 6 0 2 has a transmission control signal (xc S) bus set packet effective bit to transmit to the LLC data path marked 32 bits wide with data to be transmitted Data transfer block 2 50. Once the packet is valid, the bit is set in the transmission control xc S bus in step 602 · ’The method will proceed to step 6 ◦ 4. In step 604, the host will be set to transmit a "data ready" flag and provide data on the data bus for the current packet. In this embodiment, 'the host can be regarded as an upper layer LC layer which communicates with the media controller (MAC) layer'-once the host is set to transmit a "data ready" flag and the current packet When providing data on the data bus, the method proceeds to decision step 6 06, which is to determine whether a “ready data” flag has been transmitted to the host from the traffic-based MAC150C (Figure 2) (LLC). If the flag is not transmitted, this indicates that the traffic-based MA C 1 50 is not ready to receive data from the L·LC layer. At this point, the method will wait until the traffic-based MA C 1 50 is ready to receive data by setting the appropriate "ready data" flag sent from the host (LLC). Once the data is ready the flag The target is set in step 606, and the method will proceed to step 608, in which a 32-bit bit under the current packet data is supplied from LLC to the data transmission block of Fig. 4. As shown in Fig. 4A As stated, the data transmission block 250 receives data from the LLC via a 32-bit wide path. However, it should be understood that any suitable path data width can be used without departing from the spirit and scope of the present invention. The method now proceeds to decision step 6 1 0, which 6 1 0 is determined by ___ t · ^ I Order t * It i —Tile paper size standard in China 囡 橾 家 橾 此 *. (CNS) Λ4 specifications (21 (>; <; 297 public 嫠) -57- 457444 Ά -'- Central. ^^ 局 贝 -7- 消 先 合 竹 、 社 印, ΐ! Α7 B? V. Description of invention since 5) Is there more available in Information under the current packet. For example, 'If there are more 32-bit wide characters for the current packet to be transmitted, the method will be reversed to decision step 6 06, which is 6 6 determines whether a data is ready A flag has been transmitted to the host. LLC has been sourced from a 32-bit file under. LLC. If it is determined that the prepared data flag has been transmitted to the host in step 6 06, the method will proceed to steps 6 8 and 6 1 0 again, and step 6 6 will be brought back until all the current packets are The data has been transmitted ^ Once it is determined in step 6 10 that there is no data in the line packet, the method will proceed to step 6 10, where the packet has valid bits and the host transmitting the "data ready" flag is Deactivate the function to indicate that there is no data to be transmitted in the current packet. Of course, once the method returns to step 601, it again decides if there are more packets to be transmitted. Then, if there are more packets to be transmitted at this time, the method will go through step 6 12 again from step 602 until all the data bytes are transmitted for the next bit packet. Fig. 7 shows a flowchart showing method steps incorporated in a control path according to an embodiment of the present invention. Control path processing begins in step 602, where it determines whether a modification request for the contents of an individual control register is requested. If it decides that it does not have a modification request for an individual control register, the control path processing will not start (ie, data processing will be performed without any modification) and the processing will be transferred to decision step 702 again, It again decides whether there is a request for modification of the content of the individual control register. JL .------------ IX ------ line f-:, v wn-^-^-^^^-1 ^. /-. ¾) Kg Family Standard (CNS) Λ4 is now 297 mm in the applicable degree) -58- 444 A7B, __V. Description of the invention Bang) For example, Figure 4B shows a set of six control registers' The temporary The register has been selected to modify a packet-specific modification when it transmits the data path down as described in FIG. 6. Then, if the user wants to reset one of the plurality of registers in the control register block 2 5 2 'then_ a control signal is shown in FIG. 4A via the control bus 2 5 3 And it is transmitted to the control register block 2 5 2. Once a different register is selected, the contents of this register can be modified by writing to a different register of the DEFER cycle register 3 0 4, time slot register 3 0 6, retry limit register 3 0 8, or stylized min / max packet size register. On the other hand, if the instruction agreement register 3 2 is selected, various flags in the instruction agreement register 3 2 can be selected. As shown in Figure 4C, there are various flags that are triggered according to the type of control information fed to the control register block 2 5 2 shown in Figure 4A. For example, the user may process in full-duplex mode by selecting the fdplx 322 flag, or, for example, the user may de-enable CR C by selecting the non-CRC 326 flag. Of course, any suitable register flag or register is selected according to the type of processing agreement desired by the user. It is important to understand that the control path processing system shown in FIG. 7 and FIG. 6 Data processing performed Separate processing performed in parallel. As a result, the data processed through the data path processed by the graph stream can be modified in parallel at any point when the data processing path has nothing to do with when the control is transmitted because the control can be transmitted in parallel as shown in FIG. Step 7 0 2 When it is determined that there is a demand for an individual control register content modification request, the method will-owe, order < ^. ^ * 之; i.-i5.? _! r; -3rw-v-;. This F ') This paper standard is included in the KS family standard (C: NS) Λ4 specification (2lOx297) ) -59- 457444 Α7 Β7 V. Invention description π) Proceed to step 7 0 4 where the individual control register to be modified is confirmed and the corresponding flag set on the xc S bus is set. Is true. Once the corresponding flag is set to true, the corresponding control information is also set on the control bus. For example, if no antecedent flag is set in the instruction protocol register 3 02 of FIG. 4C, the packet being transmitted in parallel in the description of FIG. 6 will not have the corresponding antecedent added at the beginning of the packet. The method now proceeds to step 706. One of the gate control is set by the LLC that drives the XCS bus = once the capture control is set in 706, the method will proceed to step 708. The identified control register is loaded for the individual packets being processed. Once the identified control register is loaded in step 708, the method proceeds to step 710, where the gate control is removed. Once the gated control is removed in step 7 10, the method will return to step 7 2 0, where it will again decide whether to modify the contents of the individual control registers. If necessary, the method is executed again from 704 to 7 1 0. Fig. 8A is a carrier control state machine (CCSM) 266 '. The 2 6 6 system is included in the E T Η E R block 2 1 2 according to an embodiment of the present invention. In this embodiment, when there is no transmission being performed by the SUPERMAC Tx controller 118 of FIG. 3, the state starts in an idle state 8 0 2 β when it decides to receive a packet in the state 8 0 4 A valid signal, a delayed ready signal, and a back-ready signal, the state will move to the frame state 806, where the paper ruler and the Chuanchuan Zhongbei (OS'S), \ 4 specifications (210 × 297 male f) -60- 4574 4 Α7 Β7 V. Description of invention bell) The packet data transmission system is processed. In frame state 8 06, the CC SM system continues to determine whether there is a collision when transmitting packets in state 8 0. For example, 1 if a collision is detected in state 8 0 (eg, its Indicates that another station is trying to transmit while a packet is being transmitted), then the state machine will jump to a congestion state 8 1 2 where a congestion signal is sent out through the network and any current transmission will stop. The congestion signal also ensures that all other stations on the network also detect a collision and stop its transmission in the same way. Once the other station receives the congestion signal and stops transmitting | all transmissions will temporarily wait for a preset back-off period of any number of "time slots", which is calculated by using the aforementioned cut-off binary index back-step algorithm to calculate 9 and Congestion state 8 1 2 is continued in state 8 2 4 to determine whether congestion has been completed. If congestion is not completed, the congestion state will continue to be congested until the congestion state is completed. Once it decides that the congestion is to be completed in state 8 2 4, the state will return to an idle state 8 0 2 0. Now refer to state 8 0 8 again. If it determines that it has no collision in state 8 0 8, the state Will proceed to another state 8 2 0, where the 8 2 0 decides whether the packet should stop. If the packet is not stopped, the state will return to the frame state 806. On the other hand, if the packet ends in state 8 2 0, the state will return to another state 8 2 2. The 8 2 2 determines whether a large number of packets emerge or the carrier expansion is needed. As mentioned, if the carrier expansion is needed, the transmitted packet should preferably be {• '••-" " 化 "and ^-念 事 ^-堉 巧 堉 石) Paper scale In remote use, ΚΚ 家 津 (CNS) Λ4 intersect (210X297 mm > -61-4574 4 · ^ A7 B7 V. Description of the invention) At least 5 1 2 bytes long-Generally speaking, a packet is one The part of the carrier event and when each packet is transmitted, the period of a 512-byte carrier event must elapse before a new packet is transmitted. Therefore, if a packet contains less than 5 1 2 bytes of data, then Other bytes up to 5 1 2 bytes will generally contain a carrier expansion symbol. If it decides in state 8 2 2 that a large number of packets need to emerge or carrier expansion, this state will proceed to carrier expansion state 8 18, of which 8 1 8 will perform the appropriate carrier expansion processing as described above. In the carrier expansion state, it is decided in state 8 1 6 to complete the carrier expansion. If the carrier expansion is not completed, the carrier The expansion state will be maintained. Once the carrier expansion has been completed, it will decide in state 8 1 4 A large number of packets need to emerge (ie, more packets to follow). If a large number of packets need to emerge in state 8 1 ', then the state should proceed to step 8 1 0. In state 8 1 0' it determines whether a delay is ready. Complies with the new packet. If the delay is not yet ready, 'In state will be maintained in carrier extension state 8 1 8' The 818 will continue until it determines in state 816 that a carrier extension has been completed. On the other hand If the delay has been prepared in the state 8 1 0, then the state machine will determine whether a packet is valid and the state 8 11. If the state 8 1 1 is consistent, the state will return to the aforementioned state box 8 0 6. On the other hand, if the packet valid state 8 1 1 does not meet the state, the machine will return to the idle state 8 02. It should be understood that when in full duplex mode, there is no carrier sensing and no collision detection. Executed in state 8 0. Once the consensus energy flag is set in step 8 05, "the thief family in the system (rNS public)--^--r-, ----- 1 In ------ ^ ------ @ (-" " ^ '' '"and ^ & 事 ^ 再-^' :: ^^ 打) ί: Λ ii, τ. F: / v Ik f > A7 B7 V. Explanation of the invention) Timing, one of the box control state machines (FC SM) in Figure 8B will be initialized. Although the CC SM and FC SM state machines are described as separate state machines, but it should be understood that each of these two state machines can be operated as a large state machine. In addition, it is important that many of the CC SM and FC The operations performed in the SM are preferably performed in parallel. Fig. 8 B is started in a state of 850, where the box controls the state machine according to an embodiment of the present invention in an idle state of 850. From the state 850, the state machine moves to a state 851, where the next decision is made to determine that "enable" is true in the CCSM state machine in Fig. 8A. Once it decides that the enabling is true in state 8 51, the state machine will move to state 8 5 5 where it decides whether a look-ahead is needed. For example, as shown in Fig. 4C, the unprecedented 3 2 8 flag can be appropriately set for each packet being processed in the traffic-based MAC 150. If an antecedent is needed | an appropriate antecedent is generated and added to the packet being processed. As shown above, the look-ahead usually contains synchronization information and the first frame border that marks the beginning of the frame. In the advanced state 8 5 2, it is determined in the state 8 5 6 whether the addition of the advanced state is completed in the advanced state. If it is complete, the antecedent state 8 5 4 will continue. Once the appropriate antecedent has been added in state 8 5 2 ', the state will move to a data state 8 5 3 whose data is transmitted via the appropriate data path. In the data state 8 5 2, it continues to determine whether there is a collision in the state 8 5 8. As mentioned earlier, if another station attempts to transmit while the current station is transmitting, a collision will occur. If it decides that a collision will occur, the state will return-; ΐ1 ^ .., 5'ρ ·· 之 '; i-$'; fi 再 ^) " -63- ^ 7444 i. Description of the invention since 1) Return to the idle state 8 51 and remain idle to wait for a new "enable" from one of the CCS Ms in Figure 8A. On the other hand, if it decides that it has no collision in state 8 58, then it decides in state 8 6 0 whether the packet should end transmission. Of course, if the packet needs padding, automatic padding will be performed in the data state 852 and therefore the padding is part of the transmitted packet. In this embodiment * the packet being transmitted in the data state 8 5 3 does not contain a CRC. If it is in the state 8 60 that the packet has not yet completed its transmission, the state will return to the data state 8 5 3, and the 8 5 3 data will continue to be transmitted until completion. "When it decides the packet to complete the transmission and State 8 6 'then it further determines whether the CRC is needed in state 8 62. .. 屮 '于 合 竹 .ΐ 印 " For example, as shown in Figure 4C, if the non-CRC 326 flag is set to true, the non-CRC should be appended to the end of the appropriate packet being transmitted. If the C RC flag is not set to true in state 8 62, the state will return to idle to indicate that the entire packet has been transmitted without a CRC. On the other hand, if the CRC flag is not set to true, then the CRC should be added to the packet being transmitted and the state will proceed to-add the CRC state 8 6 4 where the 8 6 4 is being transmitted. The current packet is information with an appropriate CRC. Next, the Frame Control State Machine (FCSM) 265 has now properly transmitted any non-preemptive, non-CRC and detects any collisions * Of course 1 if the full duplex 3 2 2 of this FIG. 4 C is set to true, Then the state 8 5 8 will not be determined and there will be no collision detection attempts. · This machine is far-fetched according to the standard: ii? (CNS) Λ4 格格 (2ΙΟΧ 297 公 楚) -64-ixe rush ". Huan Mian Huan ^ " M ^ -elimination of the combined bamboo company seal 4- 4-M > 1 A7 B7 ____ V. Description of the invention from 2) One side of the receiver The flow-based MAC of Figure 2 MAC 1 5 0 The receiving side will now be described according to an embodiment of the invention. As shown, the receiving side of FIG. 2 generally receives a signal from the physical medium 1 41, which is input to the SUPERMAC Rx controller 120. Next, the following description will show the operation blocks contained in the SUPERMAC Rx controller 120. Figure 9 shows a functional block diagram of a receiver overdrive "controller 120" that can be included in the root case. As shown, it has a main data path, which is from a fiber channel or a ten Gigabit Media Independent Interface (GMI I) 906 into a receiver. Although any physical medium can be connected to the receiver FC / GMI I 906 'a fiber channel decoder 9 0 8-generally receives a ten bit The signal 'The signal is decoded according to the well-known optical fiber channel standard. Once decoded', a 16-bit wide data path is actually output to a receiver FC / GMII 906. Also shown is a feed to the receiver One of the GMII 8-bit wide inputs in FC / GMI I 906. As mentioned, a suitable GMI I interface generally has standard electronic and mechanical signals for reading and receiving from various types of physical layer devices. Once the receiver When FC / GMI I 9 0 6 receives and converts the appropriate signal to an appropriate 16-bit wide data path, the data is transferred to a receiver CRC check 904, one of the CRC checks Execute on the received packet to determine yes No An error occurred during transmission β The paper size is in common use 1; Wei Jia Biao Jing ([7 ^) / \ 4 size (210/297 mm) -65- ^ »57444 A7 B7 V. Description of invention $ 3) Explained with reference to the transmitting side, when a packet is transmitted, c RC is generated and added to the end of the packet with a CRC field of four bytes. Then, on the receiving side, the receiver CRC check 9 0 4 Performs the same CRC calculation to determine whether an error occurred during transmission. In general, if the CRC check output in block 9 04 is different from the block added on the transmission side, the error is generally caused by It is considered to have occurred at the time of transmission. At the same time that the CRC is checked, the data is transmitted to the receiver LLC interface 902, and the proper processing of the 902 is performed on the received packet. The plug removal, start of sampling line, self-receiving, and receiving enabling operations may be performed on the received packet according to the appropriate flags in the receiver controller register which will be described in detail with reference to FIGS. 9A and 9B. &Quot; " .Ministerial Standards Bureau Industrial and consumer cooperative printing? Once the receiver LLC interface 9 0 2 performs appropriate processing in the received packet, a 32-bit data is output to the upper layer of the LLC. Generally speaking, the receiver LLC interface 9 0 2 is based on the state of the receiver control block 910 and appropriate processing is performed on the received packet. In this embodiment, the receiver control block 9 1 0 is preferably a device with a controllable bit in the SUPERMAC Rx control. Appropriate processing operations performed in the processor 120. A public block 9 2 0 of a receiver is shown. The 9 2 0 is preferably modified to maintain statistics of the receiver. In one embodiment, the conventional receiver statistics are shown in Table 4 below. -66- (Xu first read the back of the precautions before (1; this page) This paper size is applicable to Zhongyuan Garden Standard (CNS) A4 specification (210X297 mm) 457444 A7 B7 V. Description of the invention P) -¾. The Ministry of China and the Ministry of Justice finalize the decision. • Negative-T cancellation cooperation seal. Table 4 rcv2hst stat rc vEnabled Receiver is working (enable). RcvError Received error errorCRC has CRC error erroLong The packet is too long (greater than 1 5 1 8 bytes): Of course, the standard packet size is stylized according to the embodiment of the present invention. The errorShort packet is shorter than 64 bytes. However, its programmable errorFrame detects a frame error (RXER). errorOverFlow Buffer overcurrent errorCRE Carrier event is too long error Protocol A new packet comes in before the first packet completes 512 bytes (only ten bits) macControl This packet is a MA C control packet pkt8023 This packet is a 802.3 packet recei velPG received IPG 値 octsCnt octal counter 値 ctrOflo w logarithmic (for IPG or bit counter) overcurrent Itilization factor public factor 値 read first f's attention matters again. r-: J page jv ° f «I. * I-. This paper size is described in the KS family standard (CNS) Λ4 specification (210X 297 male i) -67- 457444 A7 B7 5. Invention Description 05) An embodiment is shown in the receiver block diagram of FIG. 9. As shown, a data transfer area C / GMII receives a 16 register control register 9 5 2 temporarily '' device control logic 9 5 4 the appropriate gate AC Rx controller 120 will execute the current row 9 5 3 Transmit an appropriate control (Self-transmitting control signal bus (The selected processing control will self-receive the control block temporarily. In this embodiment, the receiving control block 9 2 0, the receiver block 920 (Figure 9) , And then A). ^ &Quot; _Bid in the ministry 汍 Bureau member τ; stamp of cooperation rights ^ Figure 9 A is a detailed block 9 0 2 of the LLC interface 9 0 2 according to the present invention 9 5 0 White receiver F Bit-width data 0 According to the status of the register and a receiving time control, the SUPER M line should be processed as desired 0 For example > once the control sink C T L) instruction and a gate control XCS ) Transmitted * then a selected register 9 5 2 is transmitted to the selected one. The appropriate control information is transmitted to FC / GM IIJ receiving public receiver control logic 9 5 4 (Figure 9 followed by j Receiver control logic (eg, > state machine) 9 1 0 to 9 0 6 〇— In the embodiment C 9 0 2 is stripped or can be used by the processor 1 1 4 a > When transmitting, it is added to the data column. When provided, 1 can also be transmitted to micro R. In this way, pad information can be transmitted in 1 1 4 a as a special invention. The advantage lies in the transmission of padding data (Xu You reads the back (Notes on this page) Series 9 5 4 The receiver control block and receiver FC / GMI IRC can be sent to the micro_RISC processor in Figure 2 to perform stripping. In addition, If the pad, the pad is plugged in a tuple that is not enabled by the I SC stream processor 1 14a. Send to the micro-RI SC stream processor for processing. The message to LLC will be allowed in the congestion column- 68- This paper uses the Chinese National Standards of Humble (CNS) Λ4 specification (2) 0 × 297 mm) 'Qiu Shiyang 桠 ^-^ tH and η-Ηίρ- ^. 7 d 4 4 A7 ______B7 5. Description of the invention @ 6) Contains appropriate information. In a further embodiment, transmitting the pad will provide additional bandwidth to include management information, which can be used to identify individual boxes that are important in the box flow. In another embodiment, if the pad is transmitted, the radio may also include time stamp information, which can be used to determine the network latency. As mentioned above, this latency can be confirmed as the time between when the packet information to be transmitted on the network is retrieved and returned to the transmitting station. Of course, 'padding' is only valid for data packets with less than 64 bytes. On the other hand, if the minimum packet size is increased to 64 or more bytes by programming, more packets will need to be plugged. FIG. 9B shows a flag included in a receiver control register 9 5 2 according to an embodiment of the present invention. The first flag is a receiving enable 990 flag, and the flag indicates that The SUPERMAC Rx controller is ready to receive data. In this embodiment, the enable 990 flag can be used by the receiver control logic 954 and the data transfer block 950 to initiate the receiving protocol. The next flag is a removing plug 9 9 2 flag ', and the flag is used to set a plug removing operation. In general, any required plug removal is performed in the receiver control block 910 state machine, which will be described in detail below. The next flag is the initial sampling line 9 9 4 flag, which is used as a trigger for sampling on the receiving side. For example, when the start sampling line 9 9 4 is triggered, the public counter is completely refreshed (refresh), and the received public register is recorded from the scratch area again. The last flag is a self-receiving 9 9 6 flag. The flag is received as enabling data, which is transmitted by the transmitter when a diagnostic operation is performed. Of course, the standard is applicable to the sample list of the Chinese family. (CNS) Λ4 ^ grid (210X 297 mm) -69- ~ ~ ίί read the back of the matter and fill in this page) 4 5 ^ 144 * ; -Ministry-B-Central Bureau of Standards T; Removal of cooperation rights A7 B7 V. Description of the invention 狖), if the operation is in half duplex and the media is M II, the signal will be automatically transmitted normally return. Although only the designated flags are confirmed, it should be understood that any number of appropriate flags or additional registers, etc. may be included according to user needs. FIG. 9C shows a more detailed block diagram of a structure included in the receiver FC / GMI I 906 of FIG. 9 according to an embodiment of the present invention == In this embodiment, a first input can be supplied at Decoder 9 0 8 and input a 16-bit wide signal to the fiber channel (FC _ 1), and the second (GM II) 8-bit wide signal can be input to a gigabit media independent interface processing area Block 9 6 3. It should be understood that 9 6 2 and 9 6 3 are independent processing blocks. For example, other interfaces that are downwardly compatible with the 100 / 10Mbps MI I interface unit can also be implemented. Shown is a shared control data path. The path is received from both fiber channel 962 and GMII 963, and the control and data information are combined to form a 16-bit wide multi-mode signal. Once the data and control information are multiplexed in block 961, the circulation will proceed to the receiver C R C check 9 0 4 and the receiver L L C interface 9 0 2 described above. Of course, if only a single signal is received from the physical layer, the receiver F C / GM I I also has the ability to receive a signal at a single time without performing a multiplexing operation. Fig. 9D is a block diagram showing the detailed situation of the functional block included in the receiving public block 920 (Fig. 9) according to an embodiment of the present invention. As shown, a support logic block 980 is used to support the application of the Chinese Enclosure Standard (CNS) Λ4 specification (2) OX297 mm at the paper size -70- J --- <-· II ----% ------ Order · ------ line. I / (诮 1 read the back and pay attention to the item again ^ .¾ this I) 457444 A7 B7 V. Description of the invention bet) The functions executed in the control block 2 10 are received. In the middle block 9 8 2 ′, an internal packet gap (IPG) and octal counter are used to record the IPG of the received packet and confirm the number of bytes received in each packet. As an example of the variable table ‘maintained in the receiving public block 9 2 0, a table 5 confirming the appropriate statistics received by the response bus“ rcv2hst_rsp ”is shown below. In a further embodiment, the part responding to the bus " rcv2hst_rsp " can also be driven by other modules. ^ T '" Order ------ line-- (-7 fW read the back " meaning Matters (Sakizaki, r ': J this page) #:-' 部 屮-乂 标 龙 局 资 工 消 贽 社 贽 印 印 -71-This paper size is applicable to China Weijia Standard Port (CNS) Λ4 specification (210X 297) (Centi) 457444 A7 B7 V. Description of the invention ㈣) Table 5 ^-•• 部 屮 ^-^^ 员 ^ 消 合 合 ^^ 印 ^ rc v2hst_rsp rc vClk The packets received by rc vDone that are useful for registering this status information and The packet status bit is valid. The pkt Valid receiver actively receives the packet (excluding the leading one). Idle Valid The required direction data from the decoder output or the byteEnable corresponding to GMII is valid. The corresponding bit is valid fc on the rcv2hst_data bus. Kg en When the KFLAG is received from FC-1 port or RX_DV, when RX_ER receives padValid in GMII port PAD data is now on the data bus ipgValid IPG information is valid on the status bus octsValid bit count is on the status bus Active (00) utilVal id (〇1) (10) Counting work flow through the current paper size This paper uses the Chinese National Standard (CNS) Λ4 specification (2 丨 0X297 mm) (Xu Xianyou ^-介 '& Note and then 4 smart books Page) 72-457444 Α7 Β7 V. Description of the invention ㈧) Still referring to FIG. 9D, a waterfall public computer 9 8 4 series is used for calculation according to an ideal " minimum number of CP interrupts " The receiver public of the added circuit. As described above, once the ideal minimum number of CPU interrupts is confirmed, the public computer circuit can be waterfall-style (that is, the increased processing power is copied and integrated) to meet the ideal. Processing requirements. Next, the number of hardware circuits can be adjusted according to a user's performance requirements. Figure 10 is a flowchart of data flow on the receiving side of the LLC according to an embodiment of the present invention. The advantage is that the data and control information are processed in a parallel manner as described above. The data path method starts at step 102, which determines whether a packet valid signal is true. If Packet valid signal is not true, then the method waits until a valid signal has been transmitted packet appropriately to the receiver based on the designated sealing the package is ready. When the packet valid signal is true, the method will proceed to step 104, in which the host is set to indicate whether the host is ready for data. In this embodiment, the host is the upper L L C layer, which is receiving data from the traffic-based MA C 1 50 in FIG. 2. When the host indicates that it has prepared the information in step 104, the method will proceed to decision step 106, which determines whether the receiver has the information of the host. For example, in this step, it is decided whether the traffic-based MA C 1 50 has the data of the L L C layer to be transmitted. If it decides that the receiver does not have the data to be transmitted to the LLC layer, the method will proceed to decision step 1 0 1 0, which is determined to be -73- (commenting with the first consideration and the other considerations before ^ .. '1,5 pages) KS Family Standards (CNS) used in this paper music standard Λ4 is present (210 × 297 male f) 45744 Ministry of Chinese Ministry of Justice 桴 Bureau 桴 -Τ 消 fr Cooperatives Indo A7 B7 V. Description of the invention (71) Whether it has a package is valid. If a valid signal of a packet appears, the method will return to decision step 106, which decides again whether the receiver has the data of the host. When the receiver does not have the data of the host, the method will proceed to step 1008 in which the data contained in the receiver (eg, the next 32 bits) is transmitted to the LLC layer. On the other hand, if it decides that the packet valid signal does not exist in step 10 10, the method will return to step 10 12 in which the host (LLC) is released from marking the information that it has prepared.横 效应。 Vertical effect. From this point of view, the method will return to the decision step 10 02, which decides again whether the valid signal of the packet is to be established. Here, the method may continue to flow the data transmitted in step 10 2 through step 10 10 until all requested data is transmitted. FIG. 11 is a flow chart showing the steps of a method for controlling transmission in parallel with a data path according to an embodiment of the present invention. In this embodiment, the method steps are described in combination with the modification of the processing control variables of the receiving part of the traffic-based MA C 1 50 located in FIG. 2. The method steps start at step 1 102. This step determines whether a modification request to the counter of the individual received content register is required. For example, the reception control register may be a register included in the receiver control register block 952 as described above. Therefore, the appropriate flag may be a register contained in the receiver control register block 9 5.2. That is, if the user wants to enable the removal of the pad flag 9 9 2, the appropriate control signal can be transmitted to the receiver by the control bus 9 5 3 of FIG. 9 A ^ --- V --- --- " ------ Order ------ Spray! 4 (Please read the reverse first. The above matters are not included on this page.) This paper refers to KEKI in the state of the paper: standard (CNS) Λ4 specification (2I0X297) 嫠 -74- 457444 A7 B7 V. Description of the invention) Control The register 9 5 2 and a transmission control signal (XC S) will indicate a gate time of the selection.

* 1T Once a modification is requested in step 1 102, the method will proceed to step 1 104, in which the appropriate reception control register is confirmed and the corresponding flag is set on the xcs bus And set to true. In addition, once the flag is set on the X c s bus, the corresponding control signal is located in the C T L 9 5 3 control bus. The method proceeds to step 1 106, where the gate control is set to the event flag. Once the gate control is set to the appropriate flag in step 1 0 6, the method proceeds to step 1 1 8. The receiving control register that is confirmed in this step is via the receiving LLC interface 9 0 2 of FIG. 9. Instead, load the appropriate treatment. Once the appropriate control register is loaded in step 11 08, the method proceeds to step 1 110, where the gate control system is removed. The important thing is that the receiving control path 1 1 0 0 can be processed in parallel with the data being transmitted through the receiving data flow path 1 0 0 0 of FIG. 10. FIG. 12 is a state machine diagram for one of the receiver control blocks 9 10 of FIG. 9 according to an embodiment of the present invention. Initially, the state machine is in an idle state and remains inactive until it decides that a packet data comes from the physical medium (e.g., the physical medium 141 of FIG. 9). For example, in condition 1 2 0 4 'if it decides that a packet of data is coming in, the state machine will proceed to a data state 1 2 0 6 in which the current packet is passed through the receiver FC / GMI I 9 06 and receiver LLC interface are processed. In the data state 1 2 06, it is also determined in the state 1 2 0 8 that the paper size applies to the Chinese National Standard (CNS) A4 specification (210.X297 mm) • 75- / 1674 44 A7 B7 5 The invention description (73) determines whether a packet is continuing, and if a packet is entering, the state machine will remain in the data state 1 2 0 6 in which the received packet is passed through the SUPERMAC Rx controller 120. However, if it decides in state 1208 that no packet is entering, the state will ‘enter a carrier extension state 1 2 1 0 in which a proper carrier extension system is processed. In this embodiment, the current packet will remain in the carrier extended state 1210 until it determines in the state 1212 that the appropriate packet length is at least 5 12 bytes (when in carrier expansion mode). Once it decides that the packet length is valid, the state will return to the idle state 1 2 0 2 indicating that the current packet is being processed correctly by the receiver. On the other hand, if it decides that the appropriate packet length is not valid in state 1 2 1 2 and it decides that a packet is entering in state 1 2 1 4, the state machine will enter a flush state, The inactive packet and the incoming packet in this state are washed (ie, two packets are washed). If no packet is entering, the state will enter the idle state 1 2 0 2 ° When the state machine is in the carrier expansion state, it again determines whether a packet is entering in state 1 2 1 4. For example, suppose a first-packet is processed in the valid state 1 2 1 0, and a second packet arrives before the first packet is valid (ie, state 12 14 is true). When this happens, the state machine will enter the erasure state 1 2 1 8 in which both the first and second packets are also eradicated. That is, both the first packet and the second packet that arrived when the first packet was valid are deleted in state 1 2 1 8 "In addition, if a packet and -76- Refill the matter i: li this page) This paper size applies to Chinese prisoner Biaojin (C'NS) / \ 4 size (210 X 297 mm) 5 4 74 44 A7 ______B? V. Description of the invention P) Any other package in The state machine is in the erasure state 1 2 1 8 and enters as determined in the state 1 2 1 6, then the packet area is also eradicated. Then a processing unit 1 2 2 0-generally in the carrier expansion mode, is to receive non-valid packets and any packets that avoid previously received packets ... from valid to a maximum packet length of about 512 bytes. Once the unwanted packet is purged, the state machine will return to idle without receiving packets that are not worn on the receiving side. This has the advantage that this feature is an example of the flexibility and precise error checking performed in S U P E RMA C CORE 1 1 6 according to an embodiment of the present invention further. FIG. 13 is a packet generation architecture according to an embodiment of the present invention. The user interface is used to construct packet data before transmission. In this embodiment, a packet count column 1320 is displayed at the top left-hand corner of the packet generation structure 1302 to confirm the number of packets contained in the packet column 1306 (i.e., in the packet). As mentioned, the packet column 1306 contains some example packets, including packets 1 3 2 2 and packets 1 3 2 4. Of course, any number of packets can be included in the packet field 1306, and additional packets can be added by selecting the ADD image button 1 3 2 6 according to an embodiment of the present invention. As shown, each packet contained in the packet field 1306 has various combined characteristics, which are based on user preferences. For example, appropriate variables may include: internal packet gap (IPG) 1 308, prior 1310, destination address 1312, source address 1314, length field 1 3 1 6 and data field 1 3 1 8. In this embodiment (-1¾ Jingji's precautions are repeated on this page) The paper size is used in China S house standard 4M C'NS) 4 size (2IOx2W mm) -77- Α7 Β7 w:; p : .- i! r-, in the final award, the cooperation of local labor and consumption. Mu Yin 1i V. Invention description p), the number 10 indicates the number of "16-bit" increase, and the number is defined as a joint The actual number of individual internal packet gaps. Then, in this example, the I PG system of the cited packet 1 322 (16 × 16 bits = 160 bits) is 160 bits. Therefore, a user can program any number in the I PG field · bit 13 0, and the number can be multiplied by 16 to reach the actual number of bits in the internal packet gap. In this example, the display of the antecedent field 1 3 1 0 is when the packet 1 3 2 2 is enabled, however, it should be understood that the antecedent deactivation can be simply modified as described above with respect to an antecedent selection field And disabling. Of course, the user interface screen drives appropriate software and the integrated circuit hardware included therein, and the software and hardware can perform processing operations according to this embodiment. In this way, a destination address 1312 and a source address 1314 are displayed at arbitrary addresses that can be modified according to user needs. The advantage is that the above module allows the user to modify its variables by simply selecting a packet and modifying it on a packet-by-packet basis. Also shown is the length field 1 3 1 6. The 1 3 1 6 confirms that the length of the sample packet 1 3 2 2 is 5 1 2 bytes, although any appropriate length can be selected by appropriately entering the ideal frame. . Finally, the data field 1 3 1 8 confirms the data of the packet 1 3 2 2 for modification. As is known in this art, the data field can be any of the following appropriate bit constructs, including: all zeros, all one's spaced one and zero, four consecutive one followed by four zeros, five consecutive One by one followed by five zeros, arbitrary bit configurations, and a modified bit pattern provided by the user. In this example, the data field 1318 contains modification data provided by the user. (τίι read the back-of-the-moment note and re-catch this book I j-丨 booked-· This paper is in use ® S 家 橾 聪 (C'NS) Λ4 specification (2 丨 0 乂 297 public 嫠) -78 -457444 A7 ______ B7 V. Description of the invention 怍) Further shown is a second example packet 1 324 with an IPG of 20. As mentioned earlier, an I PG of 20 is multiplied by 16 to reach the 3 2 0 bits of the programmable internal packet gap. In this example, the antecedent packet 1 3 2 4 is displayed in order to de-enable it, and the ‘appropriate purpose and number of source addresses can be appropriately entered by the user. Further, the length of the cited packet 1 3 2 4 is displayed in 64 bytes, and the data field 1 3 1 8 is displayed as all (one for all) as described above. Figure 14 shows an example packet definition user interface 1420 according to an embodiment of the present invention. Via this user interface, a user can precisely define the appropriate packet characteristics on a packet-by-packet basis. Then, once a user selects another packet field from the packet field 1306 of FIG. 13, the packet definition user interface 1420 of FIG. 14 can be displayed by the user for modification. From this user interface, the user can appropriately set the internal packet gap field 1 3 0 8, the destination address field 1 3 1 2, the source address field 1 3 1 4, the length field 1 3 1 6, And data style fields 1 3 1 8. In addition, the user can also choose the appropriate patterns 1414a and 1414b corresponding to the destination address 1 3 1 2 and the source address 1314, respectively. For example | By changing the mode 1414 and 1 4 1 4 b, the user can appropriately increase or decrease the appropriate input destination or source address. In another embodiment, the user may also select 1 4 1 4 a and 1 4 1 4 b to provide any destination address or source address. Therefore, the advantage is that the user orders I_ -I--I- n < IJ. J Jt n. ^; cw please recite νξ..vi intentions on this page) This paper is applicable to the standard of Chinese prisoners (CNS) / \ 4 (2 丨 0X297) 嫠 -79- 457444 Α7 Β7 V. Description of the invention β) Each of the interfaces is highly controlled and modularized by appropriately modifying the characteristics of the transmission packets based on the traffic-based MA C 1 50 (Figure 2). Further shown is a selection box 1 2 4 4 which allows the user to select antecedent, automatic padding, CRC, bit error ', and sequence. As mentioned above, if the user selects preemption, CRC, automatic padding, bit error, and serial number, these functions will be applied to the currently selected packet appropriately. In this embodiment, bit errors allow an arbitrary number of erroneous bits to be directed into a packet being transmitted in order to determine the response of a receiving station. Moreover, the serial number allows the user to add a serial number to each packet being transmitted, so that the user can confirm and decide whether the fixed packet with the attached serial number collides. Therefore, when a packet containing a sequence number is transmitted, it may determine whether any transmitted packets are in a collision or have any errors in them. This is even more characteristic when the packet has a short characteristic and is being transmitted at a speed close to one billion bits according to an embodiment of the present invention. According to this embodiment, the ability to provide serial numbers allows the user to transmit without having to provide a carrier extension to increase the packet size. Finally, the packet definition window 1402 displays a data field 1420. The 1420 is used to display the original data contained in the individual memory address position 1422. Therefore, as known to those skilled in the art, for each memory location, the data being transmitted to the selected one in Figure 8 will be joined ". Figure 15A is a user of a status interface window 1520 Interface, the 152 is a display transmission according to an embodiment of the present invention and -80- ---- · ---- II s ^-f sentence 1 read the back note of the general matter on this page) I. Λ- This paper's thick scale is suitable for China® Family Sample (C'NS) Λ4 specification (21flx 297 cm) 4 4 4 A7 B7 V. Invention Description 78) Reception status information. Generally speaking, the 'status interface 1 50 2 contains a packet and generates a status list 1 5 0 8'. The 1 5 0 8 shows various characteristics of the transfer operation being processed. For example, the variables displayed in the packet generation status table 1508 include: (a) — total transmission packet fields; (b) — 'total transmission byte fields; (c) — broadcast field (D) — a multiple broadcast field; (e) — a single broadcast field; (f) a single collision field: (g) — a multiple collision field: (h) — a most recent collision field (I) an excessive collision field: (j) an excessive collision delay: (k) a delayed field: (1) an insufficient field; and (m) a jump field. In this embodiment > the appropriate field displays the " real-time " information when the packet data is actually transmitted. Then, this type of information allows users such as network managers to monitor Transmission characteristics of a separate network. In this embodiment, when an transmission image (icon) 1 5 0 4 or a transmission button is selected, the transmission is appropriately placed, and the "transmission rate" graphics window 1 5 1 4 It can be displayed to identify the characteristics of packet data transmission. Also shown is a packet processor status table 15 1 0, which is according to an embodiment of the present invention and is responsible for processing the SUPERMAC Rx controller 1 2 0 based on the traffic based MAC 1 50 Processing of received packet data. For example, the packet processor status table 15 1 0 contains the following information: (a) total received packets; (b) total received bytes: (c.) Broadcast; (d) multiple propagation: (e) single Broadcast: (f) CRC error; (g) Combining error; J. .I- II i 1 I I--line r IJ-1—Ί This paper standard is used in China 1¾ house standard (CNS) 8 4 (2 丨 〇χ297mm) 81-5 4 4 4 A7 _B7 V. Description of the invention) (h) runts (undersized packets); (i) giants: and (j) overflow. In addition, The architecture information is also provided in the packet generator status table 15 08 and the packet processor status table 15 1 0. For the packet generation status table 158, the architecture information is provided for both the transmission mode and the packet count. For the packet processor status table 151, the architecture information is provided for miscellaneous data, multiplex broadcasts, broadcast data, C R C error data, misalignment data 'short packet data, and huge packet data. Then, during the receiving operation, a receiver image button 1 5 0 5 or a receive button 1 5 2 2 is selected to receive the function with the initial packet processor status table 1 5 1 0, the 1 5 1 0 system It can be displayed numerically and graphically in the reception rate window 1516. In this example, both the transmission rate window 1 5 1 4 and the reception rate window 1 5 1 6 give information about the relevant packet rate per second (ie, pkts / sec) that will be transmitted or received by the appropriate receiving and transmitting unit. display. As shown, the transmission rate is 175 packets per second, and the reception rate is 1000 packets per second. However, it should be understood that the reception and transmission rate indicates an embodiment and any appropriate transmission and reception rate may be displayed in the transmission rate window 1514 and the reception rate window 1516 according to the parameters of the combined network. In addition, the transmission rate window 1 5 1 4 and the reception rate window 1 5 1 6 both have a scaling graphic user interface ruler to appropriately display information in each graphic window. And, by selecting a graphic image 1 5 0 6, the user can properly scale the graphic window ^ 1 1 li I-n ^^ 1 Jii! 1 Please take the back, Jiang Yi matters -44¾ (Benedict)

'1T This paper size is suitable for Sichuan Chuanzhong 111¾¾: Standard (C'NS) Α4 size (210x297 mm) -82- 457 4 4 A7 B7: · -'ϋ; ν 屮 · ν # ^ 局 兵 -T-: .ift fee cooperation " printing * '' clothing V. invention note) information displayed in the mouth or change the characteristics of the information being displayed. Of course, when the transmitting and receiving state is generated in time, the user can stop transmitting properly by selecting a button 1 2 5 or stop receiving function by selecting a button 1 5 2 4. FIG. 15B shows a graphical architecture window 1550. The 1550 is displayed to the user with the selected image 1506 of FIG. 15A. For example, the user may select graph 1 or 2 to draw any information displayed in the packet generation status table 1508 or the packet processor status table 1510. Next, although for the convenience of explanation and explanation, only transmission and reception rates are available, it should be understood that any appropriate information can be displayed in the graphical window of FIG. 15A. Also shown are the "sampling cycles" (seconds) 1 5 5 6 and 1 5 5 8 for graphics 1 and 2 respectively, which can be used to select the appropriate sampling rate for each window combined in Figure 1 5A . Finally, the maximum / minimum amount of a scale can be used by appropriate selection of the appropriate scale image 1550 of Figure 15B. FIG. 16 is a receiving data buffer window 1602, which can be displayed to the user according to the selected receiving data buffer pattern 1570 of FIG. 15A. In a display field 1604, a list of packets received by the receiver is display user information. In this example, the number of packets is 1, the number of packets is 2 'and the number of packets up to N is displayed in the display field 1604. Once an individual packet is selected from the display field 1604, the user can select an individual packet by executing an appropriate selection device. Once a packet is selected, the appropriate packet characteristics are displayed to the user in the packet characteristics field 1640. ----------- ^ ------ Subscribe ------ ^-&l; (" Also read the back ..; 1- 恋 事 ^ 再 堉 3 pages ) This paper uses the Chinese standard 4 * (('NS) Λ4 size (2IOX25 »7mm) -83- 45744. A7 B7 V. Description of the invention π) Packet characteristics field 1 6 0 4 Receiving various characteristics of the packet. For example, the received packet information related to the length 1 6 0, the destination address 1608, the source address 1610, the data address 1612, the CRC 1 6 1 4, and the sequence 1 6 1 6 is used for display Information. Also provided is a check box which confirms whether the received packet has a C R C error, an alignment error, or a short or huge packet. Then, once each packet has been received, the user will only have individual packets in the packet field 160, and all its appropriate characteristics will show the user's simple information. Also shown is a raw memory data dump field 1620, which is used to display the attributes of the packet data received from the receiving side of the traffic-based MA C 1 50 based on FIG. 2. Of course, the received data should include the combined memory address to simplify modification and reference. FIG. 17 is a packet processor architecture window 1702. The 1702 is used to perform a management filtering function for data received by a receiver according to an embodiment of the present invention. For example, a general selection field 1704 display includes: (a) Miscellaneous, (b) Multiple Broadcast, (c) Broadcast, (d) CRC Error, (e) Arrangement Error, (f) Short Packet, and ( g) Huge packet selection characteristics. In this example, the miscellaneous selection check box is used as a filter and checks every part of the received packet (ie, although an error occurs) when performing a diagnostic analysis. The multiple broadcast selection check box is used when a user wants to construct the packet processor to receive and inspect a packet having a multiple broadcast destination address. The broadcast selection check box is used to construct the packet processor to check the packet. t) -84- -bad # 4'- 局 @ 工 consuming cooperatives printed A / ^ —I *, A7 B7 V. Invention explanation) Broadcast to this network (ie, the destination address is a broadcast address) . The CRC error selection check box is used to construct the packet processor to check (i.e., 'filter and check') packets with C R C errors. The alignment error selection check box is used to enable the ‘receive packet containing the alignment error. As is well known, for a system of 10 Mb ps, the permutation error is described as a dribble, and for 100 M bps, the permutation error is described as a four-bit error (4-bit), which is located at 100 For 0 M bps systems (ie, gigabits), permutation errors are described as byte errors. Finally, the short packet selection check box is used so that the packet shown as smaller than 64 bytes is used, and the large packet selection check box is used so that the packet is shown larger than 1518 bytes. Of course, according to an embodiment of the present invention, a user can modify and define the minimum amount of packets and the maximum amount of packets by appropriately setting appropriate registers in the SUPERMAC core 116 of FIG. 3. Alternatively, this setting can be performed through an appropriate software user interface. Modify the filtering part 1 7 6 to provide users with the option of filtering the individual parts of the destination address 1708, source address 1710, and data pattern 1712. For example, by appropriately selecting the portion of the destination address (eg, masking the portion of the destination address selected), and by entering an appropriate corresponding bit pattern, the user can filter out the appropriate information to Perform management and diagnostic operations. Then, the user can mask and correspond to more than one part of the destination address. As shown, the user can mask both the corresponding destination and source address. However, it should be understood that the user interface can be extended to be more detailed ί 1! Γ. N Ini-^-1 I. i 1--I (For the precautions for reading first, then { : (ΐPage) This paper size is applicable to China National Standard (CNS) Α4 specification (mm) -85- 4 4 Α7 __ Β7 ___ 5. Description of the invention (83) It is detailed and corresponds to the operation that meets the needs of users. For A data pattern 1 7 1 2 allows the user to select an appropriate interval from the initial point of the appropriate packet (ie, generally a 16-bit offset) by entering the appropriate information in the corresponding field. Once an appropriate spacing is selected, the user can reconfirm one of the masks and a mapping of the data pattern being filtered. As used herein, references to the IEEE 802.3 standard should be understood to include all current IEEE 802.3 standards. Contains; (a) IEEE 802.3 standard (100 Mbps-fast Ethernet) IEEE std 802.3u-1995; (b) *? Τ IEEE 802.3z standard (1000Mbps-billion-bit Ethernet ): And (c) ISO / IEC 8 8 2-3 'ANSI / ◊ I * -y IEEE Std 802.3 (No. (Sixth Edition 1996). All the standards shown above are incorporated for reference.: R; '" · Ministry of Justice Decision-making Bureau β-τ' · '; β " Cooperative Society Printing Implementation of the invention Use any type of integrated circuit logic or software to drive the operations performed by the computer. For example, a hardware description language (HDL) -based design and synthesis program can be used to design an application according to an embodiment of the invention. A silicon level circuit is necessary for proper execution of data and control operations. For example, a VHD L® hardware description language developed by the New York I EE Ε organization can be used to design an appropriate silicon level architecture .Although any suitable design tool can be used, another price-purchasing tool also includes a hardware description language "Verilog® 'This woodworking paper size is applicable to the Chinese National Standard (CNS) from the specification (297 gigabytes) -86- / 1 Λ Λ Μ Β7 i? &Quot;. Printed by the Ministry of Science and Technology Bureau β-τ Consumer Cooperative Co., Ltd. 5. Description of Invention M) The tool was developed by Cadence Design System, Inc. of Santa Clara, California. This invention uses a variety of Related to storage The computer in the computer system performs operations on the data. This operation is the physical manipulation of some physical quantities. In general, although it is not required, this quantity can be stored, transmitted, combined, and compared; otherwise, it is manipulation, electronic Or in the form of magnetic signals. Further, the execution of such manipulations is usually best in the form of, for example, generation, confirmation, decision, or comparison. Any operations described herein that form part of the invention are generally machine operations. The invention also relates to a device or device to perform such operations. The device may be specially constructed for the required purpose, or it may be a general purpose computer selectively triggered or constructed by a computer program stored in the computer. In particular, a variety of general-purpose machines can be used in the computer programs shown here, or it can be more convenient to construct a more special device to perform the required operations. The structure of one embodiment of the present invention is described below. FIG. 18 is a block diagram of a 1800 embodiment of a computer system to perform the processing of the present invention. The computer system 1 800 includes a digital computer 1802, a display screen (or monitor) 1804, and a keyboard 1806, a floppy disk drive 1808, a hard disk drive 1810, a network interface 1812, and a Keyboard 1814. The digital computer 1 8 0 2 includes a microprocessor 1 8 1 6, a memory bus 1818, a random access memory (RAM) 1820, a read-only memory (ROM) 1822, and a peripheral bus 1824 n ^ p.-in ^ — -HI 1 ^^^ 1 ---- I ^^^ 1 nf ^ i-. J • · · ν *-° (Read the precautions for the back and then " Άthis page} This paper size is applicable to Chinese stores ((,,), 6, 4 gauges (2! 0 > < 297 gongshen) -87- 457444 A7 B7 5. Invention description from 5), and a keyboard controller 1 8 2 6. The digital computer 1 800 can be a personal computer (such as an IB-compatible personal computer, a Macintosh computer or a Macintosh-compatible computer), a workstation computer (such as a Sun Microsystem or an HP workstation) ), Or some other type of computer. The microcomputer 1 8 1 6 is a general purpose digital processor that controls the operation of the computer system 1 800. The microprocessor 1 8 16 can be a A single chip processor may be executed with multiple components. By using instructions obtained from the memory, the microprocessor 1 8 1 6 controls the reception and manipulation of input data Output and display data to the output device. According to the present invention, the individual functions of the microprocessor 1 8 16 are assisted in packet processing and network management. The memory bus 1 8 1 8 has a microprocessor 1 8 1 6 is used to access the RAM 1820 and ROM 1822. The RAM 1 8 2 0 is used by the microprocessor as general storage area and drawing board memory 'and can also be used to store input data and processed data Data. The ROM 1822 can be used to store the instructions or code connected to the microprocessor 1 8 1 6 and other data. The peripheral bus 1 8 2 4 is used to access the digital computer 1 Input, output, and storage devices used in 80.2. In the above embodiments, these devices include: the display screen 1804, the printer device 1806, the floppy disk drive 1808, and the hard disk. Machine 1810, and the network interface 1 8 1 2. The keyboard controller 1 8 2 6 is used to receive input from the keyboard 1 8 1 4 and send each pressed through the network 1 8 2 8 Decode the symbol below to the microprocessor (read the back note against 1) Yiheng Xiang re Mg this page) Chinese paper standard (C'NS) Λ4 specification (210X 297 mm) for the back scale 4 of this paper -88- 457444 A7 B7 ^ # " Central ^ quasi ^ Ma ^ Consumer Hezhu? :! Yin Yang V. Description of the invention) 18 16 ° The display image 1 0 0 4 is an output device, which displays the data through the peripheral bus 1 8 2 4 and the microprocessor in the computer system 1 800 1 8 1 6 Provided or provided by other components to display data. This printer unit 1 800 is designed to supply images on paper or a similar surface when operating with a printer. Others, such as a drafting machine, a style setter can be used in place of or incorporation in the printer device 180. The floppy disk drive 1 8 0 and the hard disk drive 1 8 1 0 can be used to store various types of data. The floppy disk drive 1 8 0 8 can be used to transfer this data to other computer systems, while the hard disk drive 1 8 1 0 allows fast access to stored large amounts of data. The operating system knows that the microprocessor 1816 is operated to execute computer code and generate and use data. The computer code and data can reside in RAM 1820, ROM 1822, or hard disk drive 182. The computer code and data may also reside on a removable program medium and loaded or installed into the computer system when needed. Removable media include, for example: CD — ROM, PC — CARD, floppy disks, and magnetic tape. The network interface 1812 is used to send and receive data via a network connected to other computer systems. An interface card or similar device and appropriate software executed by the microprocessor 1816 can be used to connect the computer system 1800 to an existing network and transmit data according to standard protocols. The keyboard 1 8 1 4 is used to input instructions and other instructions to it (^ read the reverse first. 1 · 1- read the matter 4 " = 1 clever page) This paper standard uses the KS standard (C- NS) Λ4 Regulations U] 0_X 297 Gong) -89- Printed by β-t Consumer Cooperatives of the Bureau of Standards of the tty Ministry 4 4 4 A7 ______B7_ _ 5. Description of the invention $ 7) Computer system 1 800. Other types of user input devices can also be used in the present invention. For example, pointing devices such as computer mice, trackballs, stylus pens, and tablets can be used to control the screen of a general computer. The present invention can be executed on a computer-readable code on a computer-readable medium. The computer readout medium is any kind of data storage device that can store data which can be later read out by a computer system. Examples of computer-readable media include: read-only memory, random access memory, CD-ROMs, magnetic tapes, optical data storage devices, and so on. The computer readout medium can be dispersed via a network connected to various computer systems so that the computer readout code can be stored and executed in a distributed manner. Although the above invention has been described in detail for the purpose of understanding, the changes and modifications made are still within the scope of the appended patent application. It should be understood that the various processing functions described above may be via silicon such as a hard volume circuit or software code that may be stored or retrieved from any suitable storage medium. For example, such storage media include disk drives, hard drives, floppy drives, server computers, remote network computers, and so on. In addition, it should be understood that the above features and functions are backward compatible with 10Mb ps Ethernet systems and 100 Mb ps fast Ethernet systems and related asynchronous transfer mode (ATM) systems. Of course, the above embodiments can also be applied to switched and non-switched, and full / half duplex network systems. Next, this embodiment is shown rather than limited, and the present invention is not limited to the details detailed herein, but may be modified within the equivalent scope of the attached patent application. ---, ------------ Order ------ of--------- (taboo first read and read ..; 1 meaning thing β 桢·! ≪ :: · this page） This paper is in the state of Shizhou® National Standard (C'NS) Λ4 (210X 297mm) .90-

Claims (1)

457444 3 Patch 0 years 3, Γ A8B8C8D8 VI. Patent Application Scope Annex I No. 87 10 1839 Patent Application Chinese Application Patent Scope Amendment The Republic of China March 1990 Amendment 1, a media access controller, contains a transmission The medium access controller is structured to process incoming packet data received from the upper layer and transmitted to an external layer; a receiving medium access controller is structured to process incoming packet data received from the physical layer and transmitted to the upper layer. ; A multi-packet queue FIF 0 is transmitted to receive the outbound packet data from the upper layer before being transmitted to the transmission medium access controller; a multi-packet queue FI FO is received to receive the accesses received by the receiving medium. Inbound packet data received by the controller: and a media access controller management program, the program is interfaced with the transmitting and receiving media access controller, the media access management program is responsible for managing Packet queue FIF ◦ packet data traffic. 2. The media access controller according to item 1 of the patent application scope further includes a parallel event processor for parallel processing of management information and control information passing through the transmission media access controller and receiving the media access controller. 3. The media access controller according to item 1 of the patent application scope, wherein the parallel event processor includes a packet buffer to store simple network management protocol information and remote monitoring information as network traffic statistics. 4 · If the media access controller in the scope of patent application No. 1 'where the paper size is in accordance with the Chinese National Standard (CNS) A4 specification (210 X 297 male «) (Please read the precautions on the back before filling this page) I · --- -----Order ------ II Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 457444 Α8 Β8 C8 D8 VI. Patent Application Scope The parallel event processor contains a programmable counter to store Information about new network processing events and statistics. {Please read the notes on the back before filling this page) 5. If the media access controller in any of the patent application scopes 1-3 'further includes a first internal micro-RISC stream processor to handle the Transmitting multiple queues FIF0 and packet data transmitted between the transmission medium access controllers, the first internal micro-RISC stream processor is also structured to handle the receiving medium access controllers and the receiving multiple queues FIF 0 Packet data sent. 6. The media access controller in item 5 of the scope of patent application, wherein the parallel event processor further includes a second internal micro-r ISC stream processor, the processor is structured to selectively filter the first Packet data processed by the internal micro-RISC stream processor, wherein the selected filter provides packet data to process management requests. 7. The media access controller as described in item 6 of the patent application scope, wherein the second internal micro-RISC stream processor is structured to receive data from the transmission media access controller and the receiving media access controller. Select the packet profile to handle the management request. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 8 such as the media access controller in item 6 of the scope of patent application, where the second internal micro_RISC stream processor stores the selected packet information in the parallel event Statistical counter in the processor ° 9. The media access controller of any one of patent applications No. 1 to 3, further including a transmitting and receiving network traffic management F 1 controller, which transmits network traffic management FIF 0 controller is used to transmit multiple packets. F 〖F〇 and communication between the media access controller management program -2- This paper size applies to China National Standard (CNS) A4 specification (210 X 297 public «〉 A8B8C8D8 457444 6. In the scope of patent application, the receiving network traffic management FIF 0 controller communicates between the receiving multi-packet queue FIF 0 and the media access controller management program. 1 0. As described in item 1 of the scope of patent application The media access controller further includes a network data bus interface controller, which is used to transmit and receive multiple packet queues FIF 0 and the network data system bus. Communicate the packet data information. 1 1. For example, the media access controller in item 10 of the scope of patent application, wherein the network data bus interface controller communicates with the media access controller management program. 1 2. The media access control device of any one of the items 1 to 3 of the scope of patent application, further comprising a flow control bus interface controller for parallel event processors and a bus with a network data system. Communication between the management / control buses 1 3 · — A network interface system, including: a media access controller for processing the transmission data received from the upper layer and transmitting the processed transmission data to the lower layer 'Process the received data received from the lower layer and send the received data to the upper layer. The media access controller is structured to monitor the data flow between the upper layer and the lower layer. A data bus is used as the data and data control information. Communication between the upper layer and the media access controller; and a management control bus, which serves as the management control information at the upper layer and the media The access controllers communicate with each other, and the management control bus is independent of the data bus. 1 4. For the network interface system in item 13 of the scope of patent application, the paper size applies to the national standard (CNS) A4 specifications (210 * 297 public love) J 14 a ^ in κι nd .1 n-I- n-δ 'It I nnnnn 1 I i Please read the precautions on the back before filling this page) Ministry of Economy Wisdom Printed by the employee's consumer cooperative of the Property Bureau 457441 Α8 Β8 C8 D8 6. In the scope of patent application, the media access controller includes: A transmission controller, which is transmitted to the lower-level transmission data as a process. The process includes transmitting the data to At least one header is packetized;-the receiving controller, as processing data from the lower layer connected to a physical layer, the processing includes: removing at least one header and communicating the received data to the upper layer; a parallel event processing Controller, coupled to the control stream to handle management tasks. 1 5 · As for the network interface system in item 14 of the scope of patent application, wherein the medium access controller further includes: — a data management unit, which serves as an interface with the transmission controller and the receiving controller, and the transmission controller And the receiving controller communicates with the data via the first bus via the architecture: a first processor to filter the selected data that is communicating with the transmitting controller from the upper layer, and to filter the received data The controller and the selected data communicated with the upper layer; a second processor, which is structured to receive the selected data passed by the first microprocessor, and communicates with the filtered data through the second bus . 16. If the network interface system in item 15 of the scope of patent application, wherein the first bus of the media access controller is in communication with a transmission buffer and a reception buffer, the transmission buffer and the reception buffer The device is structured to store data being transmitted through the transmitting controller and to store data being transmitted through the receiving controller. This paper size applies to China National Standard (CNS) A4 specifications (210 * 297 mm) (guess first read the precautions on the back before filling out this page) Printed by the Intellectual Property Bureau's Consumer Cooperatives of the Ministry of Economic Affairs -4- 45744 A8 88 CS D8 VI. Scope of patent application (please read the unintentional matter on the back before filling out this page) 1 7. If the scope of patent application is in item 16 In the network interface system, the transmitting buffer and the receiving buffer of the media access controller are structured to store a plurality of data packets. 18. The network interface system in item 17 of the scope of patent application, wherein the media access controller further includes: a transmission flow management program, which is communicating with the transmission buffer to control the storage in the transmission buffer The transmission of a plurality of data packets in the '; and a receiving flow management program is communicating with the receiving buffer to control the transmission of the plurality of data packets stored in the receiving buffer. 19. If the network interface system in item 18 of the scope of patent application, wherein the transmission flow management program of the media access controller is structured to calculate each of the loop sequence numbering strategies and store them in the transmission buffer Data packets in the server. 20. If the network interface system in item 18 of the scope of patent application, wherein the receiving traffic management program of the media access controller is structured to calculate each of the ring serial numbering strategies and store it in the receiving buffer Data packets in the server. Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, M Consumer Cooperative, such as the network interface system in item 18 of the patent application > where the transmission flow management program of the media access controller is structured to indicate when to detect In a collision, the transmission buffer retransmits the data packet stored in the transmission buffer to the transmission controller. 2 2. The network interface system according to any one of claims 18 to 21 in the scope of patent application, wherein the packet data stored in the transmission buffer in the media access controller is connected to the selected loop sequence Counting Strategies -5- This paper size is applicable to China Standard for Household Standards (CNS) A4 (210 * 297 mm) 457444 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs? Clothing 6. Scope of patent application All packets are transmitted before they are cleaned. 2 3 The network interface system according to any one of the scope of the patent application] _ 6 _ 2 1 where the media access controller is programmable through a drawing user interface. 2 4. A method for manufacturing a media access controller that processes data transmission requests, data reception requests, and monitors the data flow through the media access controller. To communicate with upper and lower layers, the method includes the following steps: Integrate a first bus to transmit data to and from the media access controller: and integrate a second bus to manage management control requests When data transmission is in progress> communicating with the media access controller, the second bus is coupled to a parallel event processor, the processor includes a micro processor, and a processor is used as filtering through the first Selected data transmitted by a bus. 25. The method for manufacturing a media access controller in item 24 of the scope of patent application, further comprising the steps of: integrating a transmission controller and a receiving controller in communication with the first bus; and integrating a Management office_ controller to control the operation of the transmitting controller and the receiving controller. 2 6. A transmission medium access controller including: a transmission interface unit 1 configured to receive packet data from an upper layer, and transmit control information and control information: a transmission controller to process according to the control information received from the upper layer Packet information, the transmission control block is bidirectionally coupled to the transmission interface unit (please read the precautions on the back before filling this page) This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)- 6- VI. Scope of patent application 1 Transmission public block for monitoring and handling of events in the transmission control block: < Please read the unintentional matter on the back before filling this page) A redundant inspection unit for transmission cycle It communicates with the transmission control block: and an interface unit, which is structured to receive the packet data from the redundant inspection unit of the transmission cycle before the packet data is transmitted to the physical layer. 27. For example, the transmission medium access controller in item 26 of the patent application scope, wherein the interface unit is configured to communicate with a physical layer of an optical fiber channel. "28. For example, the transmission in item 27 of the patent application scope The media access controller, wherein the media unit communicates with the physical layer of the optical fiber channel through an optical fiber channel encoder. 2 9. The transmission medium access controller according to any one of claims 26 to 28 in the patent application scope, wherein the interface unit includes a gigabit media independent interface, which is structured to communicate with an Ethernet Physical layer communication. / / 3 0. — A communication method in a media access controller printed by the consumer consumption cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, which communicates with the upper and lower entities through the structure 1 The media access controller includes a transmission control A device for receiving and processing a data transmission request from the upper layer and outputting the received data to the physical layer 1 The method includes: receiving data 1 from the upper layer and processing the received data through the transmission controller, and the execution of the processing is According to the setting of a plurality of control registers incorporated in the transmission controller; when data is being processed via the transmission controller > receiving a control signal to modify at least one of the plurality of control registers ; And this paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 male *) 4 h 7/1/1/1 -i ice —Γ * T A8 B8 C8 D8 Modification of at least one of the plurality of control registers in the controller to change processing data processed in the transmission controller; and outputting the processed data. 31. The method as described in item 30 of the scope of patent application, wherein the step of receiving the control signal is performed in parallel with receiving data from the upper layer. 3 2. The method as described in item 30 of the scope of patent application, wherein the plurality of control registers include: an instruction agreement register, a delay period register, a time slot register * a retry limit register Register 'and a programmable minimum and maximum packet size register. 3 3. The method as in item 32 of the scope of patent application, wherein the delay period register is configured to define a waiting period of the transmitter after detecting a collision and before retransmission, the delay period register When the data in the transmission controller is processed, it can be modified. 3 4. As the method in the scope of patent application No. 32, where the time slot register is constructed to define the backed-up unit, the time slot register is in the process of processing the data in the transfer controller. Department can be modified. 35 • As in the method in the scope of patent application No. 32, wherein the retry limit register is constructed to define the number of attempts to retransmit before the data to be transmitted is discarded, the retry limit register is in place When the data in the transmission controller is processed, it can be modified 3 3 6. For example, the method in item 32 of the scope of patent application 'where the programmable minimum and maximum packet size register is the data packet definition The size of the packet data is the data in the transmission controller. The size of the paper is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling in (This page) * I 9 1 1 III «— Ι1Ϊ1Ι — — Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 457444 S_ 6. The scope of patent application can be modified. 3 7. If the scope of patent application is 3 2 — The method of any one of 3 to 6, further comprising the steps of: confirming one of a plurality of selected control registers to be modified by the received control signal; setting one in the control A control signal in the bus; sending a control information set in the control bus; and loading the selected control register from the control bus. 3 8. As the scope of patent application No. 3 2-3 6 The method of any one of clauses, wherein the instruction agreement register includes a plurality of flags for enabling and disabling the data processing function located in the transmission controller. 3 9. As in item 38 of the scope of patent application Method * Among them, a plurality of flags are selected from the group consisting of an enable transmission flag, a full-duplex mode flag, an automatic plug flag | aperiodic repetition flag | And the group of forced transient flags. 4 0 · The method as in any one of items 32 to 36 of the scope of the patent application, wherein when the modified control register is constructed to change the transmission control The internal packet gap between adjacent packets transmitted by the router. 4 1. As in the method in the scope of patent application item 37, the step of receiving data from the upper layer includes: receiving a packet from the upper layer in a transmission control signal bus. Effective bit Receive a data ready flag from the upper layer in the signal bus: and this paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) Γ— [I 1TIIIIIII1 ·]! 111! 1 alii ——— — — Ί (Please read the notes on the back before filling this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs-9-A8i 457444 VI. Patent Application Scope Use the control signal bus to prepare the data and flag the upper level Phase communication 4 2. A transmission medium access controller, including: a transmission interface unit, which is structured to receive packet data from an upper layer, transmit control signals and control information. —The transmission control block is used to monitor and handle the events in the transmission control area; a transmission cycle redundant check unit is structured to receive packet data from the transmission interface unit, and the transmission control block is related to The transmission cycle repeat inspection unit communicates; and a transmission fiber channel and a gigabit media independent interface unit are structured to receive packet data from the transmission cycle repeat inspection unit before the packet data is transmitted to the physical medium. 43. The transmission medium access controller in item 42 of the scope of patent application, wherein the transmission control block further includes a back calculation unit and a delay calculation unit. 4 4 · If the media access controller in item 4 2 or 43 of the scope of patent application, the state machine includes a command control state machine, a frame control state machine and supporting logic unit 45 _If the scope of patent application is 42 Or the transmission medium access controller in item 43, further comprising a transmission control register included in a transmission control register block of one of the transmission interface units, configured to receive control information, and at least a portion of the transmission control signal Memory block. 4 6 .If the transmission media access control in item 45 of the scope of the patent application, the paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) — — I1I—IIII — _- I-I! [I 1 II ^^ 11! 1111_ ^^ (Please read the precautions on the back, Luo Dong wrote this page first) Consumer Cooperation of Intellectual Property Bureau of the Ministry of Economic Affairs Du printed -10-457444 A8 B8 C8 D8 Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by Consumer Cooperatives 6. The patent application scope controller, where the transmission control register block contains a plurality of registers that are used to program the processing variables in the transmission control block. The transmission medium access controller of 46, wherein the plurality of registers include a register selected from an instruction protocol register, a delay period register, a time slot register, a retry limit register, and A programmable minimum and maximum packet size register. 48. For example, the transmission media access controller in item 45 of the patent application scope, wherein the plurality of registers are processed while the packet data is being processed. Stylized. *. 49. If applied The media access controller in Item 47, wherein the instruction protocol register includes a plurality of flags as processing variables that are set in the transmission control block and the periodic repetitive inspection unit. 50. If applying for a patent Transmission Media Access Controller in Scope Item 49, where multiple flags are selected from the group consisting of enable transmission flags, full-duplex mode flags, automatic padding flags, non-periodic repeating flags, non-loading Sub-Extended Flag | Group of Start Sampling Line Flags and Forced Transient Flags 5 1. Such as the media access controller in the scope of patent application No. 4 2 or 43, further including a transmission included A logic control unit in the interface unit, an area control logic unit structured to receive at least part of the transmission control signal, and for a packet data transmission event, a data ready flag is transmitted from the upper layer to the area control logic Unit, and a data ready flag is transmitted to the upper layer by the area control logic. 5 2. —A controller that controls the transmission of data between the physical layer and the upper layer. The controller Contains: K--I l · ----— 111-I 1 IIIII ----- 1 tf Ϊ l (Please read the precautions on the back before filling out this page) This paper size applies to Chinese National Standards (CNS) A4 size (210 X 297 mm > -11-4 5 7 4 4 A8 B8 C8 D8 Sixth, the scope of patent application-a transmitter 'as a data packet transmitted between the upper layer and the physical layer> The transmitter is configured to selectively insert a gap between serial data packets: (Page)-The delay period register can be optionally written to indicate the length of the internal packet gap, which is the gap between the sequence packet data being transmitted to the physical layer. 53. The controller as described in claim 52, wherein when the transmitter transmits data packets between the upper layer and the physical layer > the delay period register is modifiable. 54. The controller according to item 52 or 53 in the scope of patent application, wherein the packet transmission rate is set in the gap between the sequence data packets. 5 5. A media access controller for controlling data transmission between the physical layer and the upper layer 1 The media access controller includes: a transmitter for transmitting data between the upper layer and the physical layer; a retry limit register , Can be optionally written to programmatically transfer the number of times the media access controller attempts to transfer data before jumping out of the upper layer and the physical layer = printed by the Economic and Consumer Property Cooperative Bureau ’s Consumer Cooperatives 5 6. The media access controller of item 5, wherein the number of times that the media access controller attempts to transmit is adjusted upward to avoid jumping out during high traffic cycles. 5 7. A media access controller for controlling the transmission of data between the physical layer and the upper layer. The media access controller includes: a transmitter for transmitting data between the upper layer and the physical layer; a programmable Minimum and maximum packet size register 'The temporary storage 12 paper sizes are applicable to Chinese National Standard (CNS) A4 specifications (210 * 297 public love) Y Printed by the Intellectual Property Bureau of the Ministry of Economy Staff Consumer Cooperatives 5 4 A8B8C8D8 VI. Patent application The scope is selectively written to adjust the size of the packet data transmitted through the transmitter. 58.-A communication method in the medium access controller which is structured to communicate with the upper and lower physical layers. The medium access controller includes a receiving controller for receiving and processing from The lower layer receives the data request and transmits the received data to the upper layer. The method includes: receiving data from the lower layer and processing the received data through the receiving controller. The execution of the processing is based on the connection in the transmitting controller. Setting of multiple control registers; when data is being processed through the receiving controller, receiving a control signal to modify at least one of the plurality of control registers: and according to the combination in the receiving controller The modification of at least one of the plurality of control registers changes the processing data processed in the receiving controller: and outputs the processed data to an upper layer. 5 9. The method in item 58 of the scope of patent application | wherein the step of receiving the control signal is performed in parallel with the processing of the data contained in the receiving controller. 60. The method as described in item 58 or 59 of the scope of patent application, wherein changing the processing of the data processed in the receiving controller further includes modifying at least one flag contained in the receiving control register. 6 1. The method as described in item 58 of the scope of patent application, wherein the control register includes receiving the enable flag 'removal of the plug flag and starting the sampling line. The paper size is applicable to the Chinese family standard (CNS) A4. Specifications (210 * 297 mm) ----------------------------------- Order the line Precautions < «· Write this page) -13- A8 B8 C8 D8 VI. Patent application scope flag and self-receiving flag. (Please read the precautions on the back before filling out this page) 6 2. For the method in item 58 of the scope of patent application, where the control register includes the removal of the plug flag, the method further includes triggering the removal of the pad The congestion flag is used to remove excessive congestion data from the received packet data. 63 — A processing method for modifying the received data. The media access controller is structured to communicate with upper and lower physical layers. The media access controller includes a receiving controller for processing requests transmitted from the upper layer. And as processing the received data from the physical layer, the processing method of modifying the received data includes:. Processing the data passing through the receiving controller, the processing is based on the settings of the register included in the receiving controller; While processing by the receiving controller, transmitting a control signal as a modification register to the receiving controller; and changing the processing of the processed data according to the modification of the register included in the receiving controller. 64. The method for modifying the received data as described in item 63 of the scope of patent application, wherein the step of transmitting the control signal is parallel to the processing of the data contained in the receiving controller. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 65. If the processing method of modifying the received data is as described in item 63 of the scope of patent application, the register is a receiving control register, which is selected from At least one selected from the group consisting of a flag that can be flagged, a flag that has been removed from the pad, a flag that starts sampling lines, and a flag that accepts itself. 6 6. The processing method for modifying the received data as described in Item 65 of the scope of patent application, where the receiving enable flag is used to enable the receiving • 14- This paper size applies the Chinese National Standard (CNS) A4 specification (210 * 297 Public Love > VI. Apply for a patent scope controller, and when the data is being transmitted from the upper layer to the lower layer, the receiving enable flag is modifiable. (Please read the precautions on the back before filling in this (Page 7) The method for modifying the received data as described in Item 65 of the scope of patent application, wherein the control signal is received from the upper layer via the control bus; and the control signal is fetched so as to be included in the control The control information of the signal is loaded into the register. 6 8. The processing method of modifying the received data as described in item 63 of the scope of patent application | The step of processing the data via the receiving controller further includes: determining whether the upper layer is The data has been prepared; the packet is set to the effective bit of the control signal; and the data of the received controller is sent to the upper layer in response to the setting of the valid bit of the packet The processing method for modifying the received data as described in item 68 of the scope of patent application, wherein the step of processing the data through the receiving controller further includes: setting the receiving controller to prepare a flag for the data. Information to the upper level "Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives. 70. A receiving media access controller, including: a physical media receiving interface 1 for receiving packet data from the physical media, and from the fiber channel format and one billion The received packet data in one of the bit media independent formats is decoded; a receiver periodic repeat checker is structured to receive packet data from the physical media receiving interface unit: -15- This paper standard applies to the Chinese national standard < CNS) A4 specification (210 * 297 public address) 457444 A8 B8 C8 D8 Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and printed by 3 Industrial Consumer Cooperatives 6. Application scope for patents-Receiver interface unit, structured to receive from physical media Packet data of the interface unit and the receiver cycle repeat checker, and the receiver interface unit is connected from the upper layer A plurality of transmission control signals and control information; a receiving control block for processing the received packet data according to the received transmission control signals and the received control signals: the transmitter control block and the transmitter interface unit And the physical media receiving interface unit to communicate with; and a public block of the receiver as a monitor and responsible for processing events in the receiver control block. 7 1 · Receiving medium access control as in the 70th scope of the patent application The receiver control block is a receiving control state machine for transmitting the received packet data to the upper layer. 7 2 · As the receiving medium access controller in item 71 of the scope of patent application, wherein the receiving The control state machine checks for collisions and carrier extension requests. 7 3 If the receiving medium access controller in item 0 of the patent application, the transmitter interface unit further includes: a receiver control register unit, which stores a plurality of processing variables, and the receiver control temporarily The register is configured to receive control information and transmit at least a part of the plurality of control signals; and a receiver control logic unit 'receives at least a part of the plurality of control signals that determine the relevant transmission time. 7 4 .If the receiving media access control in item 73 of the scope of patent application, the paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm> -16-,] ..------ --------------- Order! --- I --- line (please fill in this page before the notice on Htt) 457444 A8 B3 CS D8 Employees of Intellectual Property Bureau, Ministry of Economic Affairs Printed by the Consumer Cooperative 6. The patent application scope controller 'where the receiver control register includes a flag selected from the receiving enable flag, removing the plug flag, starting the sampling line flag, and the self-receiving flag flag 7 5 · If the receiving media access controller in item 74 of the scope of patent application 'wherein the flag is programmable when the packet data is being processed. 7 6 .If the scope of patent application is item 70 In the receiving medium access controller 1, the public block of the receiver includes a waterfall public computer, which is extended to optimize the interruption of the central processing unit. 7 7. 76. The receiving medium access controller of item 6, wherein the waterfall type public computer is used to substantially The controller's public settings are continuously calculated ^ 7 8. — A computer-readable medium containing program instructions that drive the medium access controller that communicates with the upper and lower physical layers via the architecture. The medium access control The device includes a receiving controller for receiving and processing a request for receiving data from a lower layer, and transmitting the received data to an upper layer. The computer-readable medium includes: a program instruction for receiving data from a lower layer and The receiving controller processes the received data, and the processing is performed according to the settings of a plurality of control registers related to the transmitting controller: a program instruction, when the data is being processed by the receiving controller, Received as a control signal to modify at least one of the plurality of control registers: and program instructions, as a control paper related to the plurality of control registers related to the receiving controller, the Chinese National Standard (CNS) A4 specification (210 X 297) Mm> -17- I, ----- I ------ install -------- order -------- * line (please read the precautions on the back before IH) (Fill in this page) 457444 A8 B8 CS D8 VI. Modification of at least one of the patent application scope registers to change the processing of the data processed in the receiving controller; and (please read the precautions on the back before filling this page) Program instructions as Send the processed data. 7 9 · If the computer-readable medium in item 78 of the scope of patent application, the program instructions as the receiving control signal are executed in parallel with the processing data contained in the receiving controller. 80. The computer-readable medium in item 78 of the scope of patent application, wherein the program instructions for changing the data being processed in the receiving controller further include: Program instructions · At least as a modification contained in the receiving control register A flag. 81. The computer-readable medium according to item 80 of the scope of patent application, wherein the program instructions for modifying at least one flag included in the receiving control register are modified through a graphical user interface. 82. The computer-readable medium according to any one of claims 78-81 in the scope of patent application, wherein the medium access controller is programmable through a graphical user interface. Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -18- This paper size applies to China National Standard (CNS) A4 (210 * 297 mm)