TW457423B - Method and apparatus for cascading content addressable memory devices - Google Patents

Abstract

A method and apparatus for cascading content address memory (CAM) devices is disclosed. The method and apparatus may be particularly useful when depth cascading CAM devices that operate in a flow-through mode. In the flow-through mode, a compare instruction may be simultaneously provided to each CAM device in the cascade, and the match address, data stored at the matched location, or other status information may then be output to a common output data bus by the highest priority matching CAM device in the same cycle that the instruction is provided to the CAM devices. Each CAM device may have a cascade input and a cascade output to perform the cascade function. The cascade output of a higher priority CAM device may be connected to the cascade input of the next lower priority CAM device. The higher priority CAM device may assert a cascade signal on its cascade output at a predetermined time after receiving an input signal (e.g., a clock signal). Asserting the cascade signal may indicate that the higher priority CAM device has completed the compare instruction. When the lower priority CAM device detects that the cascade signal has been asserted on its cascade input, the lower priority CAM device may sample the match flag of the higher priority CAM device to determine if the lower priority CAM device may output its data to the common output data bus.

Description

Case number 87118088 and the year? Amendment ___ 5. Description of the invention ⑴ 'In general, the present invention relates to a content addressable memory (CAM) device. % Λ. A content-addressable memory (CAM) device is a storage device that can be instructed to compare specific types of comparative baseline data with data stored in its associated CAM array. The entire CAM array or its segments are searched in parallel to find matching comparison reference data. If a match exists, the CAM device indicates a match by claiming a match flag. Multiple matches can also be indicated by asserting a multiple match flag. The CAM device typically includes a sequential encoder that translates the matching position into a matching address or CAM index, and outputs this address to a status register. The matching address, the content of the matching position, and other status information (such as the skip bit, the blank bit 'full flag and the matching flag and multiple matching flags) can be output to an output bus by the CAM device. CAM devices can be deeply connected in series to form a larger cam device or system. For example, two lk X 64 CAM devices can be formed by deep concatenation — 2k X 64 CAM. Deep concatenation can be performed using the match flag input and output pins. The matching flag input pins of higher-order CAM devices (that is, CAM devices with lower physical addresses) can be connected to the matching flag input pins of lower-order CAM devices (that is, CAM devices with high physical addresses). In response to the ratio / command, each CAM device compares the comparison reference data with the data stored in its different CAM array at the same time. If the higher-rank CAM device matches, the result is notified to the comparison by the main matching flag output signal. Low order CAM device. However, higher order CAM device can output its matching address to a common output sink, and lower order CAM device will not be able to output data to the common & output.

45742 ^ _ Case No. 87118088 Year and month?日 倏 正 _ V. Description of Invention (2) Row. However, if the higher-order CAM device does not match, it will not claim its matching flag output, and the lower-order CA device can provide its unique address to the common output data bus (if it matches). If there are many CAM devices connected in series, and no other CAM device has a match in the series, the lowest order CAM device in the series will be the only one that can output its data to the common output bus. In other words, the lowest order CAM device will wait until the matching flag signal from the previous CAM device has pulsated through the deep concatenated chain. This results in an undesirably long response time of the deeply connected CAM system to a comparison signal. When deep cascaded CAM devices are flow-through modal operations, it may not be desirable to use only matching flag input and output pins. The CAM device flowing through the modal operation can output a matching address, data from the matching position of the CAM array, and other status information (such as matching flags, multiple matching flags, full flags, skip bits, blank Bit or device ID) in a single clock cycle. For example, a mismatched higher-order CAM device will not assert its matching flag during this single clock cycle. The lower-ranking CA with a match will not know whether it can output its matching address to the common output data bus at this clock cycle because the higher-order CAM device has a slow response time or a higher-order Whether the CAM device matches. One possible solution is to allow each CAM device connected in series to output its matching address to a common output data bus, and then allow each CAM device to properly disable when the matching flag result pulse passes through the connection. However, this solution has caused a variety of disadvantages, including: (1) causing the problem of bus competition status, and (2) because all CA devices may drive the common output data bus at the same time, so

O: \ 55 \ 55539.ptc Page 7: 57423 Case No. 87118088_ and year y? __ V. Description of the invention (3) Causes the system to use an undesirably large amount of power, and (3) The system may slow down because the capacitance of the common output data bus may increase. Therefore, there is a need for a deep tandem CAM device that can flow through modal operations. SUMMARY OF THE INVENTION A method and apparatus for concatenating a content addressable memory (CAM) device is disclosed. The method and device are particularly useful for cascading CA devices in depth through a modal operation. In the flow-through mode, a comparison command can be supplied to each CAM device connected in series, and the matching address, data stored in the matching position, or other status information can be subsequently changed from the highest due to the same cycle of the command supplied to the CAM device. The sequence matching CAM device outputs to a common output data bus. Each CAM device has a serial input and a serial output to perform a serial connection function. The cascade output of the higher-order CAM device can be connected to the cascade input of the next lower-order CAM device. The higher-order CAM device can output an asserted serial signal at a predetermined time after receiving an input signal (such as a clock signal). It is claimed that the serial connection signal indicates that the higher order CAM device has completed the comparison instruction. When the lower-order CAM device detects that the cascade signal has been asserted in its cascade input, the lower-order CAM device can sample the matching flag of the higher-order CAM device to determine whether the lower-order CAM device can output its data to the common Output data bus "Other objects, features and advantages of the present invention will be apparent from the accompanying drawings and detailed description below. Brief Description of the Drawings The features and advantages of the present invention will be illustrated by examples and are not intended to limit the scope of the present invention to the specific specific examples shown. In the drawings:

O: \ 55 \ 55539.ptc Page 8 '4 57i £ inm W Year> Month? Description of Correction Bow (4) FIG. 1 is a block diagram of two CAM devices connected in series during deep expansion according to a specific example of the present invention; FIG. 2 is a specific example of serial signals generated by the CAM device of FIG. 1 Time chart; Figure 3 is a block diagram of a specific example of the CAM device of Figure 1, which includes a flow-through circuit and an expansion circuit; Figure 4 is a specific example of a flow-through circuit of the CAM device of Figure 3; Figure 5 is a diagram 3 is a logic circuit of a specific example of an internal series signal generator. FIG. 6 is a time chart of the logic circuit diagram of FIG. 5; FIG. 7 is a circuit diagram of a specific example of the delay circuit of FIG. 6; FIG. 8 is a series connection of FIG. A logic circuit diagram of a specific example of output logic; FIG. 9 is a time chart of the logic circuit diagram of FIG. 8; FIG. 10 is a logic circuit diagram of a specific example of the ADS bus control logic of FIG. 3; and FIG. 11 is a diagram of FIG. A specific example of matching flag output logic. DETAILED DESCRIPTION A method and device for concatenating a content addressable memory (CAM) device are disclosed. In the following description, for convenience of explanation, a specific nomenclature is used for a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the specific details of implementing the present invention are not required. Other well-known circuits and devices are shown in block diagram form to avoid unnecessarily obscuring the present invention. The interconnections between circuit elements or blocks are shown as busbars or single signal lines. Each of the busbars may additionally be a single signal line, and each of the single signal buses may be a busbar. In addition, the signal or

O: \ 55 \ 55539.ptc page 9 ^ 574 23 case number 87118088 > year and month? One said Amendment_ Five. Description of the invention (5) The symbol "/" is added in front of the pin name to indicate the active low signal or pin. However, these signals or pins can also be replaced by active high signals or pins. The method and device of the present invention are particularly applicable when the cascaded CAM device is operated in a modal flow. In the mode, a comparison command is supplied to each CAM device at the same time, and then the matching address, data stored in the matching position, or other status information can be matched to the CAM device from the highest order in the same cycle that the instruction is supplied to the CAM device. Output to a common output data bus. Each CAM device can have a serial input and a serial turn out to perform the serial connection function. The cascade output of the higher-order CAM device can be connected to the cascade input of the lower-order CAM device. The higher-order CAM device can assert a serial signal at its predetermined output time after receiving an input signal (such as a clock signal). It is claimed that the tandem signal indicates that the higher order CAM device has completed the comparison instruction. When the lower-order CA MU device detects that the cascade signal has been asserted on its tandem input, the lower-order CAM device can sample the matching flag of the higher-order CAM device and determine whether the lower-order CA MU device can Output data to the output data bus. ~ Figure 1 is a block diagram of system 100. System 100 includes system devices 102 and 104 that are interconnected with a deep strike. The memory size of the system 100 is V ^^ and the individual sizes of the CAMs 102 and 104. For example, if the CAM 102 is a 4kx 64 CAM device and the CAM 104 is a lkx64 CAM device, then the system 100 can be operated as a 5k) < 64 CAM device. Any size CAM device can be used in the present invention. CAM devices with different widths can be connected in series. As an alternative specific example, other memory devices (such as SRAM, multi-port RAM 'DRAM, ROM, EEPROM, EPROM, etc.) other than the CAM device can also be used. Now the system l〇〇 can be

O: \ 55 \ 55539.ptc page 10 ^ 57423 α 0 __case number 87118088_ and year & month / day correction_ V. Description of the invention (6) Isolated CAM device can be formed by integrated circuit or integrated Substrate formation. Each CAM device receives the clock signal CLK 106 in parallel, obtained from the comparison reference data of the comparison bus CBUS 1 08, and instructions obtained from the instruction bus IBUS 1 10 (such as a write comparison instruction or other comparison instructions). As for specific alternatives, CBUS i 08 and I BUS 1 10 can be the same bus. Other input signals can also be supplied to each CAM 102 and 104 at the same time, including word enable signal, reset signal, chip enable signal, etc. CAM 1 02 and 1 04 also output data to a common related data and status information bus ADS BUS 112. The output data output from CAM 102 and 104 to ADS BUS 112 includes a matching address, data stored in the CAM device, or status information includes matching flags, multiple matching flags, full flags, skip bits, and blank bits. Yuan, device ID information and / or other information. The CAM devices 102 and 104 each include a series input pin / CSCDI, a series output pin / CSCDO, a matching flag input pin / MFI, and a matching flag output pin / MFO «CAM device 102 via Coupling its / CS CD I pin to the first power rail (eg, ground or about 0 volts) and coupling its / MF I pin to the second power rail VDD are labeled as higher order CAM devices. In a specific example, VDD may be about 1.5 volts to about 7.0 volts. Other voltages can be used. The / CSCDO pin of CAM 102 can be coupled to the / CSCDI pin of CAM 104 through line 114, and the / MFO pin of CAM 102 can be coupled to the / MFI pin of CAM 104 through line 116. If more CAM devices are included in the deep concatenation of the system 100, each CAM device may similarly have its / CSCDI pin coupled to the / CSC DO pin of the next highest (or next lowest) CAM device, and / The MFI pin is coupled to the / MF0 pin of the next highest (or next lowest) CAM device

O: \ 55 \ 55539.ptc Page 11 457423 Case No. 87118088 and the month of the year f Amendment V. Description of the invention (7) Feet. The operation of the system 100 can be explained by means of the example time chart of FIG. 2. At time t0, CLK 106 transitions to a high state to enable CAMs 102 and 104 to load the instructions derived from IBUS 110 and the comparative benchmark data derived from CBUS 108. The instruction may be an instruction to instruct the CAMs 102 and 104 to compare and compare the reference data with the data of the CAM array stored in each of the CAM devices. At time t1, CAM 1 02 and 1 04 each deasserted (for example, driven to a logic high state) their individual / [5000 signal at its / 03000 output pin. When (^ Discuss 102 deasserts its / CSC DO output pin and drives a high signal on line 114, CAM 104 can be disabled by asserting (eg, driving to a logic low state) its / CSCD0 output pin, and by providing information to ADS MS 1 12 is disabled. CAM 102 (and CAM 104) can continue to assert their individual / CSCD0 output pin schedules for a predetermined time sufficient to enable the instructions to be executed by the CAM device. For example, CAM 1 02 can assert claims on line 114 calendar A period of time is sufficient for the CAM 102 to compare and compare the baseline data with the data stored in its CAM array and for the CAM 102 to generate a matching flag indicating the result of the comparison instruction (for example, at time 12). After these intermediate operations are completed, the CAM 102 may Online assertion / CSCD0 signal. CAM 102 can also deassert that the signal on line 114 is sufficient for CAM 102 to generate a matching address, read data from the matching position of CAM array of CAM 102, and / or generate the job Status information. At time t3, CAM 104 receives the asserted / CSCD0 line 114 as the / CSCDI input signal, and can use the assertion as an indicator to indicate that the matching flag signal of line 116 is in a valid state. In other words , The output signal series / CSCD0 CAM 1 02 indicating when executing a comparison instruction and complete matching of the line

IH O: \ 55 \ 55539.ptc Page 12 457423 _ Case No. 87118088 V. Description of the invention (8) Θ year $ month? The flag signal is valid. If the match flag signal of line 116 is "asserted (eg, logic low)" at time, then the higher order c A M 1 0 2 has a match, and c A M 104 does not output data to ADS bus 112. If line The match flag signal of 116 is deasserted (for example, a logic high state) at time t3, then there is no match at station 102, and if CAM 104 determines at time t5 that the comparison reference data matches the data stored in its CAM array, then CAM 104 outputs data to the ADS bus 1 1 2. CAM 104 can receive the asserted / CSCDO signal at time t3 and output / CSCDO at time t4 after line 114. CAM 104 can also assert and release the assertion / MFO at line 120 It has nothing to do with whether the CAM 102 matches. The / CSCDO signal of line 118 and the / MFO signal of line 102 can produce the effect that any additional CAM device can be further connected in series with CAM 102 and 104. Figure 3 shows CAM 3 0 0 Block diagram. CAM 3 0 0 is a specific example of CAM 102 or CAM 1 04 in FIG. 1. CAM 3 0 0 includes flowing through CAM circuit 3 2 and expansion circuit 3 0 4. Flowing through CAM circuit 3 2 includes CAM 300 operates in the mode required for flowing through the mode. As for other specific examples, the circuit 302 may not be The CAM circuit operates in modal flow. The expansion circuit 304 includes an internal series signal generator 306, a series output logic 308, a matching flag output logic 313, and an ADS BUS control logic 3 10. The CAM 300 can be connected in series. The system operation is as follows. In response to the write and compare or any other comparison instruction in the IBUS 110, the flow through the CAM circuit 302 can load comparison reference data for comparison with the first set of CAM cells of its CAM array. Then flow through the CAM circuit 30 2 Send a signal on line 31 2 to indicate that the comparison instruction is operated by CAM 300. Then internally connect the signal generator 306 to dismiss the claim.

O: \ 55 \ 55539.ptc Page 13 457423 __Case number 87118088 and year and month? Day correction _ V. Description of the invention (9) (or claim) a signal on line 31 6 lasts for a predetermined time and it is enough to flow through the CAM circuit 3 02 to determine the comparison reference data and the CAM array flowing through the CAM circuit 3 02 Whether the data matches. If it is also possible to generate an internal serial signal for each instruction on line 3 16 (and / or / CSCDO on line 32 2) instead of only generating a comparison instruction, a predetermined time when the signal on line 3 16 is de-asserted, serially output Logic 308 may be deasserted at line 322 / CSCDO. When / CSCDO is deasserted on line 322, the next lowest order CAM device on the cascade can be blocked from providing data to ADS® bus 112 and / or not asserting its / CSCDO output signal. As for a specific example, the internal series-connected signal generator 306 generates a one-click power generation circuit, which can respond to the rising edge (or falling edge) of the CLK 106 to cancel the assertion signal for a predetermined time on line 3 1 6. Any click-to-send circuit that can generate a signal on line 3 1 6 for an appropriate amount of time can be used. The flow through the CAM circuit 302 can perform comparison of the comparison reference data with the first set of CAM cells of the CAM array. The comparison result is reflected by the status of the internal matching flag signal / MF I NT of line 3 1 4. If the data stored in the CAM array does not match the comparison reference data ', the assertion / MFINT is lifted at line 314 (for example, to a logic high state). If there is a match, then the matching address of / MFINT (for example, to a logic low state) 'and the position of the C AM array on line 314 can be supplied to the bus 3 2 6. The match flag output logic 313 may then generate an output match flag signal / MFO on line 324 in response to / MFINT on line 314 and / MFI on line 320. In a specific example, if / MFINT is asserted, / MFO can be asserted. The / MFO status of line 324 can be resolved before the predetermined time for the signal of line 316 to be disclaimed. In other words, CAM 300 can be resolved or valid at / MFO.

O: \ 55 \ 55539, ptc Page 14 457 4 2 3. ^ Α α ^ __ cable number 87118088 θ year Υ month / said correction _ V. Description of the invention (10) Used to compare instructions at line 322 claim / CSCDO. Thus, / CSCDO at line 322 can indicate when CAM 300 has completed comparing the baseline data with the data stored in its CAM array, and when the / MFO result at line 324 is valid. If a match is determined, the data flowing through the CAM circuit 3 2 can sense the data from the CAM array corresponding to the matching address, and can output the sensed data to the ADS BUS control logic 310 through the bus 3 2 6. If CAM 3 0 0 contains the highest order matching address, the ADS BUS control logic 3 0 can output the matching address, the sensed data and other status information to the ADS BUS 112 eADS BUS control logic 310 can be monitored via the line 318 / CSCDI status, / MFI of line 3 2 0 and / or MFI NT of line 314, determine whether CAM 3 0 0 has the highest matching address. If asserted at line 3 of 20 / MFI, higher order CAM devices may have matching, and ADS BUS control logic 3 10 may not output data to ADS BUS 112. However, if / CSCDI is asserted on line 318, / MFINT is asserted on line 314 and disclaimer / MFI is asserted on line 3 2 0, then ADS BUS control logic 310 determines that CAM 300 has the highest matching address and can output data to ADS BUS 1 12 .

A specific example of the flow through the CAM circuit 302 is disclosed in U.S. Patent Application No. 08 / 967,314. The synchronous content addressable memory whose name operates in a single cycle. The application date is October 30, 1997, and is described here. for reference. Figure 4 shows a specific example of the flow through the CAM circuit 400 disclosed in the application No. 08/967, 314. The flow through the CAM circuit 40 0 is a specific example of the flow through the CAM circuit 300 in FIG. 3. Flow through CAM circuit 40 0 includes CAM array 402, comparison register 404, sense amplifier 406 'clock generator 40 8, instruction decoder 410, matching latch 4 1 2' priority encoder 4 1 4, bit Address latch 4 1 6, address selector 418 and address decoder 420 »Flow through CAM circuit 4 00 also includes a CLK

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In 5 7 2 3 case number 87118088 V. Description of the invention (11) 106 The clock buffer and used to provide one or more clock signals with the same or different phases or rates to the clock generator 408 and / or the instruction solution Marker 410: 'The flow through the CAM circuit 400 can execute a comparison instruction in one (or more) cycles as follows. At the beginning of the clock cycle of CLK 106, the instruction decoder 4 丨 0 decodes-enters and compares (or compares) the instructions at I BUS 110. The instruction decoder 4 丨 〇 解 妈 ’instruction and sends a signal to the bus generator 4 4 4 to the clock generator 4 08 to indicate the nature of the input. The instruction decoder 410 also outputs a signal on line 312, which can be connected to the internal signal generator 306 in series, as shown in FIG. In response to the signal of line 444, the clock generator 408 sends a signal on line 426 to load the comparison reference data of CBUS 108 into the comparison reference register 404. Then the comparison benchmark data can be compared with the data stored in the CAM array 4 02 to decide whether to match. Then the state of the matching line in the C A M array 104 can be responded to the signal of the line 4 30 by the matching latch 4 1 2 latch. The priority encoder 1 1 6 can then respond to the signal latch of line 43 2 to match the output of latch 4 1 2. The priority encoder 4 1 4 can determine the highest matching address by comparison. Then the matching address can be output by the priority encoder 4 1 4 to the bus 4 3 8 and the address latch 416 can be responded to the signal latch of line 434. Lock (to bus 442) »Bus 4 3 8 can be part of bus 3 2 6 in Figure 3. As the industry knows, 'If there is at least one match between the reference data and the data stored in the CA Array 402, the priority encoder 1 1 6 can also generate an internal four-match flag signal / MFINT. At line 314. The matching address on the bus 442 can then be supplied to the address decoder 4 2 0 by the address selector 418 in response to the signal of line 4 2 2. The address selector 4 1 8 can couple the address of the address bus 4 3 6 or the matching address of the bus 4 4 2 to the address decoder 4 2 0. In the alternative, the address

O: \ 55 \ 55539.ptc Page 16 457423 ____Case No. 87118088 Article 1_ 5. Description of the invention (12) The selector 4 1 8 can be deleted and the bus 44 2 is directly connected to the address decoder 420. The address decoder 420 can decode the matching address and output the decoded matching address in response to the signal on line 424. The decoded matching address can select a row of C AM cells in the CAM array 4 02 corresponding to the matching address. One or more CAM cells at the high-order matching address can then be sensed by the sense amplifier 406 and coupled to the bus 440. The bus bar 4 4 0 may be a part of the bus bar 3 2 6 in FIG. 3. Before the end of the clock cycle of CLK 106 *, the matching address on bus 4 38, the internal matching flag on line 3 1 4 and the data sensed by CAM array 4 02 can be supplied to the expansion circuit. FIG. 5 is a logic circuit diagram of the internal series-connected signal generator 500. Internal serial f§ number generator 500 is a specific example of the internal serial signal generator 306 of FIG. 3 ', which generates CSCINT on line 316 for a predetermined time sufficient for CAM 300 to generate / MFINT on line 314. Other specific examples of the internal series signal generator 306 may be used. The generator 500 is a single firing circuit. It has a first delay path including inverting delay elements 502, 504, and 506 coupled in series between the first input of CLK 106 and NAND gate 514. Any odd inverting delay element can be used. As an alternative, any combination of inverting and / or non-inverting delay elements may be used. In addition, each delay element may have an equal amount of delay or an unequal amount of delay β. As a specific example, the delay elements 502 and 504 have approximately the same amount of delay, and the delay elements 504 have an unequal amount of delay. The total delay through the delay elements 502, 504, and 506 is enough to make the NAND gate 514 lift the claim that the CSCINT is on line 316 for a sufficient time, so it flows through the circuit 3 2 2 / MFINT on line 314 »Each delay element includes Resistor 'RC network' inverter or other delay circuit.

O: \ 55 \ 55539.ptc Page 17 457423 Case No. 87118088 Amendment V. Description of the Invention (13) The generator 500 also includes a second delay path, which includes an inversion delay element 508, an inverter 510, and a NAND gate 512. Inverting delay element 508 has its input coupled to CLK 106 and its output coupled to the first input of NAND gate 512. The input of inverter 510 is coupled to CLK 106 and its output is coupled to the second output of NAND gate 512. The output of NAND gate 512 can be coupled to the second input of NAND gate 514. The output of NAND gate 514 can provide internal series connection. Signal CSCINT is on line 316. The delay element 508 includes the same delay elements as the delay elements 502, 504, or 506. The operation of the generator 500 can be described by means of the example timing diagram of FIG. 6. At time t0, CLK 106 transitions to the high state, causing the signal at line 5 16 to transition to the low state at time t1, and the signal at line 5 2 0 transitions to the high state at time t2. The low state of line 5 2 0 causes the CSC I NT of line 3 16 to be deasserted and transition to the low state at time t3. After being delayed by the delay element 508, the signal of line 5118 also transitions to the low state at time t4. After delaying through the delay elements 502, 504, and 506, the signal of line 5 2 2 transitions to a low state at time t7, and causes NAND gate 514 to assert CSCINT to a high state at time t8. In this way, CSCINT can be removed from time t3 to time t8 to claim to have a predetermined time. It should be understood that the function of the second delay path is that the rising edge of CLK 106 propagates through the first delay path of delay elements 502, 504, and 506. The falling edge of CLK 106 is not allowed to assert CSCINT on line 3 6 at time t5. As for an alternative specific example, the signal of line 31 2 of FIG. 3 can be used to gate CLK 106 to delay elements 502 and 508 and inverter 510. For example, CLK 106 can logic eight 1 ^ 1 ^ < 5 lines 312 signals. In yet another specific example, lines 316 to 03 (; 0) may be connected to CSCINT to the serial output logic 308 in FIG.

O: \ 55 \ 55539.ptc Page 18 457423 Case No. 8711808S V. Description of the invention (14) a__ Signal gate control. For example, CSCINT can be logically ANDed on the signal on line 312. FIG. 7 is a circuit diagram of the delay element 700. The delay element 700 is a specific example of the delay circuit 502, 504, 506, or 508 of FIG. The delay element 700 includes a CMOS inverter formed of a PMOS transistor 706 and an NMOS transistor 708. Any other inverter from other process technologies can be used. The inverter inverts the signal on line 702. After delay is caused by resistor 710 and capacitors 712 and 714, the inverted signal can be combined to line 704. The resistor 710 has any size. For a specific example, the resistor 710 is about 100 ohms to about 1000 ohms. The resistor 710 is optional. One or two or zero capacitors 712 and 714 may be included in the delay element 700. The capacitor 712 may be formed of a PMOS transistor, and the capacitor 714 may be formed of a NMOS transistor. As a specific example, the capacitor 712 may have an aspect ratio of about 3.2 microns to about 7.8 microns and the capacitor 714 has an aspect ratio of about 7.8 microns to about 3.2 microns.圊 8 is a logic circuit diagram of the output logic 800 in series. The serial output logic 800 is a specific example of the serial output logic 308 of FIG. 3. Other specific examples of the serial output logic 308 can be used. The serial output logic 800 includes NAND gates 804 and 810, inverters 802, 806, and 812, PM0S transistor 808 and NM0S transistor 814 »The input of inverter 802 is coupled to / CSCDI of line 318 and its output coupling First input to NAND gates 804 and 810. The second input of each of NAND gates 804 and 810 is coupled to CSCINT of line 316. The input of inverter 806 is coupled to the output of NAND gate 804, and its output is coupled to the gate of PMOS transistor 808. The input of inverter 812 is coupled to the output of NAND gate 810, and its output is coupled to the gate of NMOS transistor 814. PM0S transistor 808 has its source coupled to the power rail

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Page 19 457423 Case No. 87118088 Amendment V. Description of the invention C15) VDD and its drain coupled to line 322 / CSCDO «NMOS transistor 814 further has its drain coupled to line 322 and its source coupled to ground or about 0 volt rail. The operation of the serial output logic 8 0 0 can be illustrated with reference to FIG. 3 and the example time chart of FIG. 9. It is assumed that the serial output logic is included in a lower-order CAM device, such as CAM 104 in FIG. 1. When the comparison command is loaded into the CAM device in response to the rising edge of CLK 1 06 at time t0, then the internal signal generator 3 0 6 generates a single shot signal from time 11 to 15 on line 3 1 6. This can cause / CSCD0 of line 322 to transition to a high state at time t2, because PM0S transistor 808 may be on and NMOS transistor 814 may be off. / CSCDI of line 318 can transition to a high state at time 13. A single firing signal on line 3 1 6 may transition to the high state after the internal matching flag signal on line 3 1 4 has transitioned to time t 4. When line 3 1 of 8 / CSCDI asserts to a low state, it indicates that the higher order C AM device has completed its comparison operation 'PM0S transistor 8 0 8 can be turned off, and NM0S transistor 8 1 4 is turned on while pulling line 3 2 2 / CS CD0 to low. The low state of line 3 2 2 indicates that CAM 300 has completed its comparison operation, and the matching flag output signal / MF0 of line 324 is valid. FIG. 10 is a logic circuit diagram of the ADS BUS control logic 1 0 0, and the ADS BUS control logic 1 0 0 is a specific example of the ADS bus control logic 3 10 in FIG. 3. Other specific examples of the ADS bus control logic 3 10 can also be used. The ADS BUS control logic 1 0 0 includes a matching flag valid circuit 1002, an output enable control circuit 1004, and an output buffer 1024. The matching flag valid circuit 1002 includes a NAND gate 1012 having a logic input complemented by a first input coupled to / CSCDI via an inverter ι〇β and a second input via a series connection

O: \ 55 \ 55539.ptc page 20 457423 _ case number 87118088 and year & month 7 amendment _ V. Description of the invention (16) Phasers 1008 and 1010 are coupled to / MFI «then match the flag valid circuit 1002 through The inverter 1014 supplies the NAND gate 101 2 to a logic complement line 1016. As for the specific example, the NAND gate 1012 can be replaced by an AND gate, and the inverters 10 08, 1010, and 1014 can be removed. Only when / CSCDI asserts that the low state is at line 31 8 and the matching flag is valid. The control circuit 1 002 outputs the / MF I state at line 1 01 6 »The output enable control circuit 1004 includes a NAN D gate 1020, which has its The first input is coupled to line 1016 and its second input is coupled to the logical complement of / MFINT through an inverter 1018. The inverter 1022 can couple the logical complement of the N AND gate 1020 to the output buffer 1024. When / MFINT is deasserted to the high state on line 314, indicating that there is no match in the comparison operation, the output enable control circuit 1 0 04 can disable the output buffer 1 024, so no data is supplied to the ADS BUS 112 from the bus 3 2 6. The output enable control circuit 1004 can enable the output buffer 1024 and output data from the bus 326 to the A DS BUS 112 in the following cases: (1) Line 314 / MFINT is asserted to match the low state indication; and (2 ) Line 320 / MFI is high, indicating that no higher order CAM has a match. The output buffer 1024 can be any kind of output buffer, including a tri-state output buffer, which can buffer signals from the bus 326 to the ADS BUS 112. FIG. 11 is a logic circuit diagram of the matching flag output logic 1100. The matching flag output logic 1100 is a specific example of the matching flag output logic 313 of FIG. 3. The matching flag logic 1 100 includes a NAND gate 1102, inverters 1104, 1106, 1108, and 1110, a PMOS transistor 1112, and an NMOS transistor 1114. As an alternative, inverters 1104, 1106, 1108, and 1110 can be deleted. The first input of NAND gate 1102 can be coupled to / MFI of line 320 and the second input of NAND gate 1 / MFINT «The output of NAND gate 1102 is connected to the inverter in series

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B Modification 1 1 04 and 1 1 06 are coupled to the gate of PMOS transistor 111 2. The output of the NAND gate 1 102 is also coupled to the gate of the NMOS transistor 1 1 1 4 through the series connected inverters 1108 and 1110. The PMOS transistor 1 11 2 further has / MFO with source coupled to VDD and its drain coupled to line 324. NMOS transistor 1114 further couples its drain to line 3 24 and its source coupled to ground or approximately 0 volts. . If neither / M F I nor / M F I N T asserts a low state, then / M F 0 is only deasserted to a high state. This specific example can be used in a deep tandem system, which generates a composite matching flag from the cascaded lowest order CAM device. Other specific examples of the matching flag output logic 313 of FIG. 3 can also be used. Referring to FIG. 1, an alternative specific example of generating / CSCDO on line 114 (or line 118) may generate an internal matching flag signal from an additional column of memory banks of the CAM array of CAM 102 (or CAM 104). The extra columns can be properly masked to generate matching conditions frequently, and then output / CSCDO of the supply line 114. In this way, the CAM 104 can often know the / CSCDI transition state and know when to sample the / MFO of the line 116. In the foregoing description, the present invention has been described with specific examples. However, it is obvious that various modifications and changes can be made without departing from the broader spirit and scope of the present invention. As such, the description and drawings are to be regarded as illustrative only, and not restrictive.

O: \ 55 \ 55539.ptc Page 22 457423 ___ Case No. 87118088 V. Description of the invention (18) 102, 104 CAM device mode, component symbol description 100 System 106 Clock signal CLK 110 Command bus IBUS 112 Data and Status information 114, 116, 118, 120 300 CAM 3 0 4 Expansion circuit 3 0 8 Serial output logic 312 Line 314, 316, 318 '320' 3 2 6 Bus 4 0 2 CAM array 4 0 6 Sense amplifier 410 Instruction decoder 414 Priority encoder 418 Address selector 422 '424' 426 '428, 436' 438 '440' 442, 5 0 0 Internal serial signal generation 502 '504' 506 '508 5 10 Inverter 516 '' 518, 520, 522 7 0 0 Delay element 7 0 6 PMOS transistor

108 Compare® Bus CDS Bus ADS Line 3 0 2 Flow through CAM circuit

3 0 6 Internal serial connection A 310 ADS BUS control; logic generation 313 matching flag wheel output logic 1 3 2 2 '324 line squat material 40 0 flow through CAM power @ 4 0 4 compare temporary storage ϋ 40 8 clock Generator 412 Matching latch 41 6-address latch 420 Address decoder 430 > 432 '434 line 444 bus generator inverting delay element 512, 514 NAND ^ line 702, 704 line 7 08 NMOS transistor

O: \ 55 \ 55539.ptc Page 23 457423 α _ Case No. 87118088 & Month / Β Amendment _ V. Description of the invention (19) 710 Resistor 712, 714 Capacitor 8 0 0 Serial output logic 802, 806 , 812 inverter 804, 810 NAND gate 808 PMOS transistor 814 NMOS transistor 1 0 0 0 ADS BUS control logic 1 0 0 2 Match flag effective circuit 1 0 0 4 Output enable control circuit 1006, 1008, 1010, 1014 Inverter 1012 NAND gate 1016 line 1018 Inverter 1020 NAND gate 1 0 2 2 Inverter 10 24 Output buffer 110 0 Match flag output logic 1102 NAND gate 1104, 1106, 1108, 1110 Inverter 1112 PMOS Transistor 1114 NMOS Transistor

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Claims (1)

457423 Case No. 87Π8088, Amendment τ, Patent Application Scope 1. A content addressable memory (CAM) device, including: a CAM circuit for storing data; a data input terminal for providing comparison data to communicate with the C The information of the AM circuit is compared; a series circuit is coupled to the CAM circuit; a matching flag output is coupled to the series circuit, and the matching flag output is used to provide a matching flag output signal to indicate the comparison Whether the word data matches the data of the CAM circuit; and-a cascade output, coupled to the cascade circuit, the cascade output is used to provide a cascade output signal to indicate when the matching flag output signal is valid. 2. If the CAM device in the first patent application scope includes a series input coupled to the series circuit, the series input is used to receive from another CAM device—the input signal is connected to indicate when the other CAM The device has completed a comparison operation. 3. If the CAM device of the second patent application range further includes a matching flag input coupled to the cascade circuit, the 3H flag input receives a matching flag input signal from the other CAM device, wherein The tandem input signal from the other CAM device further indicates when the matching flag input signal from the other CAM device is valid. 4. For example, the CAM device in the first patent application scope further includes a clock input coupled to the series circuit, and the clock input is used to receive a clock signal. 5. As for the CAM device in the fourth scope of the patent application, wherein the matching flag output signal and the series output signal are in a single clock cycle of the clock signal I O: \ 55 \ 55539.ptc Page 26 4 5 7 4 2 3 Case No. 87118088 & Month? Amendment_ VI. Scope of patent application The period is generated by the series circuit. 6. If the CAM device of item 3 of the patent application, the CAM circuit outputs an internal matching flag signal indicating whether the comparison data matches the data of the CAM circuit, and the CAM device further includes a matching flag output Logic coupled to the match flag input and coupled to receive the internal match flag signal, wherein the match flag output logic is structured to respond to the match flag input signal and the internal match flag signal to generate the match flag Standard output signal. 7. If the CAM device of item 6 of the patent application scope further includes a bus control logic coupled to the CAM circuit, the cascade circuit, and the matching flag input, the bus control logic is structured to output from the CAM device A bit address corresponding to the data of the CA MM circuit matching the comparison word. The bus control logic is structured to respond to the matching flag input signal, the cascade input signal, and the internal matching flag signal and output. The address. 8. If the CA M device of the first patent application scope further includes an instruction decoder, it is lightly connected to the CAM circuit. 9. The CAM device according to item 8 of the patent application scope further includes a timing generator coupled to the CAM circuit and the instruction decoder. 10. The CAM device according to item 2 of the patent application scope, wherein the series circuit includes: a series signal generator configured to output an internal series signal in response to an input signal; and a series output logic coupled to The serial signal generator and the serial input, and the serial output logic is structured to respond to the internal serial signal and the serial O: \ 55 \ 55539.ptc Page 27 4574 2 Case No. 87118088 Amendment VI. Patent Application Scope Connect the input signal and generate the signal output signal. 11. For example, the CAM device under the scope of patent application No. 10, wherein the serial signal generator includes a single-trigger circuit β 12. A content addressable memory (CAM) device, including: a CAM circuit for storing Data; The data input terminal is used to provide comparison word data for comparison with the data of the CAM circuit;-a cascade circuit, coupled to the CAM circuit; a matching flag input, coupled to the cascade circuit, the matching The flag input receives a matching flag input signal from another CAM device; and a cascade input coupled to the cascade circuit, the cascade input receives a cascade input signal from the other CAM device to indicate when it comes from The matching flag input signal of the another CAM device is valid. 13. For example, the CAM device of claim 12 in which the series circuit is further configured to generate a matching flag output signal to indicate whether the comparison word data matches the data of the CAM circuit. 14. For a CAM device according to item 13 of the patent application scope, the series circuit is further configured to generate a series output signal, which indicates when the matching flag output signal is valid. 15. If the CAM device of item 13 of the scope of patent application, a clock input is coupled to the cascade circuit and the CAM circuit, the clock input is used to receive a clock signal, which t the serial output signal and the match The flag output is generated by the series circuit in a single cycle of the clock signal. 16. The CAM device according to item 12 of the patent application, wherein the series connection circuit O: \ 55 \ 55539.ptc Page 28, 45742. n Q _ Case No. 87118088_ Year of Moon Expansion / B__ VI. The scope of patent application includes: a series of signal generators, which are structured to respond to an input signal and output a Internal serial signal; and serial output logic coupled to the serial signal generator, the _connect output logic is structured in response to the internal serial signal and the serial input signal to the CAM device to generate the serial output signal. 1 7. If the CAM device in item 12 of the patent application scope further includes a bus control logic, coupled to the CAM circuit, the serial input, and the matching flag input, the bus control logic is structured from the The CAM device outputs a bit address corresponding to the data of the CA MM circuit that matches the comparison word data. The bus control logic is structured to respond to the matching flag input signal and the serial input signal and output the address. . 18. The CAM device according to item 16 of the patent application scope, wherein the serial signal generator includes a one-shot circuit. 1 9. A system comprising: a first content addressable memory (CAM) device having a serial output and a matching flag output, the matching flag output providing a matching flag output signal to indicate comparison word data Whether to match the information of the first CA device, the cascade output provides a cascade output signal indicating when the matching flag output signal is valid; and-the second content addressable memory (CAM) device, and the first A CAM device is coupled in series. The second CAM device has a series input, a matching flag input, and a series output. The series input of the second CAM device is coupled to the O: \ 55 \ 55539.ptc page 29 ί 57423 case number 87118088 and year? Amendment 6. Scope of patent application The tandem output of the first CAM device, the matching flag input of the second CAM device is coupled to the matching flag output of the first CAM device. 20. The system according to item 19 of the patent application scope, wherein the system is integrated into an integrated circuit. 2 1. The system according to item 19 of the scope of patent application, wherein the second CAM device is configured to receive a serial output signal from the first CAM device and ensure a logical state after receiving the serial input from the serial input. That is, its serial output ensures that a serial output signal is in this logic state for a predetermined period of time. 2 2. The system according to item 21 of the patent application scope, wherein each of the first and second CAM devices has a data output coupled to a common data output bus. 23. The system of claim 22, wherein each CAM device has a data input terminal coupled to a common data input bus, and each CAM device is structured to be determined at the same time by the data input bus. Whether the comparison data provided matches the data of each C AM device. 24. The system of claim 23, wherein the second CAM device is structured to output the address of its matching data to the common data output bus when the first CAM device is not matched. 2 5. The system according to item 24 of the scope of patent application, wherein the second CAM device is within the clock cycle of the same clock signal output by the second CAM device to the shared data output bus It is structured to determine whether the comparison data provided on the data input bus matches the data of the CAM device. 26. —A kind of serially connected first and second content addressable memory (CAM) device O: \ 55 \ 55539, ptc page 30 457423 _ case number 87118088 P year of the public bus 1__ VI. Patent application method, including: Instruct the first and second CAM device to perform a comparison operation, the comparison word Compare the data with the first data stored in the first CAM device and compare with the second data stored in the second CAM device; provide a matching flag signal from the first CAM device to the second CAM Device, the matching flag signal indicates whether the comparison word data matches the first data; and a serial output signal is provided from the first CAM device to the second CAM device, the serial output signal indicates when the matching flag is The signal is valid for sampling by the second CAM device. 27. The method of claim 26, wherein the first and second CAM devices have output terminals coupled to a common output bus, and the method further includes: when the comparison word data matches the first data , Only the first CAM device outputs data to the common output bus. 28. The method according to item 27 of the scope of patent application, wherein the method is performed by the CAM devices in a clock cycle. 29. The method of claim 27, further comprising: when the comparison data matches the stored second data and does not match the first data, only the second CAM device outputs data to the shared output Bus. 30. The method of claim 29, wherein the method is executed in a clock cycle. 31. A method of operating a content addressable memory (CAM) device, including: instructing the CA device to perform a comparison operation to compare the comparison data with the O: \ 55 \ 55539.ptc Page 31 457423 Ω 0 ί} _Case No. 87118088 & Year / Month / Amendment_ VI. Compare the information stored in the patent application CAM device; generate a A matching flag signal indicating whether the comparison word data matches data stored in the CAM device; and generating an output signal from the CAM device indicating when the matching flag signal is valid. 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