TW455814B - Software directed target address cache and target address register - Google Patents

Abstract

A branch prediction system is provided that includes a first, low-latency storage structure, a second, higher-latency storage structure, and a branch prediction manager (BPM) for updating the first and second storage structures according to software provided hint information. For one embodiment, the BPM identifies branch hint information from branch related instructions and writes the identified branch hint information according to the state of an importance bit in the instruction. When the importance bit is in a first state, branch prediction information is stored in the first storage structure. When the hint information is in a second state, the branch prediction information is stored in a second structure.

Description

4 5 5 8 1 4 The controller uses the entire line. Instruction pipeline level Independent operation means the pipeline processing. In order to complete, it is enough to keep the pipe to execute a point, jump to a new one, send it to the front of the pipeline, take the execution path, and use the funds in the instruction level of the wrong path.

Page 5 Background of the Invention The field of branch prediction ' is particularly related to systems and methods for accessing branch information. Very high speed consists of several waterfall-like one-work sequence, "tubular stage") and the tubular stage. As each round of the tubular stage has a number of rounds of execution functions, the correct execution path of the processor conforms to the branch. The conditions that will arise from the execution of the management order are dependent on the possibility that the sub-pipeline may be sub-instruction. Then the order must be removed from the pipeline. The idle 4 will be filled out until the description of the invention is filled in. (1) Field of the Invention The present invention is a prediction of the background of the instruction. The advanced technology of this type of processor constitutes a tube that corresponds to several instructions and thus increases processing resources. Branching instructions with more than one instruction is challenging. When the control flow of the command line is passed, the tube line bubble is filled to ensure that the execution is effective before the decision is correct. The pipeline technology is organized by the machine to process the divided hardware (can be transmitted by different orders) The processor uses this instruction to provide lines to fill the code sequence from the branch instruction and its code. Usually branched. If it refers to 'then when the processor executes the path', these sources maintain intermediation for useful Input execution instructions. The hardware level and each task is executed. From time processing, including multiple clock cycles may have to start from the correct line of resources. The main time of the instruction, the processor's new code sequence backend, and branches Execution, depending on the branch conditions to obtain the positive outflow, leaving the state is called the tube from the JL confirms <^ 5 58 1 4 V. Description of the invention (2) &quot; &quot; Execution path instructions until now. Modern processors in The branch prediction module is integrated into the front end of the pipeline to reduce the number of pipeline bubbles. When a branch instruction is input to the front end of the pipeline, the branch prediction module predicts that: When executed, will branch instructions be used? If branch prediction is used, the branch prediction module provides a branch target address to the instruction acquisition module. The acquisition module, which is also located in the front of the pipeline, starts to obtain instructions from the target address. The traditional branch prediction module uses branch target buffers (BTBs) to store prediction tributes, such as: whether a branch will be used, and similar target addresses when branches are used. Check out an instruction in the BTB, Determining whether to use branching and providing a target address to a used predictive acquisition module delays the redirection of the processor to the target address. This delay allows the input of instructions from the wrong execution path to be routed to the pipeline. Since these instructions do not join the predicted execution path forward, when they flow out, a "bubble" will be established in the pipeline. The greater the number of clock cycles required to redirect the pipeline, the greater the number of clock cycles established in the pipeline. The larger the number of bubbles. In addition, the more sophisticated and complete the branch prediction algorithm will take longer to complete, and will be re-guided Larger delays are generated. Currently available branch prediction techniques usually require two or more clock cycles to redirect the processor pipeline to reduce but not eliminate pipeline bubbles. When these bubbles appear like this When the selected branch instruction that controls the tight loop is degraded, there may be a considerable degree of performance degradation. For example, if a cycle of one bubble is introduced in a loop of a four-clock cycle, the execution of the loop may be degraded by 2 0%.

Page 6 4 5 5 8 1 4

V. Description of the invention (3) Summary of the invention The present invention is a hierarchical branch prediction system, which provides software-oriented branch prediction information to the selected branch prediction structure. According to the present invention, a branch prediction system includes first and second misstored structures for storing branch prediction information of the first and second types of branch instructions, respectively. A branch prediction manager (BPM) provides branch prediction information of a branch to the first or second health structure according to the important reminder related to the branch. In a specific embodiment of the present invention, the first storage structure is a register file * that can be accessed in a single clock cycle, and the second storage structure is a fast memory that can be accessed in two clock cycles . 'Brief Description of the Drawings The present invention can be understood by referring to the following formulas, in which similar elements are indicated by similar numbers. These drawings are provided to illustrate selected embodiments of the invention 'and are not intended to limit the scope of the invention. FIG. I is a block diagram of a front-end stage of a processor pipeline, which includes a traditional branch prediction module. FIG. 2 is a block diagram of a processor pipeline, which includes a processor pipeline according to the present invention. A branch prediction system. FIG. 3 is a block diagram of a specific embodiment of a branch predictive administrator (BPM). The branch prediction manager (BPM) is used to update the branch storage structure of the branch prediction system in FIG. 1. . FIG. 4 is a block diagram of a write pipeline for updating the target address register (τ a R) and the target address flash memory (TA c) of FIG. 2.

Page 7 4 5 581 4 V. Description of the invention (4) Figure 5A-5C is a branch and branch-related instruction. The branch-related instruction is suitable for the branch prediction system using the block diagram of the ', f package example. It is used to provide important reminder information to Figure 2. Figure 6 is a method of first-class cabinet update branch forecast information. ~ The method is used in accordance with the present invention, and Fig. 7 is a method of a method of _ from the branch to predict the structure of the-order to mention \ Fang: used to according to the present invention, 丨 stratum for branch prediction information. Detailed discussion of the invention The following discussion states a variety of macros to provide a thorough understanding of the present invention-a thorough person will understand: the present invention; people who understand the advantages of this disclosure will be able to make a decision ..., need some special疋 Detailed implementation. In addition, each component, program, and circuit are not described in detail so that the set t focuses on the characteristics of the present invention. Obviously, the traditional processor pipeline 100 has a front-end tubular stage. In the example disclosed in Yuan 4 shai, the 'stage 1 102' includes resources for indicating one: for: the private order of the eyeline J0, and the stage 104 includes the use of In order to obtain the source of Bei = Zha7. Usually, the instruction is by a corresponding instruction indicator (Ip) = no. Therefore, the level 102 includes a command indicator (ιρ) multiplexer (M "), a command quick memory (I-quick memory) U0, and branch prediction module 120. Please remember : The part of the fast memory ιι〇 and the branch prediction module 120 extends to the acquisition level 104. The pipeline 100 has the fast memory 11 〇 and the branch prediction module 丨 20 and other locations and sizes indicate their respective positions and sizes. When to receive the instruction indicator (IP), and where it processes the received instruction indicator (Ip)

4 5 58 1 4 V. Description of the invention (5) It takes time. For example, the instruction index (IP) multiplexer 130 selects an instruction index (IP) in the first half of the stage 102. I fast memory 1 1 0 and branch prediction module 1 2 0 receive the instruction index (ip) through the IPG level 10 02, and complete the processing during the level 104. An instruction indicator (IP) multiplexer (MUX) 130 receives instruction indicators (ip) from various sources including a branch prediction wedge set 120. Depending on the input from the branch pre-rigidity module 1 20 and other control circuits (not shown), the instruction index (IP) multiplexer (MUX) 130 will consume one of its input instruction index (ip) to I -Quick memory 120 and branch prediction module 丨 20β When the instruction index (IP) selected in the text is received, 1_Quick memory 11 and branch prediction module 120 initiates the review process: to obtain relevant information Information on the selected order indicator (IP). In particular, Bu Yiji Yiyi 丨 10 stores a copy of the selected instruction, and uses its corresponding instruction index (Ip) as an index. The received instruction index (ίΡ) is compared with its registration item ', then the corresponding instruction is transmitted to the pipeline two-level ν / Λ: When the registration item' is a circuit (not shown) in the 浐 俨 r T D,,. If you know that ^ crystal ^ (IP) in the I-fast memory, such as by the memory subsystem (not shown), lj buckle 7 is borrowed. Potential period changes and read the branch prediction module 1 2 0 Store the selected message 'The instruction index (Ip) branch of the branch instruction; if the branch prediction data is like an indication,' A is it possible to use the Correspondence =. This information includes examples of residential addresses (instruction indicators ([p)), where, for example, a knife is used to predict the use of the branch, the

4 5 5 8 1 A Five 'invention description (6)-pipeline 100 leads to the predicted target address. When the instruction indicator (IP) forwarded by the instruction indicator (ίρ) multiplexer (MUX) 130 hits the branch prediction module 1 20, it accesses and reads the score related to the hit registration item. Branch prediction information to decide whether to predict that branch. If it is, the corresponding target address (instruction index (IP)) is coupled back to the instruction index (ιρ) multiplexer (MX) 130 to redirect the pipeline to the code sequence starting from the target address. The primary question 122 controls the timing of coupling the signal from the branch prediction module 120 to the multiplexer (MUX) 130. Branch instructions are relatively common in computer code 'and occur on average every 5 to 12 instructions. In order to adjust the prediction information of a rational decimal that is often encountered in branch instructions, the branch prediction module 丨 2 0 must be a relatively large structure. The size of the branch prediction module 120 is limited by the timing considerations in the pipeline 100. If the branch prediction module 120 is too large, it will have a relatively long access km size to predict the branch size. The accuracy of the branches also affects the speed of the branch prediction system. More accurate branch prediction algorithms tend to be more complex and require additional time to provide a prediction for a branch instruction. As such, Erming, the branch prediction module 120 is used to access-predict each additional clock cycle required to allow additional instructions from the wrong execution path (bubble, ') to be input into the pipeline 100. Therefore, the size of the two pre-two 20 is usually selected and its prediction algorithm is selected, so that the pipeline can be redirected within a few clock cycles after the follow-branch instruction. The trade-off between the pipeline speed and the provision of a relatively large amount of unbranch accurate branch prediction hints that appear in most computer code.

Page 10 V. Description of the invention (7) ^ The trade-off between speed and size / accuracy may have significant weights. For example, when the redirection requires two clock cycles (the effect of a re- ^ of 1 bubble.), It has a large cycle count. Each loop of the loop will be bubbled each time. If there are only a few materials in the main circuit of the circuit, such as “to-road”, then the bubble can represent an important decline in resource use. Closely back to the present invention is a hierarchical branch prediction system, and the branch selected by Wei Cai instructs its speed. With the size / fine production / optimization or improvement of the present invention, the branch prediction system includes the first and the second, and the house. According to the hint generated by the compiler, two funds are saved: the storage structure, and the first and second storages are used. Structure write logic. The test information configures the prediction information of the selected branch instruction, and stores the branch prediction information of the branch instruction group stored in the structure storage; 'Generation: knot: storage-larger can implement a more accurate The branch prediction is based on the second storage structure and the larger branch prediction capacity of the branch. The branch prediction is more accurate for the specific branch. Information, 偁 fork supply soap-cycle access in more cycles to access branch prediction information. Eighty-two storage structure is provided in two or according to various branch-related instructions: branch prediction manager (BPM) root branch prediction information Stored in One or Chu_ shows the information provided, and the branch prediction information can be based on the ~ branch storage f structure. An important stop of the information is stored in the designated branch prediction information in the relevant instruction. In a specific embodiment, the second f or the second storage structure is used to indicate: the importance of predicting that information should be stored in a single bit. The meaning of the meaning of the “n bit”, which is the meaning of the storage structure. A wider range can be used to select branch prediction information

Λ55814 V. Description of the invention (8) Selectively stored in a 2n level hierarchy of the branch prediction storage structure 3 For a specific embodiment of the present invention, the branch-related instructions include branch prediction instructions (BRPs), branch instructions ( BR), MOV_TO-BR instruction (M0V branch prediction instruction (BRP) designation related instruction index (IP) relative branch prediction target address' prediction guidance (adopted / not adopted), and importance reminder The branch index (BR) instruction related to the instruction indicator (IP) specifies its target address and may also include a hint of importance ^ The MOV instruction specifies the target address of a non-oriented branch and may also include a hint of importance. In addition to important Out of sexual prompts, each of these branch-related instructions can provide prediction hints, indicating which resources should be used to predict related branches. For example, prediction hints can indicate: a branch is static or dynamic prediction. Static prediction uses branch-related instructions. And compile time information provided, and dynamic prediction uses information gathered during code execution. Providing branch prediction information in the processor pipeline early helps To quickly obtain and follow instructions along the appropriate instruction path. As long as the structure storing this information does not load important paths into the processor pipeline, or becomes too tricky to introduce unnecessary pipeline bubbles into the often used internal circuit branch This strategy is beneficial. The present invention provides a layer of the structure for storing branch prediction information, and can promote the branch prediction information without hindering access to the branch instruction information of an important category of the branch instruction. The use of branch prediction information for all branch instructions. Figure 2 is a block diagram of a portion of a processor pipeline 200, which includes a branch prediction system 2 8 0 according to the present invention. At the same time, an instruction indicator UP is displayed. Tool (MUX) 250, one instruction quick memory (I-quick memory

Page 12 455814 V. Description of the invention (9)) 21 〇, an instruction buffer 2 〖4, distribution logic 216, and a branch execution unit (BRU) 270. Instruction indicator (IP) multiplexer (MUX) 250 receives instruction indicators (IP) from various sources, and integrates a selected instruction indicator (IP) to I-Quickly remember billion body 21 G and branch prediction system 28 0 for processing. Instructions from I-Quickmemory 2 10 or side-by-side (not shown) are stored in buffer 214 and are routed to the execution resources such as branch execution unit (BRU) 270 through the distribution logic 216 . When the buffer 214 is blank, the instruction may also be transferred directly from the I-flash memory 21 to the distribution logic 216. For a specific embodiment of the pipeline 200, the instructions that can be processed at the same time are &amp; integrated bundles. A metric board associated with each instruction bundle refers to the distribution logic 21 &amp; &quot; ^ instruction type, which guides the instruction path to the appropriate execution resources. The instruction frame may include multiple branch instructions. In this case, the branch execution unit (BRU) 2 70 includes resources to process multiple branch instructions at the same time. Some characteristics of the branch prediction system 280 are described in a specific embodiment designed for bundling, but the present invention has nothing to do with how instructions are provided to the pipeline 200. The pipeline 200 is represented as a series of pipeline ("tubular") stages 2101-2χ to indicate when the different elements of the branch prediction system 280 operate on a given instruction. Except where noted, the signal travels from left to right, so, for example, during the clock (CLK) period N, the circuit response in the tubular stage 201 will propagate to the clock (CLK) period N +1 in its tubular stage 002. Circuit. The stage latch 2 1 8 controls the signal flow between the tubular stages 2 (Π-2χ. Other embodiments of the present invention may use a different relative configuration of the branch prediction element and the stage latch 218. The present invention is not intended to take

Page 13 4 5 58 1 4 V. Description of the Invention (10) In the specific embodiment disclosed by the invention, the 'branch prediction system 280 includes a target address register (T AR) 2 3 0, a target address shortcut memory ( D a) 24 0, a branch prediction table (BPT) 220, selection logic 254, and branch prediction manager (BPM) 260. Coupling the target address register (TAR) 230, the target address flash memory (TAC) 240, and the branch prediction table (BPT) 220 (collectively referred to as the "branch storage structure") for receiving instructions from the instruction indicator (IP) A multiplexer (MUX) 2 50 is an instruction index (IP), and when the received instruction index (IP) matches one of its entries, the branch prediction information is provided to the selection logic 2 5 4. The selection logic 2 5 4 guides the branch prediction information from one of the paths of the branch storage structure back to the instruction index (〖P) multiplexer (MUX) 250 for processing. Therefore, the branch prediction structure is combined with the selection logic 254 and the instruction index (IP) multiplexer (MUX) 2 50 to operate. A branch used for prediction is used to redirect the pipeline 2 when it hits the branch prediction system 280. 〇〇. Target address register (T AR) 2 2 0, target address shortcut memory (T AC) 2 3 0 'I-shortcut memory 210, and branch prediction table (BPT) 2 20 are related to level 20 1 and The 20 2 extension indicates the time required for each structure to process the received instruction indicator (IP). In the disclosed specific embodiment, the target address register (TAR) 23 0 is designed to process a received instruction index (IP) 'and provide related branch prediction information to a single clock cycle to Selection logic 254. This is done, for example, by limiting the target address register (TAR) 230 large &amp; small 'to reduce its potential access period. In a specific embodiment, the ^^ address temporary register (TAR) 230 stores the predicted target addresses of the four branch instructions (BR) in four completely related entries, the entries are

O: \ 59 \ 59052.PTD Page 14 ab 5 8 1 4 Five 'invention description A hit in the address register (TAR) 23 0 is before the clock cycle N + 1, that is, the zero bubble is redirected When quoted, a predicted a-mark address is provided to the instruction index (IP) multiplexer (· X) 250. Because the target address register (TAR) 230 supports zero-bubble redirection, it is suitable for storing branch prediction information for branch instructions that have the greatest potential to impact processor performance. For a courteous embodiment, the circuit used for prediction The branch instruction has branch prediction information marked with a storage location in the target address register (L) 230. As discussed below, the branch prediction manager (βρμ) 2 60 processes branch prediction information and writes it to the target address register (TAR) based on an indication of the importance of the branch to processor performance. 230 and target address quick access memory (TAC) 240. In this specific embodiment, the target address register (TAR) 230 does not need to store the predicted branch decision, because each branch instruction provided by the target address register (TAR) 230 for a target address is predicted to be adopted. When an instruction index (IP) hits the target address register (TAR) 230, the selection logic 254 can transfer one hundred standard addresses from the target address register (TAR) 230 to the multiplexer (MUX) 250. The small target address register (TAR) 23 0 is partially adjusted by the branch prediction table (BPT) 22 0 and the target address fast memory (TAC) 24 0 to compensate for 'resize' and adjust a relatively large Branch prediction information for the number of branch instructions. The larger branch prediction table (βρτ) 2 2 0 and the target address Quick Access Memory (TAC) 240 prevents it from responding until the level 20 2 section is completed. For the specific embodiment disclosed, this results in a two-clock cycle branch prediction potential period 'and a single bubble redirection of its pipeline 2 0 for a branch instruction that hits the target address fast memory (TAC) 24 0 . therefore,

Page 15 455314_ 5. Description of the invention (12) &quot;-Although the target address register (TAR) 230, the target address shortcut memory (TAC) 240, and the output of the branch prediction table (βΡΤ) 22 are coupled to the stage The selection logic 254 in 201, but the branch prediction table (βρτ) 22 and the target address fast memory (TAC) are generated a complete clock cycle after the output of the target address register (TAR) 23〇 is generated. ) 24 of these outputs. In the specific embodiment disclosed, the target address flash memory (TAC) 24o and the branch prediction table (BPT) 220 are separated structures', but they can also be implemented in a unified structure. In a specific embodiment of the present invention, the branch prediction table (βρτ) 22 and the target address shortcut memory (TAC) 240 can store the prediction decisions and target address information of 64 registration items in one or four ways. Configuration. When the phase indicator (IP) multiplexer (MUX) 23 0 provided in the clock cycle N-the branch instruction indicator (IP) fails in the target address register (TAR) 230 is a branch prediction table A hit in (BPT) 220 and / or target address shortcut memory (TAC) 240 will be temporarily stored in the clock cycle N + 1, and the corresponding prediction information will be from clock cycle N + 2 MUX 250 acquired. Depending on how the branch prediction information is updated, the branch prediction table (Βρτ) 220 and the target address fast memory (TAC) 240 do not need to hit the same instruction index (IPs) in the register. Branch prediction management M (BPM) 2 6 0 processes branch prediction information, and then updates the target address register (TAR) 23, target address flash memory (TAC) 240 'and branch prediction table (BPT) 22 (^ In particular, the branch prediction manager (BPM) 2 60 recognizes branch prediction information from various branch-related information, and extracts the identified information based on the hints contained in the branch prediction information.

Page 16 d55B 1 4 V. Description of the Invention (13) Supply to branch storage structure. Branch prediction manager (BPM) 26. At the same time, it can provide target address temporary register (TAR) 230, target address shortcut memory (TAC) 240, and branch prediction table (BPT) 22 0 (static prediction). The prediction information of the branch instruction, check the accuracy of the branch prediction information from the target address register (TAR) 230, the target address flash memory (TAC) 240 'and the branch prediction table (BPT) 220, and check the accuracy of the branch prediction information. When an error is detected, an instruction indicator (IP) is provided to redirect the pipeline 200. The branch prediction manager (BPM) 260 can also receive branch prediction information from the branch execution unit 270 at the same time. For example, the branch execution unit 270 may decode the hints from the branch (BR) and MOV-TOJR instructions and the target address information, and provide this information to the branch prediction manager (BPM) 26 to update the target address temporary storage. Device (TAR) 230, target address shortcut memory (TAC) 240, and branch prediction table (BPT) 2 20. This information provides a dynamic composition to branch prediction information 'to subsidize the static composition provided by software-oriented prompts. Branch Prediction Manager (BPM) 260 operates in conjunction with Target Address Temporary Register (TAR) 2 30, Target Address Shortcut Register (TAC) 240, and Branch Prediction Table (ΒΡΤ) 2 2 0 to provide One level of branch prediction structure. Table 1 summarizes the different redirect events, conditions, and goals implemented by a specific embodiment of the branch prediction system 280. For the specific embodiment represented in Table 1, N instructions are grouped into a bundle for processing at the same time. Multiple branch instructions may be included in an instruction bundle, and the instructions are designated as the first order based on the relative order in the code. 1-Section Ν.

Page 17 4b58 1 4 V. Description of the invention (14) Table 1 ---- Event type (priority order) Pre-condition conditions reason! Retargeting address register (TAR) Redirection (4 'lowest priority order) No Target Address Register (TAR) Hit Target Address (TA) from Target (TAR) Target Address Quick Memory (TAC) Redirect (3) First Match ----- No Target Address Register (TAR) Redirection 1) Hit in target address shortcut memory (TAC), the adoption of branch prediction table (BPT) predicted on the same instruction bundle (TK) and branch does not return 2) Target address selection Hit in memory (TAC), and mistake in branch prediction table (BPT) 3) Hit in address shortcut memory (TAC), predicted by branch prediction table (BPT) on the same instruction bundle (TK ) And branches for return 1) Target address (TA) from target address flash memory (TAC) 2) Target address (TA) from target address flash memory (TAC) 3) From return stack buffer ( (RSB) target address (TA) Dao Yi gave the addressee S yuan (BAC1) to guide again (2) no target address register (TAR) or target TAC redirection 1) Errors in the target address shortcut memory (TAC), the adoption as predicted by the branch prediction table (BPT) (TK and branches not returning 2) — instruction bundle Any valid branch in the instruction bundle is taken with static prediction (TK), and the last branch in the instruction bundle is not a non-directed branch3)-any valid branch in the instruction bundle is taken with static prediction (TK), and the The last branch in the bundle is an undirected branch. 1) The last branch in the instruction bundle is marked with an address (TA). 2) The last branch in the instruction bundle is marked with an address (TA). 3) From the return stack buffer. RSBk target address (TA) _ 1111 page 18 455814 V. Description of the invention (15) Target address temporary register (TAR) redirection 4) Pseudo branch prediction, no valid branch in the instruction bundle 3) Counting loop, Instructed by the loop predictor: Count or leave at the top loop 4) Next instruction bundle address 5) Next instruction bundle address Second branch address correction unit (BAC2) Redirection (1, highest priority) Instruction east Target address flash memory (CTAC) Branch address correction unit (BAC1) redirection 1) Target address flash memory (TAC) target section identifier (ID) does not meet the first branch prediction used, and the branch is not a non-directional branch 2) Use the first branch address correction unit (BAC1) to redirect with an overflow calculated from the target address (TA) 3) Shield from the first branch address correction unit (BAC1) 4l First adoption (TK) sub-technology Instruction (BR) 'there is not a non-directed branch instruction (BR). There is an adoption (TK) branch. 4) The first adoption (TK) branch instruction from the first branch address correction unit (BAC1). (BR) is not the last bar and is not a non-directional branch 5) The first adoption (TK) branch instruction (BR) from the first branch address correction unit (BAC1) is not the last bar and is a non-oriented Branch 1) From the second branch address correction unit (BAC2> iL first adoption (TK) target address (TA) 2) From the second branch address correction unit (BAC2) first adoption (TK) target address ( TA) 3) From the second branch address correction unit (BAC2), the first adoption (TK) S marked residential address (TA) 4) from the second branch First use (TK) target address (TA) of the address correction unit (BAC2) 5) From the return stack buffer (RSB) 4l target address (TA)

Page 19 455814 V. Description of the invention (16) 6) _ mask from the target address 6) from the target first branch address correction unit (BAC1) re-entering the stacking fast memory (TAC) / punch (RSB) The first adopted branch instruction (FTB) 'is that there is a branch instruction using (TK) in the instruction bundle, and the adoption (TK) branch is a non-directed branch instruction (BR) address (TA) ) Head on the instruction bundle 7) Mask from the target address 7) Next instruction bundle address mark address short note short memory (TAC) / memory body (TAC) / first branch address correction one branch address update unit (BAC1) The first branch of the redirection unit (BAC1) uses the branch redirection instruction (FTB), and no other branch instruction (BR) in the instruction bundle is adopted (TK). In Table 1, TK indicates a point. For branch prediction / decision, TA refers to the target address, FTB refers to the branch adopted first, and RSB refers to a return stack buffer of the target address (TA) to return. FIG. 3 is a block diagram of a branch prediction manager (BPM) 260 according to an embodiment of the present invention. For illustration, the specific embodiments disclosed include the inspection characteristics noted above, and can process up to two instruction bundles at the same time, including instruction bundles with multiple branch instructions ("multi-mode branch"). Those who are familiar with this technique and who have benefited from this disclosure will recognize a branch prediction manager (BPM) 2 6 0 correction to handle more or fewer instructions. Specific examples of the disclosed branch prediction manager (βPM) 2 6 0 include

Page 20 4 5 5 3 1 4 V. Description of the invention (17) A first branch address correction unit (BAC1) 3 I 0, a second branch address correction unit (BAC2) 360, and a path guidance module 370. Also shown is a mode multiplexer (MUX) 306 that couples instructions and decoded information from the previous stage to a branch prediction manager (BPM) 260 and an instruction buffer 308. The first branch address correction unit (BAC1) 310 and the second branch address correction unit (BAC2) 3 60 process the instruction index (IP) and instruction decoding information to identify branch prediction information, check for errors in the identified information, and If the decision is wrong ', correct the information. The path guidance module of the path guidance module 370 processes the tips and branch prediction information from the first branch address correction unit (BAC1) 31 and the second branch address correction unit (BAC 2) 3 600. To determine an appropriate storage structure for the predicted information. The path guidance module 37's path guidance module will be discussed in detail in conjunction with FIG. A specific embodiment of the first branch address correction unit (BAC1) 310 initially determines a target address of an instruction bundle, and a first branch instruction in the instruction bundle predicted to be used. It also recognizes a fake branch instruction, that is, when no branch instruction appears, it is in the target address register (TAR) 23, the target address shortcut memory (TAC) 240, or the branch prediction table (BpT) 220. Hit. The first branch address correction unit (BAC) 310 includes merging logic 320 'to find a first adoption branch in an instruction bundle using the logic of a multi-branch instruction (FFT logic 324), and a decoder 3 28, using To evaluate (predict) branch-oriented. The first branch address correction unit (BAC1) includes addresses 312, 314'316, 318, and a multiplexer (MUX) 338 for evaluating branch target addresses, including a pseudonymous decoder 334 and a multiplexer (Μυχ ) 330 'to identify pseudo-branch prediction. ’

45 58 1 4 V. Description of the invention (18) The decoder 312 receives instruction information including, for example, branch prompt information from the I flash memory 210. The hint information may include an indication that a branch should be predicted dynamically or statically. If the indication is a static prediction, the hint information may also indicate the predicted branch-oriented (TK / NT) e merge logic 32. The combined hint information and from the target address register (TAR) 320 and the target address shortcut memory (TAC) ) Any predicted branch of 340, and multiple branch instruction (FFT) logic 324 determines a first adopted branch from the decoded and predicted information. Multiple branch instruction (FFT) logic 324 uses a multiplexer (MUX) 338 to select an offset to calculate the second branch address correction unit (BAC2) 360 (predicted) whose target address is the first branch used . Addresses 312 and 316 use the decoded information from the branch prediction instructions (BRP) in the first and second instruction bundles, respectively, to determine the branch target address. The target address is provided using a multiplexer (MUX) 2 50. It is determined by the instruction index (IP) and the address offset specified in the branch prediction instruction (BRP). The addresses 314 and 318 use the instruction instruction index (ip) and decoded offset information to determine the branch target address of the instruction index (ip) and its related branch instruction, for example, for static redirection. For a specific embodiment of the present invention, the addresses 314 and 318 can be simplified, such as excluding the selected carry logic to meet the timing constraints required to provide the redirect instruction index (IP) to the selection logic 254. If an address shortcut generates a carry, the correct address can be determined by a full adder (358) in the second branch address correction unit (BAC 2) 360. In order to limit the size of the branch prediction manager (BPM) 260, not all instruction slots in an instruction bundle need to provide adders. For the specific facts disclosed

Page 22 ^ 5581 4 V. Description of the invention (19) Example, the adders 3 1 2 and 3 1 6 calculate the target address of the branch prediction instruction (BRP) in the specific instruction slot of the first and second instruction bundles, respectively. . Similarly, the adders 31 4 and 3 1 8 calculate the target address of the branch instruction (BR) in the specific instruction slot of the first and second instruction bundles, respectively. For example, when the instruction bundle is three instructions wide, the third instruction slot of each instruction bundle processed at the same time can be consumed by the adder 3 1 2, 3 1 4, 3 1 6, 31 8 and the branch instruction can be The priority path leads to these instruction slots. In this specific embodiment, the target address of the branch instruction that is not assigned to the third slot is a value added by an adder (adder 35 8) ordered by the second branch address correction unit (BAC2) 2 60 The detector 334 can ensure that the target address register (TAR) 230, the target address flash memory (TAC) 240, and the branch prediction table (BPT) 22 0 hit the instruction index (IP) corresponding to the branch Related instructions. For example, the target address shortcut memory (TAC) 230, the target address register (TAR) 2 40, and the branch prediction table (BPT) 220 may use only one knife of an instruction index (IP) as their stored data. The index β of the branch prediction information can save the area of Shi Xi in this way, but some instruction indicators (IP) may correspond to addresses of more than one instruction ("alias"). The detector 334 uses the instruction to decode information to ensure that a hit instruction index (IP) generated in the branch memory structure corresponds to the branch-related instruction. Multiplexer (MUX) 33 0 selects an instruction indicator (IP) under the control of the alias detector 334 and couples it back to the selection logic 254 for detecting an error event in the branch prediction information In the middle, redirect the bow 丨 pipeline 20-branch address correction unit (BAC1) redirection). A specific implementation of the second branch address correction unit (BAC2) 360-the preliminary result of the branch address correction unit (BAC1) 310,

4558 1 4 V. Description of the invention (20) Validity check 'Next and update the target address register (AR) 2 3 0' The target address shortcut memory (T AC) 24 0, and the branch prediction table (B ρτ) 2 2. In the specific embodiment of the road disclosed, the 'Target Address Quick Memory (TAC) / Branch Prediction Table (BPT) check module 344 decides whether the branch prediction table (Bρτ) 22 is used to predict whether the branch and target are used. The address shortcut memory (TAC) 240 provides branches related to the target address. If the result is inconsistent, the target address quick access memory (TAC) / branch prediction table (Βρτ) check module 344 uses the address generated by the second branch address correction unit (BAC2) and obtains it according to the 77 branches. Quietly predicting information and redirecting. When the carry logic is excluded from the adders 3 1 4, 3 1 8 to meet timing constraints, the included adder check module 3 4 8 is used to detect overflow errors. The adder check module 348 determines whether a target address calculated by the adder 3 丨 4 or 3 丨 8 generates a carry ', and when a carry is detected, the entire adder 3 5 8 is triggered to recalculate the target address. The mask validity module 3 50 determines when one of the instruction slots served by the adder in the first branch address correction unit (B A C1) 3 1 0 does not have a predicted first adoption branch. In a specific embodiment of the Branch Prediction Manager (BPM) 260, a mask indicates an unserved instruction slot. When the adopted branch exists in a shaded instruction slot, the mask validity module 3 50 uses the multiplexing Is (MUX) 3 5 4 to select the target address from the adder 3 58. The output of the multiplexer (MU X) 354 provides the target address to the selection logic 254 to redirect the pipeline (the second branch address correction unit (BAC2) redirects). Path guidance module 370 updates the target address register (TAR) 230 with the data from the decoded branch instruction (BR) and branch prediction instruction (β Rp) instructions. The target address is fast.

O: \ 59 \ 59051PTD Page 24 4 5 5 8 1 4 V. Description of the invention (21) Flash memory (TAC) 240 'and branch prediction table (BPT) 220. FIG. 4 represents a pipeline 400 for updating the target address flash memory (tac) 23 and the target address register (TAR) 240. Although in the pipeline 200, the target address shortcut memory (TAC) 230 and the target address register (TAR) 240 are physically located in front of the branch prediction manager (BPM) 2600 and the branch execution unit (BRU) 270. But FIG. 4_ shows that it follows the branch prediction manager (BPM) 260 'to emphasize the relative timing of various decoding, execution, and update operations. In addition, the disclosed write pipeline 400 embodiment is applicable to the case where the processor pipeline 200 (FIG. 2) processes a maximum of two instruction bundles at the same time. Therefore, the 'target address register (TAR) 230 and the target address flash memory (TAC) 240 are each coupled to two read / write ports (port 0, port 丨) to adjust the two update operations at the same time ^ _ 所In the disclosed embodiment, the first branch address correction unit (BAC1) 310 and the second branch address correction unit (BAC2) 360 of the branch prediction manager (βPM) 2 60 are displayed at the tubular levels 402 and 4 03 in. The target address register (TAR) 230 is represented as a target address register (TAR) reading module 430 and a target address register (TAR) writing module 434, which are accessed at levels 403 and 404, respectively. Similarly, the target address shortcut memory (TAC) 240 is represented as a target address shortcut memory (TAC) reading module 440 and a target address shortcut memory (TAC) writing module 444, in levels 403 and 404, respectively. access. The path guidance module 370 includes a source selection multiplexer (MUX) 412, 414, a write control multiplexer (MUX) 460, 464, and its control logic (not shown). A source selection multiplexer (MUX) 41 2 and 41 4 Select destinations from various sources

Page 25 0 0814 V. Description of the invention (22) address, and couple the selected target address to target address register (TAR) 230 and target address flash memory (TAC) 240, port 0 and port 1, respectively. In the disclosed embodiment, the first branch address correction unit (BAC1) 3 1 0 provides the target address from the decoded branch prediction instruction (BRP) instruction to the multiplexer (MUX) 412, 414 'and The branch execution unit (bru) 170 provides the target addresses from the decoded branch instruction (BR) and M0V_T0_BR instruction to multiplexers (MUXs) 412 and multiplexers (MUX) 414, respectively. The multiplexer (MUX) 414 can also receive data from the second branch address when a predicted target address is not correct or when the calculation of a target address exceeds the capacity of the first branch address correction unit (BAC1) adders 314, 316. A target residential address for correction unit (BAC2) 360. The write control multiplexer (MUX) 460, 464 uses decoded hint information from various sources to control whether the target address from the multiplexer (MUX) 412, 414 is written to the target address register (TAR) 230, Target address shortcut memory (TAC) 2 4 0, or both = For a specific embodiment, the first branch address correction unit (BAC1) 360 provides important hints from the decoded branch prediction instruction (BRP) instruction, The branch execution unit (BRU) 270 provides important hints from the branch instruction (BR) and M0V „T0_BR instruction. Arrival to the multiplexer (MUX) 412 '414 The control signal is based on the events detected in pipeline 200' For example, command type, prediction prompt, check error, etc. 'to select a target address source. The selected target address is provided to the target address register (TAR) reading module 4 30 through port 418 through the level latch 418. Port 1. The target address register (TAR) reading module 430 determines whether the selected target address matches one of its registered items ("hit") Q If detected

Page 26 abb8 1 4 V. Description of the invention (23) is a hit, and the corresponding hit bit is set, then the target address is written to the hit registration entry in the target address register (TAR) written in the module 434. If there is no hit in the measurement but a corresponding prompt bit is set, a registration item is configured in the target address register (TAR) writing module 434, and the target address is written to the configured registration item. In a specific embodiment, the target address register (TAR) 230 implements a first-in-first-out (FIFO) configuration algorithm. Since the target address register (TAR) 230 is dual-port, it can read and write both entries at the same time. A similar writing procedure is performed using the target address flash memory (TAC) read and write modules 440, 444, respectively. Compare the target address with the entry in the target address flash memory (TAC) read module 440 t. If the detection is a hit, the target address is written to the target address shortcut memory (TAC) and the hit entry of module 4 4 0 is written. If the detection is not commanded, configure a login item and write the target address to the configured login item. In a specific embodiment, the target address shortcut memory (TAC) 24 0 implements a least-recently-used (LRU) configuration algorithm. Therefore, the write pipeline 400 allows branch prediction information to be written to the target address register (TAR) under the control of various branch-related instructions (branch instruction (M), branch prediction instruction (BRP), M0V_T0_BR). 230 and target address quick access memory (TAC) 2 4 0. For example, the 'importance block' may be included in these instructions to indicate whether the branch prediction information specified in the instruction should be configured with a target address register (TAR) 2 3 0 or a target address flash memory (TAC) 240. A compiler may set one or more bits in the importance field of these instructions based on the information about the relevant branches available at compile time.

Page 27 4 5 5814 V. Description of the invention (24) Various rules can be used to indicate the branch prediction information of the target address register (TAR) 230 or the target address flash memory (TAC) 240. These rules are characteristics related to the predicted information about branches. For example, since the 'Target Address Register (TAR) 23' at the time of branching provides effective redirection of pipeline 200, when branch prediction is adopted, branch prediction information can be easily stored in The target address register (TAR) is 23 °. Furthermore, since the branch prediction information is decoded by the compiler ', it is particularly appropriate to select the branch that can be predicted based on the information available at the time of compilation. Because the size of the target address register (TAR) 230 is relatively small, it is impossible to adjust the prediction information of all branches used for prediction. Additional rules can be used to reduce the number of competing branches. For example, repeat the branch of the access control loop until the loop terminates. Β is repeated through a branch such as "Counting Top Loop, (CTOP-) and" When Top Loop "(WToop). Each time the loop repeats, it can get help from zero bubble redirection. This is especially true for top loops with relatively few instructions ("tight loops,") in the loop body. In these cases, even a single pipeline Bubbles can still represent an important part of the recursion period. Therefore, the branches related to (counting or when) the top circuit are good choices for storing the prediction information in the target address register (TAR) 230. The target address flash memory (TAC) 24 is provided to the branch. Branches of the branch prediction information are branches that are less important to the processor performance than the target address register (TAR) 230. The target address shortcut memory (TAC) 230 can also adjust the branch prediction information shifted from the target address register (TAR) by 22 ° through the branch prediction information provided subsequently. therefore

1H9 Page 28 4 5 58 1 4 V. Description of the invention (25) The availability of the target address fast memory (TAC) 240 allows the branch prediction speed / accuracy of branches in important code sections to be reduced without reducing the performance. Software hints are widely used to configure branch prediction information in the branch prediction system 280. FIG. 5A is a block diagram of a branch prediction instruction (BRP) 50 0, which is suitable for transmitting branch prediction information to the branch prediction system 280. The branch prediction instruction (BRP) 500 includes an opcode field of 51 0, a "yes / no" field of 5 14, a importance prompt field of 5 1 8, a target stop of 5 20, and a marker stop. 524 »Op Code Field 51 ◦Indicate that this instruction is a branch prediction instruction. The yes / no block 51 4 indicates how the branches should be predicted, such as ‘with / without, dynamic / static prediction, and the like. The flag bit 5 1 8 indicates an address of the relevant branch instruction (BR), and the target stop 52D indicates a predicted target address of the branch instruction (BR). The importance hint field 524 indicates the relative importance of providing a low-potential-phase branch prediction for the relevant branch. The branch prediction manager (BPM) 260 uses the importance prompt fields 5 24 to guide the data from the target field 520 to one or more branch storage structures. FIG. 5B is a block diagram of a branch instruction (BR) 540. The branch instruction (BR) is suitable for transmitting importance information to an instruction index (IP) -related branch prediction system 280. The branch instruction (BR) 540 includes an opcode field 544, a branch type field 548, a target bit field 5 50, a yes / no field 5 54 ', and an importance field 558. When the branch type block 548 indicates, for example, a call, return to the 'counting loop, the modulo-scheduled counting loop, and the modulo-schedule is a branch type such as the loop, the opcode block 544 branches the instruction ( BR) 5 4 0 is identified as a non-directed branch instruction (BR). Branch prediction

Page 29 45 58 1 4 5 'Explanation of the invention (26) The administrator (BPM) 260 guides the data from the target field 550 path to one or more branch storage structures according to the status of the importance position 558. FIG. 5C is a block diagram of a MOV_TO_BR instruction 560. The mOV_TO_BR instruction is suitable for transmitting branch prompt information of non-oriented branches to the branch prediction system 280. MOV instruction 560 includes an opcode field 564, a branch type field 568, a target field 5 70, a register block 574, an importance block 578, and a yes / no block 58 0 . Opcode block 5 64 identifies the instruction as a MOV-TO-BR instruction. Target block 5 70 specifies the target address, and register field 574 specifies the branch register in which the target address is stored. The data from the target field 5 7 0 is provided to the target address register (TAR) 2 3 0 and / or the target address shortcut memory (TAC) 240 according to the status of the importance field 5 7 8. FIG. 6 is a flowchart of a method for storing branch prediction information according to the present invention. In the disclosed specific embodiment, the method 600 can be initiated, for example, when a branch prediction manager (BPM) 260 or a branch execution unit (BRU) 270 decodes a branch-related instruction. When an appropriate instruction is detected (6 丨 〇), the branch prediction information contained in (6 2 0) is retrieved, and it is determined (6 3 0) whether to set the importance bit in the instruction. If the (6 3 0) importance bit is set to 则 ′, the branch prediction information is stored in the branch prediction structure of the lowest potential period, such as the target address register (TAR) 23 〇. In a specific embodiment, when the branch prediction information is subsequently removed from the target address temporary register (TA R) 2 3 0 ′, it can also be stored in the target address fast memory (TAC) 24 0 _. If the (6.30) importance bit is not set, the branch prediction information is stored in a branch prediction structure in a southward potential period, such as a short note of the target address

Page 30 4 5 5 8 1 4 V. Description of the invention (27) Yi Zhao (TAC) 24 (3 and branch prediction table (βρτ) 220. In some examples, the branch instruction (BR) may pass through the processor pipeline 2000 and its related branch prediction instruction (BRP) instruction, so before the branch instruction (BR) is needed, there may not be enough time to store the branch prediction information from the branch prediction instruction (CBRP) instruction. In these cases, the branch prediction information may be directly coupled to the instruction indicator (11 &gt;) multiplexer (MUX) 250 through a bypass structure (not shown) '. FIG. 7 is a flowchart of a method 700 for using branch prediction information according to the present invention. The method 700 is initiated when a new instruction index (Ip) is transmitted (70 [)) to the branch prediction structure, such as in level 202, during a first clock cycle. If the instruction index (IP) hits (72) an entry in the branch prediction structure of the low potential period (target address register (TAR) 23〇), then in the next clock cycle period, it will be related to the entry A predicted target of the item was sent back (IP). If the instruction index (UP) fails in a structure with a low potential period (7 20), then the method 700 waits (74) for a structure with a higher potential period (target address shortcut memory (TAC) 24), a branch prediction table ( Βρτ) 22〇) If the structure of the higher potential period indicates a hit (740), then at the next time, one of the-, the target instruction of the hit entry, and the structure of the lower potential period will be ^ Error (740) instructions • Enter the structure of the lower potential period "branch instruction (βΐ〇, or u I () sub-corresponds to a subdivision. If additional :::; branch instruction (BR) available The branch prediction resource m continues to search for such information that can be used for branch prediction information, and then the method X and other structures are hit. If the new instruction index

Page 31 b8 1 4 V. Description of the invention (28) (IP) does not represent a branch instruction 7 7 0 determined by the branch prediction manager (BPM) 2 60, for example, the branch prediction included in the instruction The information can be used to update (780) the first or second branch prediction structure (BPS) according to the included prompt information »The present invention has described a system in which the branch instruction uses its corresponding instruction index (IP) as the Index β However, this is not necessary, and some notations can be used for branch instructions for this purpose, such as branch instruction opcodes. Furthermore, the present invention has described the case of a branch prediction hierarchy of a two-branch prediction structure. Those skilled in the art will recognize that the present invention can be quickly applied to the branch prediction hierarchy of a branch prediction structure with more than two layers. In these cases, the Branch Prediction Instruction (BRP) instruction will use the corresponding larger hint field and will provide additional categories of the Branch Instruction (BR). _ Therefore, a system and method for fast branch prediction operations have been provided here ^ A hierarchy of branch prediction structures operating under software guidance. The branch prediction information of one of the first types of branch instructions is stored in a small and fast branch prediction structure, and the branch prediction structure can be obtained at one = two: f. The branch prediction information of another type of the branch instruction 俾 the second type. When a branch instruction is in the-structure; in the clock cycle after the clock cycle at the start of the human branch instruction, the 7 indicator (IP) is provided to the first of the drowling cry line of the pipe of the pipe soil. -level. Even at high frequencies, the disclosed invention can still provide the maximum effective branch = estimated early cycle throughput. Branching

Page 32

Claims (1)

4 5 5 8 1 4 .______ Six 'patent application scope 1 · A branch prediction system, comprising: a first storage structure for branch target addresses; a second storage structure for branch target addresses; and A branch predictive manager (BPM) coupled to the first and second storage structures, the branch predictive manager (BPM) identifying a branch target address and an importance indicator in an instruction, and based on the Importance indicator, and write the τ branch target address into the first or second storage structure. 2. The branch prediction system according to item 1 of the patent application scope, wherein the first storage structure has a response potential period which is shorter than the response potential period of the second storage structure. ， ', 3 _ If the branch prediction system of the first patent application scope, wherein the branch prediction manager (BPM) includes decoding logic: to identify the instruction including branch prediction information' and extract from the decoded instruction Take branch prediction information. 4. If the branch prediction system of item 1 of the patent scope is declared, the light branch prediction officer (BPM) is used to receive branch prediction information from a selected instruction from a branch execution unit. 5. A processor comprising: an execution pipeline; a target address register that is lightly closed to the execution pipeline and can store selected branch prediction information 'for changing an instruction flow through the execution pipeline; coupled to A target address shortcut memory of the execution pipeline, which can store technical prediction information 'for changing the instruction flow through the execution pipeline; and coupled to the execution pipeline, a target address temporary register (TAR), and the target address shortcut memory ( TAC) branch prediction manager (BpM) Page 33 6. Scope of patent application '------ = branch prediction information of the instruction in the line, and the detected branch prediction information will be provided according to the temporary ί / ϋ indication specified by the instruction. The target address R) and the target address are provided to the TAC. 62. If the processor of item 5 of the patent application scope, wherein the execution unit includes two tools v execution instructions, the branch prediction information can be retrieved from the instruction and the blade prediction information is coupled to the branch Prediction manager (βρΜ) ^ In ^: The processor of the fifth item in the patent scope, where the target address is temporarily stored in an execution pipeline to obtain a command to receive a command finger: within a single clock cycle, A target address corresponding to the instruction index UP) is returned for storage. Jie U is the processor of item 7 in the patent scope, where the target address is fast: = coupled to to obtain storage, used to receive a command finger #, and in the period of more than 5 5 Yinmai, will correspond to Instruction index (return for storage. 〃 町 目 目 Address I, such as the processor in the scope of patent application No. 8, when the target address temporary mark = return to the target address 1 Prohibit the target address fast memory to return to the target 10 · One The processor includes: an instruction acquisition module;: a coupled target address register (TAR) 'for receiving an instruction indicator (IP) from and, and the instruction indicator ([P) The registration items of the TAR register are in accordance with the Shaw, within the -single-clock cycle; the return-target instruction index (IP); send a coupled target address fast memory (TAC) to receive from The 455814 6. Scope of patent application ~ — Obtain an instruction index (IP) of the module, and when the instruction index (Ip) matches the entry of the target address flash memory (TAC), it will be at two or more clock cycles Incoming a target instruction indicator (I ρ); and a branch prediction manager (BPM) to identify the branch prediction information, and according to an importance indicator in the branch prediction information, from the branch A target instruction index (IP) of the prediction information updates the target address temporary storage (TAR) and the target address shortcut memory (TAC). 11. If the processor of the scope of patent application No. 10, when the importance indicator is set, the branch prediction manager (BPM) writes the target instruction index (IP) to the target address register (TAR) and Target Address Shortcut = (TAC), if not set, when it is important, it is written to the target residence ^ memory (TAC) separately. · 、 12. If the processor of the scope of patent application No. 10, wherein the branch manager (BPM) includes a coupled decoder to receive the instruction 'identify branch related instruction' from the 77 acquisition_ group And branch prediction information is retrieved from the identified branches and instructions. Related 13. If the processor of item 11 of the patent application scope further includes a branch execution unit, which is coupled to the acquisition module and the branch prediction management knife (BPM), the branch execution unit may be branched and branched. The related instructions take eight prediction information and provide the obtained information to the branch prediction management branch (BPM). Stomach 14. A branch prediction system comprising: a target address register (TAR) for storing target addresses of a group of branch instructions; first 6. Scope of patent application—Target address shortcut memory (TAC) for storing the target address of a second group of branch instructions; and—branch prediction manager (βPM) for identifying branch instructions The branch prediction information of the first group and the first group are updated with a target address from the identified branch prediction information and a target address shortcut memory (T ac) and a target address register (TAR). "15. If the branch prediction system of item 14 of the patent application scope, wherein the branch prediction information includes an importance bit 'and when the importance bit is set', the branch prediction manager (BPM) sets the target The address is written to the target address register (TAR). 16. —A branch forecast manager of the hierarchical branch prediction system, the branch forecast manager includes: a branch address calculator to identify branch related The branch prediction information in the instruction; and a path guidance module for providing branch prediction information from the branch address calculator to an indicated position in the hierarchical branch prediction system. The branch prediction manager of item 16, wherein the branch prediction machine includes a prompt and a negative address of the target address' and the path guidance module provides the target address information to the location indicated by the prompt information. 18. If The branch forecasting administrator of item 17 in the scope of patent application, wherein the branch forecasting information is provided by a branch forecasting instruction. 19. If the branch forecasting administrator of item 16 in the scope of patent application, the branch Comprises a first exclusive address even juice branch address calculator for the 'preliminary decision branch prediction of a branch prediction and target address information guide, and a Page 36 4 5 581 4 -------------------- 6. The second branch address calculator of the scope of patent application, used to guide the branch of this preliminary decision Valid with target address. 20. The branch prediction manager of item 19 in the scope of patent application, wherein the branch prediction information is provided by a branch instruction. 21. The branch prediction manager of item 16 in the scope of patent application, wherein the position indicated in the hierarchical branch prediction system is a registration item in a first or second branch prediction structure. 22. If the branch prediction manager of the 21st patent application scope, wherein the first branch prediction structure is a target address register file, supporting pipeline redirection within a single clock of the selected branch, The second branch prediction structure is a target address shortcut memory, which supports pipeline redirection in two or more cycles. · 2 3. If the branch forecast manager of item 22 of the patent application scope, one of the predicted target locations is based on a field in the branch forecast information, and the path is directed to the target address register file or Target address shortcut memory. 24. A processor comprising: a first device for storing branch prediction information of a first group of branch instructions; a second device for storing branch information of a second group of branch instructions ; And a device for managing branch prediction information, the branch prediction information is used to detect branch prediction information in a branch-related instruction, and branch according to the prompt information in the branch-related instruction. The prediction information path is directed to the first or second storage device. Page 455814 6. Application scope of patent 25. For the processor of application scope 24, the management device comprises: a device for generating a branch target address from the branch prediction information; and a device for prompting information based on the prompt information , And guide the branch target address path to the first or second storage device. 26. For example, the processor of the scope of application for patent No. 25, wherein the multiple branches can be processed at the same time, and the generating device includes a plurality of addresses, which is used to calculate the target address of the multiple branches, and is used between multiple branches. Identify the logic of a first adopted branch. 27. For the processor of claim 26, wherein the first adopted branch is determined using the predicted branch information. 28. The processor of claim 25, wherein the management device includes:-a calculator of the first address calculator to determine a preliminary target address and the branch itself from the branch prediction information; and-the first Two address calculators are used to validate the initial target address and the branch itself. 29. The processor of claim 28, wherein the branch prediction information is provided by a branch instruction. 30. If the processor of the scope of application for patent No. 25, wherein the first storage device includes a plurality of registers, a target address can be provided for redirecting the processor in a single clock cycle, and the first The two storage devices include a target address address memory, which can provide a target address address to redirect the processor in two or more clock cycles. Page 38