TW454316B - Multi-chip package module - Google Patents

Abstract

A kind of multi-chip package module mainly contains two semiconductor chips, which are mutually stacked and mounted on a baseboard. The multi-chip package module is featured with having a dummy chip sandwiched between these two semiconductor chips. The size of this dummy chip is smaller than the lower semiconductor chip such that any part of dummy chip will not block the vertically upward region of the chip bonding-pad for the lower chip to avoid blocking its wire bonding process. In addition, the dummy chip has a preset thickness that is enough to provide the required clearance for bonding wires of the lower chip bonding-pad so as to prevent the bonding wires of the lower chip from being damaged by the upper chip.

Description

1543 1 6 V. Description of the Invention (1) [Field of the Invention] The present invention relates to a multi-chip package structure (m u 11 i-c h p p module, MCM), and particularly to a chip-stacked multi-chip package structure. [Previous Technology] As electronic products become thinner and thinner, packaging structures for protecting semiconductor wafers and providing external circuit connections also need to be thinner and shorter. With the miniaturization and increasing demand for high operating speeds, multi-chip packaging structures are becoming increasingly attractive in many electrical devices. The multi-chip package structure can minimize the system speed limitation by combining two or more chips in a single package structure. In addition, the multi-chip package structure can reduce the length of the inter-chip soldering circuit and reduce the signal delay and access time. The most common multi-chip package structure is a side-by-side multi-chip package structure, which is a combination of two More than one wafer mounts the main mounting surface of a common substrate side by side. The connection between the chip and the conductive line on the common substrate is generally achieved by a wire bonding method (w i r e b ο π d i n g). However, the disadvantage of the side-by-side multi-chip package structure is that the packaging efficiency is too low, because the area of the common substrate will increase as the number of chips increases. Therefore, U.S. Patent No. 5 3 2 3 0 60 discloses a multichip stacked device. It includes a semiconductor wafer 11 on a substrate 12 and is electrically connected to the substrate 1 2 And a second semiconductor wafer 13 is stacked on the first semiconductor wafer and is electrically connected to the substrate (see the first figure). This U.S. Patent No. 5 3 2 3 0 6 0 is characterized by

Ρ00-Ϊ42. Ptd page 4 4 5 43 16___, _ Yau, description of the invention (2). An adhesive layer 14 provided between two wafers is used to provide the 1 oops of the bonding wires. Required clearance. The wire bonding process of the first semiconductor wafer 11 must be completed before the second semiconductor wafer 12 is stacked. This means that the die bonding process and the wire bonding process of each layer of wafers need to be performed separately, so additional process steps will be added. In addition, because the gap between adjacent wafers is quite tight, it limits the processing window of wire bonding and wire bonding, which affects the reliability of bonding wires. · In general, the arc height of the bonding wire is about 10 to 15 mils (m i 1). Although by adjusting the line arc parameters, shape and type, the conventional wire drawing technology can reduce the arc height to about 4-6 mils (mi 丨). However, this is already the minimum arc height achievable because if it is lower, the wire will be damaged and its tension will be worsened. Therefore, when using conventional wire bonding technology, the thickness of the adhesive layer 4 must be greater than 6 mils to completely prevent the wafer 13 from contacting the wire arc of the bonding wire 15. The material of the adhesive layer 14 is generally epoxy or tape. However, it is very difficult to form an epoxy layer having a thickness of more than 6 mm and maintain a stable bond thickness. However, once the thickness of the adhesive layer cannot be controlled, not only will the coplanarity (c0Unary ty 2 problem) be caused after the upper wafer 1 3 is installed, but also the upper wafer 3 will touch the lower bonding wire in serious cases. The arc of the line even causes its distortion. In addition, when using tapes up to 6 mils in thickness, on the one hand, it will greatly increase the manufacturing cost; on the other hand, the thermal expansion coefficient (CTE mismatch) between the plastic tape and the silicon wafer will also seriously damage the resulting package. Structural reliability. [Summary of Invention.],

Page 5 Η dSd ^ iβ Five 'invention description C3) The main point of the present invention is to have a virtual lower wafer, the substrate 11 the bonding pad of the virtual wafer pad damages the lower crystal. According to the present invention, two semiconductor wafers are characterized by a wafer The dimensions are not in any part, so it may be possible to provide the present invention with the damage of the underlying solder layer wafer according to the present invention. In order to make this obvious, the following detailed description is given below. [Explanation of the invention] Please refer to the second package structure 200. The structure of a stack mounted on a basic connection trace) 120a ° package structure, which features an upper layer chip and a stacking method mounted on a layer sufficient to provide the lower layer crystal to prevent the upper layer The crystal structure mainly includes conductors between the multi-chip package structures. This design allows the vertical upward structure of the pad of the dummy wafer, due to the side dummy crystal), which can prevent the sign, and the advantages can better understand the attached figure. The main purpose is to provide a multi-chip wafer ( The dummy chip is sandwiched between the upper and lower wafers. The wafers have a clear line of the required clearance. The multi-chip packages of the preferred embodiment are stacked on top of each other and mounted on a substrate. There is a dummy wafer sandwiched between the two halves that is smaller than the lower semiconductor wafer, which will block the wafer soldering of the lower wafer and hinder its wiring process. The gap required for the multi-chip packaging line of the preferred embodiment (c 1 earance layer wafer bonding wire.) For the above and other purposes, the preferred embodiment 1 of the present invention is provided with a drawing, which discloses the preferred implementation according to the present invention. For example, many wafers mainly include two semiconductor wafers 1 10 and 1 3 stacked on each other 1 2 0. The substrate 1 2 has a structure for forming electricity with the outside and includes a plurality of conductive lines (c ο nductive semiconductor wafers). i 1 0, 1 3 0 each with a plurality of wafer pads

P00-142.ptd Page S i fi____ 5. Description of the invention (4) 1 1 0 a, 1 3 0 a is provided on the front side for connecting its internal circuit. The wafer pads 11 Oa and 220a are connected to a plurality of conductive lines i 2a of the substrate 120 via a plurality of bonding wires 152 and 154, respectively. The multi-chip package structure 200 preferably includes a piece of colloid 170 covering the wafers 11 (), 130, bonding wires 152, 154, and a part of the substrate 120. The sealant 丨 7 〇 is generally formed on the wafer 11 0, 1 by using a conventional plastic molding method (for example, a transfer > master forming method (..tran s. 丨 e Γ clawed 〇1 di η § :)). 30 and a part of the upper surface of the substrate. The substrate 1 2 0 may be made of glass fiber reinforced β τ. (Bisma 1 eimide -1 ria 2 ine) resin, or F r _ 4 glass fiber reinforced epoxy resin (core made of fiberglass reinforced epoxy resin). layer) form. In addition, the substrate 12 may also be a film substrate. Or a ceramic substrate (rate). It can be understood that the substrate 120 can also be replaced by a lead frame. The lead frame generally includes a plurality of wires and has an inner pin portion and an outer pin portion, wherein the inner pin portion is used to be electrically connected to the crystal moon. The outer feet are electrically connected to the outside world. Please refer to the second figure again. The feature of the multi-chip package structure 200 is that it has a dummy chip 160 sandwiched between the two semiconductor chips j i 〇, ″ 30 ″. The material of the virtual wafer 160 according to the present invention is the same as that of the semiconductor wafer provided on the substrate. Therefore, it will have a consistent coefficient of thermal expansion (CTE) with the Shi Xi wafer, thereby greatly improving the reliability of the package structure obtained . In addition, the dummy chip does not need wiring because it does not participate in the operation of the entire device. According to the virtual wafer of the present invention, its size is smaller than that of the underlying semiconductor.

POO-142, ptd

Page 7 4543 1 6 V. Description of the invention (5), wafer 1 1 0, so that no part of the virtual wafer 1 60 will bear the straight upward area of the wafer freshness 110a of the lower wafer 110 So as not to hinder its wire-making process. A distance of at least 6 mil (mi 1) is preferably reserved between the virtual wafer 160 and the wafer welding pad I 1 a of the wafer 1 10, thereby retaining a larger working space and increasing the semiconductor wafer 1 1 〇 Reliability of the bonding wire 1 5 2. The virtual wafer 160 is sandwiched between two wafers i 10 and 130 by two adhesive layers 16 2 and 16 4. Suitable adhesive layers such as epoxy compounds (ep 0 X y), thermoplastic materials (tape), tapes, etc. ° Generally speaking, the arc height of the welding wire 1 5 2 is about 10 to 15.5 mil . And by adjusting the parameters and shape of the line arc parameters, the conventional wire drawing technology can reduce the arc height to about 4-6 mils. Therefore, when using conventional wire bonding technology, the bond line thickness of the virtual chip 160 plus the two adhesive layers 162 and 164 must be at least 6 mils to completely prevent the chip 130 from contacting the wire of the bonding wire 152 arc. Preferably, the thickness of the adhesive layer 16 2, 16 4 is controlled to be about 1 mil; therefore, the virtual wafer 1 60 has a thickness of at least 4 mils to provide the required clearance of the 152 (ciearance). In order to prevent damage to the upper wafer _ bonding wire of the wafer. In addition, the virtual chip provided between the two chips provides good thickness control, so the chip 130 has good coplanarity (c ο p I anarity) after mounting, thereby improving the multi-chip package structure. 2 0 0 reliability. Although the present invention has been disclosed in the foregoing preferred embodiments, it is not intended to limit the present invention'to any person skilled in the art, and various changes and modifications can be made without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention

Article 8 I 454316 V. Description of Invention (6) The definition in the scope of the attached patent shall prevail.

ιιηι POO-142, ptd Page 9 4543 1 β Brief description [Illustration] Figure 1: Sectional view of a conventional multi-chip package structure; and Figure 2: Multi-chip package according to a preferred embodiment of the present invention Structural cut-aways. [Illustration of drawing number] 11 semiconductor wafer 12 substrate 13 semiconductor wafer 14 adhesive layer 15 bonding wire 200 multi-chip package structure 110 semiconductor wafer 1 10a wafer bonding pad 120 substrate 120a conductive line 130 semiconductor wafer 130a wafer Hui 152 bonding wire 154 bonding wire 160 virtual wafer 162 adhesive layer. 164. adhesive layer 170 sealing gel

POO-142.ptd Page 10

Claims (1)

^ 45431 ^ 6. Scope of patent application-1. A multi-chip package structure (mult ichi p module), which includes: ... a device for carrying a chip, the carrying device has a device for forming electrical properties with the outside world Connection structure; a first semiconductor wafer is fixed on the carrier device, the first semiconductor wafer has a plurality of first wafer pads arranged on the front surface thereof; a plurality of first bonding wires are electrically connected to the plurality of first wafers A pad to the structure for forming an electrical connection with the outside world; a dummy chip is fixed on the front side of the first semiconductor wafer, so that no part of the dummy wafer will block the first wafer The vertical upward region of the pad so as not to hinder its wire bonding process; and a second semiconductor wafer fixed to the dummy wafer, the second semiconductor wafer is electrically connected to the structure for forming an electrical connection with the outside, wherein the The dummy wafer has a predetermined thickness sufficient to provide a clearance required for the first bonding wire between the first semiconductor wafer and the second semiconductor wafer. 2. The multi-chip package structure according to item 1 of the patent application scope, wherein the first semiconductor wafer and the second semiconductor wafer have approximately the same size. · 3. The multi-chip package structure according to item 丨 of the patent application scope, wherein the carrier device is a substrate. 4. The multi-chip package structure according to item 1 of the patent application scope, wherein the carrier POO-142, ptd Page 11 4543 1 β POO-142.ptd Page 12