TW453498U - High volume multi-layer stack memory - Google Patents

High volume multi-layer stack memory

Info

Publication number
TW453498U
TW453498U TW89218210U TW89218210U TW453498U TW 453498 U TW453498 U TW 453498U TW 89218210 U TW89218210 U TW 89218210U TW 89218210 U TW89218210 U TW 89218210U TW 453498 U TW453498 U TW 453498U
Authority
TW
Taiwan
Prior art keywords
layer stack
high volume
stack memory
volume multi
memory
Prior art date
Application number
TW89218210U
Other languages
Chinese (zh)
Inventor
Ming-Jou Jeng
Wen-Yan Chen
Jr-Sheng Pan
Fang-Jen Guo
Bo-Chin Chen
Original Assignee
Taiwan Micropaq Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Micropaq Corp filed Critical Taiwan Micropaq Corp
Priority to TW89218210U priority Critical patent/TW453498U/en
Publication of TW453498U publication Critical patent/TW453498U/en

Links

TW89218210U 1999-03-12 1999-03-12 High volume multi-layer stack memory TW453498U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW89218210U TW453498U (en) 1999-03-12 1999-03-12 High volume multi-layer stack memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW89218210U TW453498U (en) 1999-03-12 1999-03-12 High volume multi-layer stack memory

Publications (1)

Publication Number Publication Date
TW453498U true TW453498U (en) 2001-09-01

Family

ID=21674038

Family Applications (1)

Application Number Title Priority Date Filing Date
TW89218210U TW453498U (en) 1999-03-12 1999-03-12 High volume multi-layer stack memory

Country Status (1)

Country Link
TW (1) TW453498U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8305833B2 (en) 2002-04-10 2012-11-06 658868 N.B. Inc. Memory chip architecture having non-rectangular memory banks and method for arranging memory banks
CN111458621A (en) * 2019-01-21 2020-07-28 华邦电子股份有限公司 Integrated circuit and method for detecting multi-chip state thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8305833B2 (en) 2002-04-10 2012-11-06 658868 N.B. Inc. Memory chip architecture having non-rectangular memory banks and method for arranging memory banks
CN111458621A (en) * 2019-01-21 2020-07-28 华邦电子股份有限公司 Integrated circuit and method for detecting multi-chip state thereof
CN111458621B (en) * 2019-01-21 2022-03-01 华邦电子股份有限公司 Integrated circuit and method for detecting multi-chip state thereof

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Legal Events

Date Code Title Description
GD4K Issue of patent certificate for granted utility model filed before june 30, 2004
MM4K Annulment or lapse of a utility model due to non-payment of fees