4 b288 8 A7 __B7 五、發明説明（/ ) (_)發明頜域 本發明係揭露出一種避免中間介電層剝落之製程方 法，尤指一種避免中間介電層與複晶矽閘電極之間發生 剝離之方法。 (二)發明背景： 積體電路(IC ; Integrated Circuit)之傳統製程方法： 首先在晶格方位<1〇〇>的P型或N型半導體矽基板上， 利用熱氧化技術形成二氧化矽墊層(Pad Oxide)，厚度約 100至500埃之間；然後，利用低壓化學氣相沈積法 (LPCVD ; Low Pressure Chemical Vapor Deposition)沈積 一層厚約300〜1500埃左右的複晶矽在Si02墊層上，之 後，再利用LPCVD沈積一層厚約1000〜3000埃左右的 氮化矽層在複晶矽層上。接著，利用電漿触刻技術單向 性地(Anisotropically)制定所述二氧化砂墊層、複晶砂層 與氮化矽(SiN)複合結構的圖案。然後，將晶圓置於富 含氧氣的高溫環境中，以所述氮化矽作爲氧化保護罩 (Oxidation Mask)來形成厚約4500〜6500埃左右的場氧化 層(Field Oxide)，然後，利用熱磷酸溶液將SiN層去掉， 再利用乾蝕刻技術去掉複晶矽層，並以氫氟酸溶液將 Si02層去掉。 再次利用熱氧化技術生成厚約50〜300埃左右的閘 極氧化層，並利用LPCVD沈積一層閘極複晶矽層，以 傳統光罩蝕刻技術界定複晶矽閘電極，之後，以8卩2等 N+/P+型離子佈植到所述第一複晶矽閘電極，其植入能 本紙張尺度適用中國國家標準（CNS } A4規格（210X297公釐） -----------^------1T------^ (請先閱讀背面乏注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印裝 經濟部中央標準局員工消費合作社印製 4 5 2 8 8 8 A7 B7 五、發明説明（厶） 量爲60〜80 KeV，其劑量介於2E15到5E15原子/每平 方公分之間。 接著沈積一層中間介電層（ILD ; Inter Level Dielectric)，再利用微影技術與電漿蝕刻技術蝕去部份 中間介電層以形成接觸窗(Contact Hole)。接著，再沈積 一層鋁合金爲主的金屬，再利用微影技術與電漿蝕刻技 術飩去所述部份的鋁合金，以形成第一金屬連線，該第 一金屬連線跨過接觸窗與金氧半場效電晶體之源極/汲 極(Source/Drain)作電性接觸。 然後*沈積一層中間金屬介電層(IMD ; Inter Metal Dielectric)，並進行平坦化製程(Planarization prceass)以 改善陡峭的地形地勢(Severe Topography);接著，利用 微影技術與電漿蝕刻技術去除部份中間金屬介電眉以彩 成介眉孔(Via Hole)，介層孔終止於第一金屬連線表 面。接著，形成一層以鋁合金爲主的金屬，再利用微影 技術與電漿蝕刻技術蝕去部份鋁合金以形成第二層金屦 連線，跨過介屑孔與其第一金屬連線或源極/汲楹作電 性接觸，積體電路之製造，於焉完成。 但，豐量的F_型離子佈植到所述第一複晶矽閘極 內，以致於後續沈積一屑中間介電層(ILD)覆蓋在第一 複晶矽閘極上時，將會因爲含豐量的F_離子之複晶矽閘 電極在後纘沈積ILD過程時遇熱而排放氟氣，使得複晶 矽閘電極表面起泡泡狀，造成該複晶矽閘電極與ILD之 間有剝離現象發生；若該現象不解決，則因排氣而造 I---------^------、訂------0 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） 經濟部中央標隼局員工消费合作社印製 4 5 2 8 8 λ? 五、發明説明（）） 成複晶矽閘電極產生空洞，將會降低積體罨路之良率 (Yield) 〇 (三)發明的簡單說明： 本發明的主要目的在於提供一種避免中間介電層 (ILD ; Inter Layer Dielectric)與複晶砂閘電極之間發生剝 離之技術。 本發明之主要方法如下：首先，在矽半導體基板上 形成隔離電性活動區(Active Ares)所需要的場氧化層 (Field Oxide);利用LPCVD方法沈積一閘極複晶矽層， 應用傳統光罩蝕刻技術界定複晶矽眉以形成複晶矽閘電 極圖案。接下來，利用熱氧化技術，在該複晶矽閛電極 上形成一厚約50埃至150埃左右的犧牲氧化層，之後， 再行以BF22P+型離子對其複晶矽閘電楹進行離子佈 植，其BF2之植入能量爲60〜80 KeV，佈植劑量爲2E15 〜5E15原子/平方公分；然後，利用乾蝕刻(Dry Etching)或濕化學軸刻(Wet Chemical Etching)技術去除該 犧牲氧化層，由於所移走的银牲氧化層將帶走部份 BF2，則將避免複晶矽閘電極含過於大量的F_離子，使 得在後續ILD製程步驟中遇熱產生排氣現象；接下來， 沈積一層中間介電層(ILD)，並利用微影技術與電漿蝕 刻技術蝕去所述部份的ILD以形成接觸窗；然後，沈積 一眉鋁合金爲主的金屬，並利用微影蝕刻技術製作形成 第一金屬連線，該第一金屬連線跨過接觸窗與金氧半場 效電晶體之源極/汲極作電性接觸。 I 1 批衣 i —訂 I I I 線 (請先聞讀背而之注意事項再填窍本買) 本紙浪尺度適用中國國家標準i CNS ) A4规格（2丨〇'乂297公釐） 4 5284 b288 8 A7 __B7 V. Description of the invention (/) (_) Invention of the jaw field The present invention discloses a method for avoiding the peeling of the intermediate dielectric layer, especially a method for avoiding between the intermediate dielectric layer and the polycrystalline silicon gate electrode. How peeling occurs. (II) Background of the Invention: Traditional manufacturing method of integrated circuit (IC; Integrated Circuit): Firstly, on a P-type or N-type semiconductor silicon substrate with a lattice orientation < 100 >, a thermal oxidation technique is used to form a dioxide. Pad Oxide with a thickness of about 100 to 500 angstroms; then, a low-pressure chemical vapor deposition method (LPCVD; Low Pressure Chemical Vapor Deposition) is used to deposit a layer of polycrystalline silicon with a thickness of about 300 to 1500 angstroms in Si02 After that, a silicon nitride layer having a thickness of about 1000 to 3000 angstroms is deposited on the polycrystalline silicon layer by LPCVD. Next, a pattern of the composite structure of the sand dioxide underlayer, the polycrystalline sand layer, and silicon nitride (SiN) is unidirectionally (Anisotropically) prepared using a plasma etching technique. Then, the wafer is placed in a high-temperature environment rich in oxygen, and the silicon nitride is used as an oxidation mask to form a field oxide layer having a thickness of about 4500 to 6500 angstroms. The SiN layer is removed by a hot phosphoric acid solution, and then the polycrystalline silicon layer is removed by a dry etching technique, and the Si02 layer is removed by a hydrofluoric acid solution. A gate oxide layer with a thickness of about 50 to 300 angstroms was again generated by thermal oxidation technology, and a gate polycrystalline silicon layer was deposited by LPCVD. The polycrystalline silicon gate electrode was defined by the traditional photomask etching technique. The N + / P + type ions are implanted to the first compound silicon gate electrode, and the implantation energy of the paper is applicable to the Chinese national standard (CNS) A4 specification (210X297 mm) ---------- -^ ------ 1T ------ ^ (Please read the notes on the back before filling out this page) Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 4 5 2 8 8 8 A7 B7 V. Description of the invention (厶) The amount is 60 ~ 80 KeV, and the dose is between 2E15 and 5E15 atoms / cm². Next, an intermediate dielectric layer (ILD; Inter Level Dielectric) is deposited. Then, lithography and plasma etching are used to etch away part of the intermediate dielectric layer to form a contact hole. Next, a layer of aluminum-based metal is deposited, and then photolithography and plasma etching are used. Removing the part of the aluminum alloy to form a first metal connection, the first gold The line crosses the contact window to make electrical contact with the source / drain of the metal-oxide-semiconductor field-effect transistor. Then * deposits an intermediate metal dielectric layer (IMD; Inter Metal Dielectric) and planarizes it Planarization prceass to improve Severe Topography; then, using lithography and plasma etching technology to remove some of the intermediate metal dielectric eyebrows to form Via holes, and terminate the interlayer holes On the surface of the first metal connection. Next, a layer of metal mainly composed of aluminum alloy is formed, and then a portion of the aluminum alloy is etched by lithography technology and plasma etching technology to form a second layer of gold-alloy connection across the chip The hole makes electrical contact with its first metal connection or source / drain, and the fabrication of the integrated circuit is completed in Y. However, a large amount of F_-type ions are implanted into the first complex silicon gate. , So that when the subsequent deposition of an interstitial dielectric layer (ILD) covers the first polycrystalline silicon gate, the polycrystalline silicon gate electrode containing a large amount of F_ ions will encounter heat during the ILD deposition process The emission of fluorine gas makes the surface of the polycrystalline silicon gate electrode bubble. As a result, a peeling phenomenon occurs between the polycrystalline silicon gate electrode and the ILD. If the phenomenon is not resolved, it will be caused by exhaust. I --------- ^ ------, order --- --- 0 (Please read the notes on the back before filling out this page) This paper size is applicable to Chinese National Standard (CNS) A4 (210 X 297 mm) Printed by the Staff Consumer Cooperative of the Central Bureau of Standards, Ministry of Economic Affairs 4 5 2 8 8 λ? V. Description of the invention ()) The generation of voids in the compound silicon gate electrode will reduce the yield of the integrated circuit (Yield). ○ (3) Brief description of the invention: The main purpose of the present invention is to provide a The technology to avoid the peeling between the interlayer dielectric (ILD; Inter Layer Dielectric) and the composite crystal gate electrode. The main method of the present invention is as follows: First, a field oxide layer required to isolate the electrically active regions (Active Ares) is formed on a silicon semiconductor substrate; a gate polycrystalline silicon layer is deposited by using the LPCVD method, and conventional light is applied. The mask etching technique defines a polycrystalline silicon eyebrow to form a polycrystalline silicon gate electrode pattern. Next, a sacrificial oxide layer with a thickness of about 50 Angstroms to 150 Angstroms is formed on the polycrystalline silicon hafnium electrode by using a thermal oxidation technology, and then the polycrystalline silicon gate electrode is ion-distributed with BF22P + type ions The implantation energy of the BF2 is 60 to 80 KeV, and the implantation dose is 2E15 to 5E15 atoms / cm 2. Then, the sacrificial oxidation is removed by using dry etching or wet chemical etching. Layer, because the removed silver oxide oxide layer will take away a part of BF2, it will prevent the polycrystalline silicon gate electrode from containing an excessive amount of F_ ions, so that in the subsequent ILD process steps, heat will generate an exhaust phenomenon; next , Depositing an intermediate dielectric layer (ILD), and using lithography and plasma etching to remove the ILD to form a contact window; then, depositing an aluminum-based metal and using lithography An etching technique is used to form a first metal connection, and the first metal connection makes electrical contact with the source / drain of the metal-oxygen half field-effect transistor across the contact window. I 1 batch of clothes i — order I I I line (please read the precautions and fill in the tips before buying) The paper scale is applicable to the Chinese national standard i CNS) A4 specification (2 丨 〇'297mm) 4 528
經濟部中央標準局員工消費合作社印製 五、發明説明（^) (四) 圖示的簡單說明： 圔1係爲本發明之一種避免中間介電層剝落之製程方法 剖面圖。 (五) 發明的詳細說明： 首先，請參考圖1A，如同傳統製程，首先我們提供 一P型矽基板51，應用熱氧化技術在其矽基板51形成厚 約100〜500埃的二氧化矽Si02墊層53(pad oxide);然後 利用LPCVD沈積一層厚約300〜1500埃之複晶矽層55在 Si02 53墊屑上，之後，再利用LPCVD沈積一厚約1000 〜3000埃左右的氮化矽屑57在複晶矽層55上。 請參考圖1B，利用電漿蝕刻技術非等向性 (anisotropic)地制定所述二氧化矽墊層53、複晶矽層 55與氮化矽屑57之複合結構圖案。 請參考圖1C，將晶片置於富含氧氣的高溫環境中， 以所述氮化矽57作爲氧化保護罩，來形成厚約4500〜 6500埃左右的場氧化層(Field Oxide)59 〇 請參考圖ID，利用熱磷酸溶液將SiN 57層去掉，再 利用乾蝕刻去掉複晶矽層55，並以氫氟酸溶液將Si02 53 墊層去掉。 請參考圖1E，利用低壓化學氣相沈積法(LPCVD ; Low Pressure Chemical Vapor Deposition)沈積一層厚約 300〜1500埃左右之複晶矽層，並以傳統微影蝕刻技術 界定該複晶矽層圖案，以形成複晶矽閘電極61。 . .i I I ~1 [ I 訂 I I . ~^線 <韩先吼讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準{ CNS ) A4現格（210X297公釐） 經濟部中央標隼局員工消費合作社印掣 4528 五、發明説明（y) 請參考圖IF，利用熱氧化技術，在其矽基板51、場 氧化層59和複晶矽閘電極61上形成一厚約50〜150埃左 右的犧牲氧化層(Sacrificial Oxidation Layer)63 ’該播牲 氧化層63係在其溫度爲850°C〜920°C之高溫環境中形 成。 請參考圊1G，應用光罩65遮住基板51上欲形成N通 道MOS電晶體的其餘部份，進行P+型離子67植入，使用 之植入物種爲劑量爲2E15〜5E15原子/平方公分，能 量爲60〜80 KeV之二氟化硼(BF2)離子，以形成P型離子 接觸窗區之離子植入區69，其上述之離子植入區69即爲 M0S電晶體之源/汲極。 請參考圔1H，利用乾軸刻(Dry Etching)或濕化學蝕 刻(Wet Chemical Etching)技術去除所述犧牲氧化層63。 請參考圖II，在場氧化眉與元件區域上，以化學氣 相沈積法（CVD ; Chemical Vapor Deposition)形成一中間 介電層(ILD ; Inter Layer Dielectric)71，通常該ILD爲沒 有摻雜離子之二氣化矽(NSG ; Neutral Silicate Glass)絕 緣眉，其上再以CVD法沈積一具有流整作用之硼磷矽酸 鹽玻璃層73(BPSG ; Boronphosphosilicate Glass)。 請參考圖1J，應用一光罩，以傳統光罩蝕刻技術， 制定出圖1J之接觸窗(Contact Hole)75圖案，未來，第一 層金屬連線將透過該接觸窗75跟金氧半場效電晶體之源 極/汲極區域作電性接觸。 -----------^------ΐτ------Ί0 (請先閱讀背而之注意事項再填本頁) 本紙張尺度適用中國國家標準（CNS ) Α4規格（2ΙΟΧ297公釐）Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (^) (4) Brief description of the diagram: ： 1 is a cross-sectional view of a manufacturing method of the invention to avoid the peeling of the intermediate dielectric layer. (5) Detailed description of the invention: First, please refer to FIG. 1A. As in the traditional process, first we provide a P-type silicon substrate 51, and apply thermal oxidation technology to form silicon dioxide Si02 with a thickness of about 100 to 500 angstroms on the silicon substrate 51. Pad layer 53 (pad oxide); then LPCVD is used to deposit a layer of polycrystalline silicon layer 55 with a thickness of about 300 to 1500 angstroms on Si02 53 pads, and then, LPCVD is used to deposit a thickness of about 1,000 to 3,000 angstroms of silicon nitride Chips 57 are on the polycrystalline silicon layer 55. Referring to FIG. 1B, a composite structure pattern of the silicon dioxide pad layer 53, the polycrystalline silicon layer 55, and the silicon nitride chip 57 is formulated anisotropically using a plasma etching technique. Please refer to FIG. 1C, the wafer is placed in a high temperature environment rich in oxygen, and the silicon nitride 57 is used as an oxidation protection cover to form a field oxide layer 59 having a thickness of about 4500 to 6500 angstroms. Figure ID, the SiN 57 layer is removed by using a hot phosphoric acid solution, the polycrystalline silicon layer 55 is removed by dry etching, and the Si02 53 underlayer is removed by a hydrofluoric acid solution. Referring to FIG. 1E, a low-pressure chemical vapor deposition method (LPCVD; Low Pressure Chemical Vapor Deposition) is used to deposit a polycrystalline silicon layer having a thickness of about 300 to 1500 angstroms, and the pattern of the polycrystalline silicon layer is defined by a conventional lithographic etching technique. To form a polycrystalline silicon gate electrode 61. . .i II ~ 1 [I order II. ~ ^ line & read the notes on the back of Han Xianhou and fill out this page) This paper size applies the Chinese national standard {CNS) A4 format (210X297 mm) Central Ministry of Economic Affairs Standards Bureau employee consumer cooperative stamp 4528 5. Description of the invention (y) Please refer to Figure IF, using thermal oxidation technology, to form a thickness of about 50 ~ on its silicon substrate 51, field oxide layer 59 and polycrystalline silicon gate electrode 61 Sacrificial Oxidation Layer 63 of about 150 angstroms' The sowing oxide layer 63 is formed in a high temperature environment with a temperature of 850 ° C ~ 920 ° C. Please refer to 圊 1G. Use the mask 65 to cover the rest of the N-channel MOS transistor on the substrate 51, and perform P + ion 67 implantation. The implantation species is 2E15 ~ 5E15 atoms / cm2. Boron difluoride (BF2) ions having an energy of 60 to 80 KeV to form an ion implantation region 69 of the P-type ion contact window region, and the above-mentioned ion implantation region 69 is the source / drain of the MOS transistor. Referring to 圔 1H, the dry oxide etching (Wet Chemical Etching) or wet chemical etching (Wet Chemical Etching) is used to remove the sacrificial oxide layer 63. Please refer to FIG. II. An intermediate dielectric layer (ILD) 71 is formed by chemical vapor deposition (CVD; Chemical Vapor Deposition) on the field oxide eyebrow and the device area. Generally, the ILD is not doped with ions. The second is an insulated eyebrow of silicon gas (NSG; Neutral Silicate Glass), and a borosilicate glass layer 73 (BPSG; Boronphosphosilicate Glass) having a leveling effect is deposited by the CVD method. Please refer to Figure 1J. Apply a photomask and use the traditional mask etching technology to develop the contact hole 75 pattern of Figure 1J. In the future, the first layer of metal wiring will pass through the contact window 75 and the metal-oxygen half field effect. The source / drain regions of the transistor are in electrical contact. ----------- ^ ------ ΐτ ------ Ί0 (Please read the precautions on the back before filling this page) The paper size applies to the Chinese National Standard (CNS) Α4 specification (2ΙΟχ297 mm)