五、發明說明（1) 【發明領域】 本發明是有關半導體元件的隔離製程，且特別是有關 於一種具側邊延伸結構之元件隔離物的製造方法。 【發明背景】 近年來，隨著半導體積體電路製造技術的發展，晶片 中所含元件的數量不斷增加，元件的尺寸也因積集度的提 昇而不斷地縮小，生產線上使用的線路寬度已進入深次微 米甚或更細微尺寸的範圍。而無論元件尺寸如何縮小化， 在晶片中各個元件之間仍必須有適當地絕緣或隔離，方可 得到良好的元件性質。這方面的技術一般稱為元件隔離技 術（device isolation technology)，其主要目的係在各 元件之間形成隔離物，並且在轉保良好隔離效果的情況 下’儘量縮小隔離物的區域’以空出更多的晶片面積來容 納更多的元件。 在各種元件隔離技術中’局部矽氧化方法（L〇c〇s)和 淺溝槽隔離區（shallow trench isolation ;STI)製程是 最常被採用的兩種技術，尤其後者具有隔離區域小和完成 後仍保持基底平坦性等優點，更是近來頗受重視的半導體 製造技術。傳統上’係先利用化學氣相沈積（c)程序， 形成一介電層以填入基底的溝槽中’之後再以化學性機械 研磨程序（CMP)去除表面多餘的介電層，以完成溝槽隔離 區製程。 以下將配合第1〜6圖，就習知一種製作淺溝渠隔離的V. Description of the Invention (1) [Field of the Invention] The present invention relates to an isolation process for a semiconductor device, and more particularly to a method for manufacturing a device spacer with a side extension structure. [Background of the Invention] In recent years, with the development of semiconductor integrated circuit manufacturing technology, the number of components contained in wafers has continued to increase, and the size of components has been continuously reduced due to the increase in the degree of accumulation. Enter the range of deep sub-micron or even finer size. Regardless of how the component size is reduced, each component in the wafer must still be properly insulated or isolated to obtain good component properties. This technology is generally referred to as device isolation technology. Its main purpose is to form a spacer between components, and to 'narrow the area of the spacer' as much as possible in the case of good isolation. More chip area to accommodate more components. Among the various element isolation technologies, the 'local silicon oxidation method (LoCos) and shallow trench isolation (STI) process are the two most commonly used technologies, especially the latter has a small isolation area and complete Later, the advantages of maintaining the flatness of the substrate and the like are even more recent semiconductor manufacturing technologies. Traditionally, 'the chemical vapor deposition (c) process is used to form a dielectric layer to fill the trenches in the substrate', and then the chemical dielectric polishing process (CMP) is used to remove the excess dielectric layer on the surface to complete the process. Trench isolation process. The following will cooperate with Figures 1 to 6 to learn a method for making shallow trench isolation.
“51398 五、發明說明（2) ^ 乍、，一說明’以討論現有製程所遭遇的問題。請參照第 圖’首先在一半導體基底10表面上，依序形成一墊氧化 廣1 2和氮化石夕層1 4。其中氮化矽層1 2將在後續定義溝槽 夺作為硬式罩幕。然後’在氮化矽層14上形成一光阻圖 -I λ ^ 路出欲形成元件隔離區的部分。請參照第2圖，利 用光阻圖案1 6當作罩幕，依序蝕刻氮化矽層1 4 '墊氧化層 12、2半導體基底10，以形成溝槽17。 、 請參照第3圖’去除光阻圖案1 6後，以化學氣相沈積 法(CVD)形成一氡化層18覆蓋在氮化矽層丨4上，並完全填 '籌槽1 7靖參照第4圖’施行一化學性機械研磨（c Μ Ρ )程 序’去除氛化層18高出氮化矽層14表面的部分以形成一平 坦$表面構造’並藉此使留在溝槽内的部分形成一元件隔 離區18Α接著，如第5圖所示，將氮化石夕層14與塾氧化層 1 2去除，以定義溝槽隔離區丨8Α。最後，依序施代一犧牲 氧，序（sacr i f i c i a 1 ox i dat i on pr oce ss )與一去除程 序以完成如第6圖所示之溝槽隔離區18B。 .然而’根據上述習知的溝槽隔離方法，由於隔離氧化 物與犧牲氧化層的蚀刻性質相近，因此當以蝕刻液浸泡 (dip)去除犧牲氧化層時，不可避免地也會侵蝕到溝槽隔 離，區:8B’因此隔離氧化物的邊緣會形成如第6圖所示的輪· 磨A 亦即’元件隔離區在邊緣部分的輪廓是尖銳的， 因此當形成閘氧化層日夺，在此邊界部分會變得比較薄，造 成電場過度集中。此外，亦會累積較大的應力，導致漏電 流的產生或影響主動區元件的特性。"51398 V. Description of the invention (2) ^ At first, a description 'to discuss the problems encountered in the existing process. Please refer to the figure' First, a pad of oxide 12 and nitrogen are sequentially formed on the surface of a semiconductor substrate 10 Fossil layer 1 4. The silicon nitride layer 12 will be used as a hard mask in the subsequent definition of the trench. Then, a photoresist pattern is formed on the silicon nitride layer 14 -I λ ^ The path is to form an element isolation region Please refer to FIG. 2, using the photoresist pattern 16 as a mask, and sequentially etch the silicon nitride layer 1 4 ′, the pad oxide layer 12, and the semiconductor substrate 10 to form a trench 17. Figure 3 'After removing the photoresist pattern 16, a halide layer 18 is formed by chemical vapor deposition (CVD) to cover the silicon nitride layer 4, and it is completely filled with the' chip trench 1 7. Refer to Figure 4 ' A chemical mechanical polishing (c MP) procedure is performed to 'remove the portion of the atmosphere layer 18 above the surface of the silicon nitride layer 14 to form a flat surface structure' and thereby form a component in the portion remaining in the trench Isolation area 18A Next, as shown in FIG. 5, the nitride nitride layer 14 and the hafnium oxide layer 12 are removed to define a trench isolation. Region 丨 8Α. Finally, a sacrificial oxygen, sacrificia 1 ox i dat i on procce ss and a removal procedure are sequentially performed to complete the trench isolation region 18B as shown in Fig. 6. However, ' According to the above-mentioned conventional trench isolation method, since the etching properties of the isolation oxide and the sacrificial oxide layer are similar, when the sacrificial oxide layer is removed by dipping the etching solution, the trench isolation will inevitably be eroded. : 8B 'Therefore, the edge of the isolation oxide will form a wheel as shown in Figure 6. Grinding A, that is, the contour of the element isolation region at the edge is sharp, so when the gate oxide layer is formed, it is at this boundary portion. It will become thinner, resulting in excessive concentration of the electric field. In addition, it will also accumulate large stresses, leading to the generation of leakage current or affecting the characteristics of the active area components.
451398 五、發明說明（3) 因此’為了使淺溝槽隔離技術的應用更綠於完1，實 有必要針對上述問題謀求改善之道。 '兀。 【發明概述】 有鑑於此’本發明的主要目的就是提供一種溝槽隔離 區的改良製程’其可形成具有側邊延伸結構之溝槽隔離 物’以降低溝槽邊緣產生缺陷的機會。 曰 為，上述目的，本發明提供一種形成溝槽隔離物之方 法，1·先在基底上形成一罩幕層（例如氮化 :光阻層，其中光阻層具有一用來定義溝槽二複二卜 後，先利用等向性的蝕刻（is〇tr〇pic etch) :出-個擴大的開口，再利用定向性的蝴二 etch) 光阻層既有的開口在基底中定義出溝槽。去除光 Ϊ層点將：：緣材料填入溝槽與罩幕層中擴大後的開 便形成一具有侧邊延伸結構的溝槽隔離物。 根據本發明一較佳實施例，其主要 形成一塾氧化層及-罩 卓綦層上形成一光阻層，直且古笙 ^f -σ # / 7 ^A#; 之第-鬥ΓΤ I f地蝕刻罩幕層，以形成較寬 -第：二第—開口下方：⑷以光阻層為罩幕， 槽(口二二地蚀刻墊氧化層與半導體基底，以形成 上述第二開e 口/以开阻/ 1 以及（f)將一絕緣層填入溝槽與 覆蓋在丄圍的基溝槽隔離物，其具有-延伸部位451398 V. Description of the invention (3) Therefore, in order to make the application of shallow trench isolation technology greener than complete, 1 it is necessary to seek ways to improve the above problems. 'U. [Summary of the Invention] In view of this, the main purpose of the present invention is to provide an improved process for trench isolation regions, which can form trench spacers with side extension structures to reduce the chance of defects at the edges of the trenches. That is, for the above purpose, the present invention provides a method for forming a trench spacer. 1. A mask layer (such as a nitride: a photoresist layer) is first formed on a substrate, wherein the photoresist layer has a After doubling, first use isotropic etching (is〇tr〇pic etch): to create an enlarged opening, and then use the directional butterfly two etch) Existing openings in the photoresist layer define a groove in the substrate groove. Removal of the light layer points: The edge material is filled into the trench and the mask layer to expand the opening to form a trench spacer with a side extension structure. According to a preferred embodiment of the present invention, it mainly forms an oxide layer and a photoresist layer on the cover layer, and is straight and ancient ^ f -σ # / 7 ^ A #; The mask layer is etched to form a wider-second: second-below the opening: ⑷ the photoresist layer is used as the mask, and the groove (the second layer etches the pad oxide layer and the semiconductor substrate to form the second open e-port / Open resistance / 1 and (f) fill an trench with an insulating layer and a base trench spacer covering the perimeter, which has an -extending portion
4513 9 8 五、發明說明（4) 根據上述，本發明所形成的溝槽隔離物除了會填滿溝 槽之外，也會延伸覆蓋住溝槽周圍的基底，因此可提供適 當的保護’避免溝槽邊緣受到侵蚀而造成缺陷。 為讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂’下文特舉出較佳實施例，炎配合所附圖式，作詳 細說明如下： 【圖式之簡單說明】 第卜6圖為一系列剖面圖，用以説明習知製作溝槽隔 離物的流程。 第7〜1 3圖為一系列剖面圖，用以說明本發明一較佳實 施例製作溝槽隔離物的流程。 【符號說明】 ίο、1〇〇〜半導體基底； 12、102〜墊氧化層； 14、1〇4〜罩幕層； 1 6、1 0 6〜光阻層； 17、109〜溝槽 1 8、1 〇 8〜絕緣層； 1 〇 7〜開口。 【實施例】 請參照第7圖至第1 3圖 製作溝槽隔離區的流程。首 ，其說明本發明一較佳實施例 先請參照第7圖，在一半導體4513 9 8 V. Description of the invention (4) According to the above, the trench spacer formed by the present invention will not only fill the trench, but also extend to cover the substrate around the trench, so it can provide appropriate protection. Erosion of the trench edges causes defects. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the preferred embodiments are described below, and the accompanying drawings are described in detail below: [Brief description of the drawings] Figure 6 is a series of cross-sectional views to illustrate the conventional process for making trench spacers. Figures 7 to 13 are a series of cross-sectional views for explaining the process of manufacturing a trench spacer according to a preferred embodiment of the present invention. [Symbol description] Ιο, 100 ~ semiconductor substrate; 12, 102 ~ pad oxide layer; 14, 104 ~ mask layer; 16, 106 ~ photoresist layer; 17, 109 ~ trench 1 8 １００〜〜 内 层层 ； 〇07〜 开口。 [Example] Please refer to FIG. 7 to FIG. 13 for the process of fabricating the trench isolation region. First, it illustrates a preferred embodiment of the present invention. Referring to FIG. 7, a semiconductor
^51398 五、發明說明（5) 基底，像是矽基底100的表面上，覆蓋—墊氧化層（pad ox 1 de) 1 0 2和一罩幕層i 〇 4。例如，先以化學氣相沈積程序 丄CVD)或熱^^成長程序（thermal 〇xidat 形成一厚度 介於50〜200 ，然彳ϋ墊氧化面上]~ 以CVD法沈積一厚度介於5〇〇~2〇〇〇 Α的複晶矽或氮化矽層 104。墊氧化層1 〇2與罩幕層1〇4的功用與習知技術相同： 墊氧化層102乃是用以消除罩幕層丨〇4與基底丨〇〇之間的應 力，而罩幕層104是用來作為蝕刻淺溝渠時的罩幕，另外 也可作為化學機械研磨（CMp)或蝕刻的終止層（st〇p layer)。 繼續參照第7一周，塗佈一光阻層丨〇6在罩幕層丨〇4上， 並以微影成像程序形成一開口丨〇7 ,用以定義溝槽並露出 底下部分的罩幕層104。接下來，透過開口 1〇7對底下的 幕層104進行等向性的蝕刻（is〇tr〇pic etch)。如第8圖所 =拔在等向性的蝕刻中，由於直向（veriical)的蝕刻速率 與橫向（laterai)的蝕刻速率相當，因此在開口 1〇7底下會 造成如圖中所示的底切（undercut)現象。易言之’由於橫 向蝕刻的結果，蝕刻後的罩幕層1〇4A在開口 1〇7下方形成 了一個擴大的開口，其寬度”大於開口1〇7的寬度们（此寬 2為溝槽的寬度）。根據本發明，上述蝕刻較佳可利用 的電漿银刻達成’更佳者，上述等向性的敍刻與後 縯=向性的蝕刻可在同一蝕刻機台中in_situ進行，以簡 =j程併提高產能。舉例而言，當罩幕層為氮化 向性的電槳蚀刻可利用含氣氣體或含氟氣體為餘刻源；複^ 51398 5. Description of the invention (5) The substrate, such as the surface of the silicon substrate 100, is covered with a pad oxide layer (pad ox 1 de) 102 and a cover layer i 04. For example, a chemical vapor deposition process (CVD) or a thermal growth process (thermal oxidat) is firstly used to form a thickness between 50 and 200, but the pad oxide surface is then deposited by a CVD method with a thickness between 50 and 〇. 〇 ~ 2〇〇〇 polycrystalline silicon or silicon nitride layer 104. The function of the pad oxide layer 10 and the mask layer 104 is the same as the conventional technology: the pad oxide layer 102 is used to eliminate the mask The stress between the layer 丨 〇4 and the substrate 丨 〇〇, and the mask layer 104 is used as a mask when etching shallow trenches, and can also be used as a chemical mechanical polishing (CMp) or an etching stop layer (st〇p Continuing to refer to week 7, a photoresist layer is applied on the mask layer, and an opening is formed by the lithography imaging program, which is used to define the groove and expose the bottom part. Cover the curtain layer 104. Next, the underlying curtain layer 104 is isotropically etched through the opening 107. As shown in FIG. 8 = in the isotropic etching, because The vertical (veriical) etch rate is comparable to the lateral (laterai) etch rate, so it will cause The undercut phenomenon. In other words, 'as a result of the lateral etching, the etched mask layer 104A forms an enlarged opening below the opening 107, and its width is greater than the width of the opening 107 ( This width 2 is the width of the trench.) According to the present invention, the above-mentioned etching is preferably achieved by the plasma silver engraving, which is better, and the above-mentioned isotropic etch and post-play = directional etching can be performed in the same etching. The in_situ process is performed in the machine to simplify the process and increase the production capacity. For example, when the mask layer is nitrided, the electric paddle etching can use a gas or a fluorine-containing gas as the remaining source;
^5)398 五、發明說明（6) 晶矽的等向性的電漿蝕刻則可利用含氣氣體如c i 、cc丨或 HBr等為蝕刻源。 請參照第9圖’接下來，以光阻層1 〇 6為軍幕，沿既有 的開口 107對底下的墊氧化層102與矽基底1〇〇進行定向性 的蝕刻（directi on al etch)，以形成隔離用的溝槽1〇9。 一般而言’溝槽109之深度可介於3 500 A和5000 A之間。 此步驟可利用習知的電裝触刻，例如反應性離子钱刻法進 行。钮刻基底1 0 0時，例如可使用C 12 + 02作為姓刻源，在下 列條件下進行姓刻：壓力4〜8 m T 〇 r r、C 12氣體流量5 〇〜8 0 seem、〇2氣體流量5〜10 seem。在本發明的較佳實施例 中’第9圖所繪示的定向性蝕刻與第8圖的等向性蝕刻係在 同一乾触刻機台in-situ進行。 請參照第1 0圖，以適當方式將光阻層丨〇 6去除後，沈 積一絕緣層1 0 8，例如氧化矽，於半導體基底表面上，並 填滿溝槽1 0 9與溝槽上方經擴大後的開口。此絕緣填充物 1 0 8可利用此技藝人士所熟知的方法來製作，這些方法包 括：以各種化學氣相沈積（CV1))程序所沈積之氧化層，例 如是常壓化學氣相沈積（APCVD)、次常壓化學氣相沈積 (SACVD)、低壓化學氣相沈積（lpcvD)、或高密度電漿化學 氣相沈積（HDPCVD)程序等；或是由旋轉塗覆玻璃（S0G)技 術所形成者。此外，在沈積絕緣層丨〇 8之前，通常可藉由 熱氧化法在溝槽109的底部與側壁形成一層厚度約1〇〇〜300 A的襯墊氧化層（1 in ing oxide)來確保Si/Si〇2的界面品 質。 451398 五 '發明說明（7) 請參照第1 2圖，接著以回蝕刻或化學機械研磨（CMP ) 程序，去除絕緣層108高出罩幕層104A表面的部分，以形 成一平坦的表面構造，而使留在溝槽109内的部分形成一 元件隔離區1 〇 8 A。在進行絕緣層1 0 8的平坦化時，基底上 的罩幕層104A可作為適當的蝕刻終止層或研磨終止層。 請參 去除，露 石夕時，可 則使用乾 除後，便 形的剖面 108A具有 即使在去 緣的主動 能性，確 雖然 限定本發 和範圍内 範圍當視 照第1 3 出底下 使用磷 银刻較 得到如 結構。 側邊延 除墊氧 區也不 保了元 本發明 明，任 ，當可 後附之 m 的墊氧 酸溶液 佳。最 第13圖 如圖中 伸結構 化層或 會曝露 件隔離 已以較 何熟習 作各種 申請專 罩幕層1 04A以濕蝕刻或乾蝕刻方式 化層102A。例如，當罩幕層為氮化 將之去除；當罩幕層為複晶矽時， 後，以適當方式將墊氧化層102A去 所示的溝槽隔離區108A，其具有T 所示’由於本發明的溝槽隔離區 覆蓋住溝槽109周圍的基底表面， 犧牲氧化層時，這些位於隔離區邊 出來’因此降低邊角出現缺陷的可 的品質 佳實施例揭露如上，然其並非用以 此技藝者，在不脫離本發明之精神 之更動與潤飾，因此本發明之保護 利範圍所界定者為準。^ 5) 398 5. Description of the invention (6) Isotropic plasma etching of crystalline silicon can use gaseous gases such as c i, cc 丨 or HBr as the etching source. Please refer to FIG. 9 'Next, with the photoresist layer 106 as a military curtain, the underlying pad oxide layer 102 and the silicon substrate 100 are directionally etched along the existing opening 107 (directi on al etch) To form an isolation trench 109. Generally speaking, the depth of the 'groove 109 may be between 3 500 A and 5000 A. This step can be performed using a conventional electric device engraving, such as a reactive ion coin engraving method. When the button base is 100, for example, C 12 + 02 can be used as the source of the last name, and the last name is engraved under the following conditions: pressure 4 ~ 8 m T 〇rr, C 12 gas flow rate 5 〇 ~ 8 0 seem, 〇2 The gas flow is 5 ~ 10 seem. In the preferred embodiment of the present invention, the directional etching shown in Fig. 9 and the isotropic etching shown in Fig. 8 are performed in the same dry-contact engraving machine in-situ. Referring to FIG. 10, after the photoresist layer is removed in an appropriate manner, an insulating layer 108, such as silicon oxide, is deposited on the surface of the semiconductor substrate and filled with the trenches 109 and above the trenches. Enlarged opening. The insulating filler 108 can be produced by methods well known to those skilled in the art, including: an oxide layer deposited by various chemical vapor deposition (CV1) procedures, such as atmospheric pressure chemical vapor deposition (APCVD) ), Sub-atmospheric pressure chemical vapor deposition (SACVD), low pressure chemical vapor deposition (lpcvD), or high-density plasma chemical vapor deposition (HDPCVD) procedures, etc .; or formed by spin-on-glass (S0G) technology By. In addition, prior to the deposition of the insulating layer, it is common to form a pad oxide layer (1 in ing oxide) with a thickness of about 100 to 300 A on the bottom and sidewalls of the trench 109 by a thermal oxidation method to ensure Si / Si〇2 interface quality. 451398 Five 'invention description (7) Please refer to FIG. 12 and then use etch-back or chemical mechanical polishing (CMP) procedures to remove the portion of the insulating layer 108 above the surface of the mask layer 104A to form a flat surface structure. An element isolation region 108 A is formed in a portion remaining in the trench 109. When planarizing the insulating layer 108, the mask layer 104A on the substrate can be used as an appropriate etching stop layer or a polishing stop layer. Please refer to the removal. When the stone is exposed, you can use the dry section. After the removal of the section 108A, it has the active ability to remove the edge. Silver engraving is more structure-like. The lateral extension of the oxygen-removing zone is not guaranteed. The present invention states that any oxygen-repellent solution of m is better when attached to it. Figure 13 shows the structured layer may be exposed as shown in the figure. Isolation of the parts has been familiar with various applications. Cover layer 1 04A The layer 102A is wet-etched or dry-etched. For example, when the mask layer is nitrided to remove it; when the mask layer is polycrystalline silicon, the pad oxide layer 102A is removed to the trench isolation region 108A shown in an appropriate manner, which has a T ' The trench isolation region of the present invention covers the substrate surface around the trench 109. When the oxide layer is sacrificed, these are located at the edge of the isolation region, thus reducing the quality of the defects that may appear at the corners. The preferred embodiment is disclosed above, but it is not intended to Those skilled in the art can make changes and decorations without departing from the spirit of the present invention. Therefore, those defined by the protection scope of the present invention shall prevail.