TW451362B - Manufacturing method of high voltage device compatible to low voltage device - Google Patents

Abstract

A manufacturing method of high voltage device compatible to low voltage device is disclosed, which comprises providing a substrate; forming an oxide layer on this substrate; forming an N-well and a P-well on this substrate; forming plural N-fields on this P-well as the drift region and on this N-well as the insulation region; forming plural P-fields on this N-well as the drift region and on this P-well as the insulation region; forming plural N<SP>+</SP>-type doped regions on this P-well by N-grade implantation; forming plural N<SP>+</SP>-type doped regions on these N<SP>+</SP>-type doped regions as the source/drain of one of the NMOS transistors on P-well; form plural P<SP>+</SP>-type doped regions on N-well as the source/drain of one of the PMOS transistors. This polysilicon gate layer is defined to form the gate. This gate is across one channel of this NMOS/PMOS and one portion of neighboring field oxide.

Description

V. Description of the Invention (1) 5-1 Field of the Invention: The present invention relates to a method for forming a semiconductor element, and more particularly to a method for manufacturing a high-voltage element compatible with a low-voltage element on a semiconductor element. 5-2 BACKGROUND OF THE INVENTION: Recently, the demand for semiconductor components has increased rapidly due to the large number of electronic components. In particular, the rapid spread of computers has increased the demand for semiconductor components. Some integrated circuits around the computer, such as output / input circuits or circuits in the monitor, also need control circuits and drive body circuits. In most cases, low voltage components are usually used in control circuits, while high voltage components are usually used in drive circuits. However, in addition to the above components, there are still many components that require integrated high and low voltage components, such as liquid crystal displays for notebook computers, and electronic parts in watches. Therefore, integrated high and low voltage components are often used in semiconductor devices. The first A to C diagrams are cross-sectional diagrams showing various steps of forming a high-voltage element in today's deep submicron semiconductor technology. In the first diagram A, first, N well blank implantation is used to form N wells 102 and 104 on the substrate 100. The N wells 10 2 and 104 are usually formed by N-type ion implantation, such as using phosphorus ions or arsenic.

Page 5 4 513 6 2 V. Description of the invention (2) Ion implantation. In the first B diagram, a well compensation step is required to convert the N well 102 into the P well 106 for the formation of an NMOS transistor on the substrate 100. This type of well compensation step can be performed using P-type ion implantation, such as boron ion implantation. For N-type ion implantation, the filling or arsenic ions are biased closer to the surface of the N-well; for p-type ion implantation, In other words, boron ions tend to be far from the surface of the P well. Therefore, the well compensation step for N well 102 to form P well 106 will result in uneven distribution of ion concentration in well P 106, and another well compensation step must be performed. "Form N in Figure C" Before the doped regions (N_type doped regi on) 112a and 112b, a gate oxide layer 108 and a polycrystalline silicon layer as the gate 110 are formed first. After the polysilicon gate 110 is formed, N-grade implantation is used to form the N-type doped regions 112a and 1 1 2b. The N-type doped regions 11 2a and 11 2b are only activated by a high temperature. Steps such as tempering (annealing). Therefore, the diffusion depth of the N-type doped regions 112a and 112b is shallow. Furthermore, as described above, the distribution of the ion concentration in the P well 106 formed by the compensation using the N well completely implanted previously was not uniform. Therefore, it is difficult to obtain a good doping profile for snap-back voltage, and it is also difficult to control the hot carrier effect. 5 -3 Purpose and Summary of the Invention: In view of the above background of the invention, the high-voltage element manufactured by the traditional method

Page 6 451362 V. Description of the invention (3) Many shortcomings caused by the item ’The inventor is committed to the improvement of the manufacturing method of high and low electric dust components, and the invention has been produced. The main object of the present invention is to provide a method for manufacturing a high-voltage element compatible with a low-voltage element on a semiconductor substrate, in which only a single N-well and a P-well are used to form a high- and low-voltage element without repeated well compensation. Steps, so the mask for ion implantation can be reduced. Another object of the present invention is to provide a method for manufacturing a high-voltage device compatible with a low-voltage device on a semiconductor substrate, in which an N-level implant (N- grade implantation) forming N-type doped regions in a P well. Therefore, a better doping profile (doping profiie snap-back voltage) can be obtained, and the breakdown voltage can be increased. According to the above-mentioned object, the present invention provides a method for manufacturing a high-voltage element compatible with a low-voltage element on a semiconductor; first, a substrate is provided, an oxide layer is formed on the substrate, β forms an N-well, and a p-well. On the substrate. A plurality of N-type fields (N-f i e 1 d) are formed on the P well as a drift region (dr i ft region) and as an insulation region on the n well. A plurality of p-type% (P-f i e 1 d) are formed on the N well as a drift region (d r i f t r e g i ο η) and as an insulation region on the P well. Before the formation of a gate oxide layer and a gate polycrystalline silicon layer, a plurality of N-type doped regions are formed on the p-well by N-grade implantation. Formation complex

Page 7 1 4 5 1 3 6 2 V. Description of the invention (4) Several N-type doped regions (N + type doped regions) are used in this N-type doped region for one of the NMOS transistors on the P well. Source / immortal. A plurality of p + doped regions (P + type doped regions) are formed on the N-well for the source / drain of a PMOS transistor. The gate polysilicon layer is defined to form a gate that spans a channel of the NMOS / PMOS and a portion of adjacent field oxides. The purpose and many advantages of the present invention will become clearer through the following detailed description of the preferred specific embodiments and with reference to the attached formula "5-4 Detailed Description of the Preferred Specific Embodiments: The second to sixth figures are representative A schematic view showing various steps of a preferred embodiment of the present invention. First, a P-type semiconductor substrate 200 is provided, as shown in the second figure. Continue with reference to the second circle 'to form an oxide layer 2 2 with a thickness of about 300-7000 angstroms on the substrate 2000. The oxide layer 202 may be a silicon dioxide layer formed by a chemical vapor deposition method, such as PECVD, LPCVD, or APCVD. The first ion implantation and drive in 'are performed to form an N-well 204 on the substrate 200. Then, a second ion implantation and thermalization are performed to form a PM0 anti-punchthrough (PAPT) well 20 6 having a thickness of about 0.2 to 0.4 m on the N-well 204. This heating step can be used back

451 36 2 V. Description of the invention (5) The annealing process. The PAPT well 206 is used to prevent the penetration between the source and the drain of a PM0S transistor in the N well 204.

Referring to the third figure, the oxide layer 202 on the substrate 200 is removed. An oxide layer 208 and a silicon nitride layer 2 10 are formed on the substrate 2000 and are defined, and the P APT well 2 0 6 and the substrate 2 0 part in the N well 20 4 are defined. Exposed. A third ion implantation and drive are performed to form a P-well 212 on the substrate 200. In this specific embodiment, the doping concentration of the P-well 206 is greater than the doping concentration of the substrate 200. Next, a fourth ion implantation and heating step is performed to form a NMOS anti-punchthrough (NAPT) well 214 with a thickness of about 0.2 to 0 · m in the P well 212. This heating step may use an annealing process. The NAPT well 2 1 4 is used to prevent the penetration between the source and the drain of an NM0S transistor on the P well 2 1 2. Referring to the fourth figure, 'N-field implantation is performed, and N-type doped regions 216a and 216b' are formed on the NAPT well 2 1 4 as a drift region. N-type doped regions 218 and 218b are formed on the PAPT well 20 6 as an insulating region. The dopant concentration of this N-type field implant is about 1 × 10 0% 3 × 10 0 17 / cm 3. After that, a field oxide layer 2 20 is formed on the defined substrate 200, for example, the exposed substrate 200 'is thermally oxidized, that is, the thermally exposed p apt wells 206 and N APT wells 214. Referring to the fifth figure, the silicon nitride layer 2 1 0 is removed. Then, using a photomask and fifth, description of the invention (6), an eye implantation was performed to form a 1 ^ -type doped region (1 ^ -Shi 7 6 doped regi) 222a ^ on the "?" Well 214. 222b, with a doping concentration of about ΐχΐ〇ΐ6 to 3χ10π / cubic centigrade for p-field implantation to form a p-type doped region on the PAPT well 2 0 6 224a and 224b 'are used as drift regions, and P-type doped regions 2 2 6 a and 2 2 6 b' are formed as n APT wells 21 4 as insulation regions. 1 0 16 to 5 X 1 0 1V cubic centimeters. Referring to the sixth figure, after removing the pad oxide layer 208, V heterogeneous implantation can be selectively performed to control the starting voltage (thresh〇i (i voltage). A polycrystalline silicon layer as the gate electrode 2 3 0 a / 2 3 0 b is formed and crosses part of the adjacent field oxide 2 2 0 and part of the adjacent NAPT well 2 1 4 / PAPT well 206. Finally, using a photomask and performing a sixth ion implantation, an N-type doped region 2 3 2aA 232b is formed in the n-type doped regions 222 a and 222 b, and the doping concentration is about 9X101 Sheng 7x10 15 / Cubic centimeters, which are regarded as p wells 212 〇05 the source and non-electrode of the transistor. Seventh ion implantation was performed to form P-type doped regions 234 a and 234 b in N well 2 'with a doping concentration of about 8x10% 5x10 15 / cm 3', respectively As the source and drain of the PM0S transistor in N well 2 0 4. Since the gate oxide layer 22 8 and polycrystalline stone gate 2 3 0 a and 230 b are formed at high temperature, it is favorable for doping. Diffusion. The 1 ^ -type doped regions 216a, 216b, 222a, and 222b and the P-type doped regions 224a and 224b become deeper diffusion regions, and even diffuse into the substrate 200. Therefore, better doping of the doping voltage can be obtained. Curve (doping profile for snap-back voltage), and increase the breakdown voltage. Then prevent the vertical transfer of carriers towards the substrate, and avoid

Page 10 4 5 13 6 2 V. Explanation of the invention (7) ~~~ —- Free f = = f f crystal formation (ParaSitic bipQlar tFansistQfk formation, and effectively control the hot carrier effect. Furthermore, the invention The method does not require repeated well compensation steps, so it can also reduce the photo-implantation mask. To the top of the special V volume is available on the low-brightness electricity available / supply-kind / semiconductor substrate used in 2. The sub-head is a high-voltage component of a low-voltage component. In the preferred embodiment, &quot; N stands for high dopant concentration. N stands for N-type dopant with low dopant concentration. On the other hand, ρ + &quot; = P-type dopant with epitaxial concentration, &quot; ρ * _, which represents low-type dopant with ρ-type dosing book: the embodiment of the moon and 6 'is not used To limit the spirit dli: 71 other changes or modifications that do not depart from the scope of the patent disclosed by the present invention shall be included in the following applications

451362 The diagrams briefly illustrate the first A to C diagrams showing cross-sections of various steps of a conventional method for forming a high-voltage element on a semiconductor substrate; and the second to sixth diagrams are cross-sections of various steps in a preferred embodiment of the present invention. schematic diagram. Representative symbols of main parts: 100 substrate 102 N well 104 N well 106 P well 108 Gate oxide layer 110 Gate 112a, 1 12b N-type doped region 114a, 1 14b N-type doped region 116a, 1 1 6b P-type Doped region 200 substrate 202 oxide layer 204 N well 206 PAPT well 208 whole oxide layer 210 silicon nitride layer 212 P well 214 NAPT well

Page 12 45 1 3 6 2 Schematic description 2 1 6 a, 2 1 6 b N 螌 doped regions 218a, 218b N-type doped regions 220 Field oxides 222a, 222b N-type doped regions 224a, 224b P-type doped region 2 28 Gate oxide layer 230a, 230b Polycrystalline silicon gate 232a, 232b N-type doped region

Page 13

Claims (1)

451362 VI. Application Patent Scope 1. A method for forming a high-voltage element compatible with a low-voltage element on a semiconductor substrate, which at least includes: forming an oxide layer on a substrate; covering a photomask on one of the substrates In the upper part, an N-well is formed on the substrate; successively formed—a pad oxide layer and a silicon nitride layer on the substrate; the hafnium oxide layer and the silicon nitride layer are defined to expose a part of the substrate Use a photomask 'to form a P-well on this substrate, which uses a photomask relative to the N-well to form a plurality of N-type fields in the P-well for the drift region', where each N-type field is covered in A part of a channel of an NMOS transistor in the P-well 'and a plurality of N-type fields are provided in the N-well t as an insulation region, and each N-type field is adjacent to a PMOS in the N-well One source / drain of a transistor; forming a plurality of field oxides on the exposed portion of the substrate; using a photomask to form an N-doped region between the two field oxides in the P well, which surrounds One of the NMOS transistors in the P well has a source / non-polarity; use a A mask to form a plurality of P-type fields in the N well for use as a drift region. Each of the P-type fields respectively covers a part of a channel of a PMOS transistor in the N well and is located adjacent to this channel. Below a field of oxide 'and a plurality of P-type fields in the P-well for use as an insulating region, where each P-type field is located below each of the field oxides adjacent to the source / drain in the P-well, respectively. ; Page 14 451362 6. The scope of the patent application forms a gate oxide layer on the substrate; a polycrystalline silicon gate is formed on the gate oxide layer on the N and P wells respectively, and the polycrystalline silicon gate spans the This channel of N / P well and a part of the field oxide adjacent to this channel; using a photomask, forming an N-type doped region in the N-type impurity region for use in the P-well A source / drain of the NM 0 S transistor; and using a photomask to form a P-type doped region in the N well for use as the source of the PMOS transistor in the N well / Drain. 2. The method according to item 1 of the scope of patent application, wherein the above-mentioned N-type doped region is a lightly doped implantation method, and its doping concentration is about 1X 1 0 16 to 3X1 0 | 7 / cubic centimeter. 3. For the method of applying for the first item of the patent scope, wherein the above-mentioned N-type doped region is formed by a heavily doped implantation method, and its doping concentration is about 9 × 101 Sheng 7x10 15 / cm 3. A method according to item 1, wherein the above-mentioned P-type doped region is formed by a heavily doped implantation method, and its doping concentration is about 8 × 10 14 to 10 15 / cm 3 ^ 5. As the method of claim 1 in the patent scope, wherein After the formation of the above-mentioned N well, a PMOS ^ penetrating well is formed in the N well. Page 15 6. Scope of patent application 6. The method of the first scope of patent application, wherein after the above-mentioned P well is formed, an NMOS anti-penetration well is formed in the P well. 7. The method of claim 1 in which the above-mentioned field oxide layer is formed by a thermal oxidation method. 8. The method according to item 1 of the scope of patent application, wherein before the formation of the above-mentioned gate oxide layer, V T implantation is performed to control the starting voltage. 9. The method according to item 1 of the patent application, wherein before the formation of the gate oxide layer and the polycrystalline silicon gate, the N-type doped region is first formed in the P well. 10. The method according to item 5 of the patent application, The P-type fields in the above-mentioned PAPT layer serving as drift regions span a part of the N 丼. 1 1. If the method of applying for item 6 of the patent scope is applied, wherein the N-type doped regions in the above-mentioned NAPT layer and the N-type fields used as drift regions span a part of the P well. 12. If the method of the scope of the patent application is applied to item 5, wherein after the formation of the above PMOS anti-penetration well, a heating step is performed to densify the PMOS anti-penetration well at high temperature. 13. If the method of the scope of the patent application is applied, Of which the above NMO &amp; charge penetration Page 16 451362 VI. Scope of patent application After the well is formed, a heating step is performed to densify the NMOS anti-penetration well at high temperature. 14. The method according to item 5 of the scope of patent application, wherein the thickness of the above-mentioned PMOS through-through-hole is about 0.2 to 0.4 m. 15. The method according to item 6 of the patent application, wherein the thickness of the above NMOS anti-penetration well is about 0.2 ~ 0.4 / z m. Page 17