A7 B7 449915 五'發明説明（） 發明領域： 本發明揭露一種有關於半導體元件製程，特別是有 關一種具有帶與帶（band tq band)低漏透穿電流特性之標 記唯讀記憶想（mask read only memory，簡稱 mask R〇M) 之元件的結構與製程· I發明背景： 今曰’由於用於筆記型電雎行動電話、可機式CD 唱盤等等需要大量的儲存裝置，因此，一半導雜記愧元 件技術*用以製造極高I度非揮發性半導體記億元件精 體電路的製程已引起廣的注目。一般而言，應用於標 β己唯讀記憶趙以儲存資訊之每一金氧半電晶艘的閘極下 通道之啟始電壓（threshold voltage)在資料寫入之前，皆 設定為同一預設值（例如0.2-1伏）換言之.是預設為導 通狀態（“on” state)。另一方面，金氧半電晶體也可以以 提高啟始電壓以設定為關閉狀態（“off» statep另外，資 料的寫入也可以以降低電晶體的啟始電壓來達成目的》 例如’以經由改變電晶體的模式，例如加強模式（enhance mode)變更為空乏區（depletion mode)模式。一般而言， 依所储存之資料製造一常態為關閉狀態之標記唯讀記憔 體*經常是藉由硼離子經一犧牲氧化層或複晶矽而至通 道區域以達成，請參考由Aoki在1996年7月23曰所 本紙張尺度適用中國困家標準（CNS ) Μ规格（210X297公釐） -----^---T---------訂------1 I -· <請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印策 4499 1 5 A7 B7 五、發明説明（) 取得的美國專利案號第5,5 3 8,906號。 ---------^-- (請先閲讀背面之注意事項再填寫本頁) 不過高劑量的離子佈植將導至被設碟（codeii)之金氧 半電晶體低接面崩溃電壓，並且更重要的是導至成為極 高的帶與帶（band to band)漏透穿電流特性之標記唯讀記 憶體》請參考由Irani在1997年11月所取得的美國專 利案號第5,683,925號。A7 B7 449915 Five 'invention description () Field of the invention: The present invention discloses a semiconductor device manufacturing process, and in particular, a mark read-only memory thinking with a low leakage through current characteristic of a band and band (band tq band). Only memory (referred to as mask ROM) component structure and manufacturing process · I BACKGROUND OF THE INVENTION: Today's' Because it requires a large number of storage devices for notebook-type mobile phones, portable CD players, etc., half of the guide Miscellaneous shame device technology * The manufacturing process used to make extremely high-degree non-volatile semiconductor memory devices with delicate circuits has attracted wide attention. Generally speaking, the threshold voltage of the channel under the gate of each metal-oxide-semiconductor wafer applied to the standard β-read-only memory and Zhao to store information is set to the same preset before data is written The value (for example, 0.2-1 volt), in other words, is preset to the "on" state. On the other hand, the metal-oxide semiconductor transistor can also be set to the off state by increasing the start voltage ("off» statep ", and the writing of data can also be achieved by lowering the start voltage of the transistor). Change the mode of the transistor, for example, enhance mode to depletion mode. Generally speaking, according to the stored data, a mark that is normally closed is read-only. The body is often read by Boron ions pass through a sacrificial oxide layer or polycrystalline silicon to the channel area to achieve. Please refer to the paper size applicable by China Standards (CNS) M standard (210X297 mm) by Aoki on July 23, 1996- --- ^ --- T --------- Order ------ 1 I-· < Please read the precautions on the back before filling out this page) Staff Consumer Cooperatives, Central Bureau of Standards, Ministry of Economic Affairs Seal 4499 1 5 A7 B7 5. Description of the invention () US Patent No. 5,5 3 8,906 obtained. --------- ^-(Please read the notes on the back before filling in this (Page) However, high-dose ion implantation will cause the low junction of the metal-oxide-semiconductor crystals in the codeii to collapse. Voltage, and more importantly, a read-only memory that leads to extremely high band-to-band leak-through current characteristics. "Please refer to US Patent No. No. 5,683,925.
Sheu等人在1997年1月28曰所取得的美國專利案 號第5.597,753號，提到佈植之摻雜離子在退火予以活 化的過程中能會產生橫向的擴散而導致鄰接之深埋層的 位元線（buried bit line) 摻雜離子相碰觸。很明顯的， 這將使得深埋層的位元線和設碼佈植（coding imp丨ant)區 鄰接之欲予的宽度相衝突並且顯著的增加了各別位元線 之串聯電阻。這問題在兩個鄰接區都都被設碼佈植的情 況下將更嚴重。 .線 經濟部中央標準局員工消费合作社印装 由於，CMOS電晶體之啟始電壓與閘極軋化層的厚 度以及通道的摻雜準位有關。因此，在製造常態為關閉 狀態之標記唯讀記德體的技術文獻中，巳有一些方法已 被提出用以解決上述的問題。例如Irani等人，在其專 利說明書中便提出一方法以製造標記唯讀記憶體*如圖 一所示，以熱氧化法在唯讀記憶體陣列區30成長一厚 的閘極氧化層18，即使周邊的閘極氧化層2較薄。不過 ik張纽逍用中理國家標率(CNS ) A4祕（210X297公釐） 卜 4 499 1 5 A7 一 — _ B7五、發明説明（） 值得注意的是，在他們的標記唯讀記憶體之摻雜準位仍 將使得帶至帶的漏電流和弱的接面崩潢性能的問題。 Sheu等人在其專利說明書中提出另一方法，如ffl二 所示。一設码區域50經由微影和光阻技術以沉積一層 厚的氧化層而勿需實施離子佈植以達到將啟始電壓調整 目的。這一方法的優點在於厚的氧化層14可使得鄰接 的位元線具有極佳的電氣絕緣特性並且無帶與帶之間漏 電流的問題需要加以考慮。不過，為增加啟始電壓氧化 層就需要頗厚的（例如欲得到5.7伏的啟始電壓氧化層的 厚度約需要80 nm的大小。除此之外，當欲去除厚的氧 化層上的光阻層，卻不會傷害到氧化層的品質最值得考 慮的。 發明目的及橛述 I (I n It ^ ———In!— 訂 (请先聞讀背面之注意事項再填寫本頁) 線 經濟部中央標準局員工消费合作社印製 本發明之目的在揭露一具有改善帶與帶（band to band)高漏透穿電流特性之標記唯讀記憶體（簡稱 mask ROM)之元件的結構與製程》 本發明之標記唯讀記憶體結構概述如下：複數個深 埋層的位元線形成於一半導體基板上。每一深埋層的位 本纸張尺度適用中國國家揉率（CMS ) A4说格（210X297公釐） d49915 A7 B7 經濟部中央標準局員工消費合作社印裝 五、發明説明（） 元線間彼此保持一距離，而複數個第一氧化層是以墊氣 化層以熱氧化法成長而形成。相較於第一氧化層，第二 氧化層是那些以前述的熱氧化法處理卻未成長的氧化 層。每一第二氧化層皆與第一氧化層相毗鄰並和深埋層 的位元線相接β —設碍區域（coding region)位於這些第 二氧化層其中的一個之下；一第三氧化層是一液相沉積 氧化層形成於設瑪區域的上面，中間以第二氧化層隔 開。一同步摻雜的複晶矽層形成於這些第一氧化層、第 一氧化層和第三氧化廣的上面》 本發明之在半導體基板上製造具有帶與帶低漏透穿 電流特性之標記唯讀記憶體之元件的方法，包含以下步 驟：首先，形成一墊氧化層於半導體基板上；接著形成 一氮化層於墊氧化層上；然後以一罩幕層囷案復蓋於氮 化層上以定義該深埋層的位元線，隨後蝕刻氮化層並施 以第一次離子佈植以形成深埋層的位元線佈植；在去除 氮化層上之罩幕層後，以第一熱氧化製程以使曝露之墊 氧化層成長。接著，去除其餘之氮化層以曝露出未成長 之墊氧化層；然後，以一光阻圓案覆蓋在所有區域上， 僅曝露出預定之設碼區域；之後，以第二次離子佈植以 調高啟始電壓。接著形成一絕緣層於預定之設碼區域之 上；隨後去除該罩幕層；再施以另一次含氟之氧或氮氣 氛熱處理製程。最後形成一導電層在該半導體基板的所 有表面上。 ¾-- (請先閲讀背面之注意事項再填寫本瓦) 訂 線 II--^---- 本紙張尺度逋用中國國家標準（CNS ) A4规格（210X297公釐} --4499 1 b A7 B7五、發明説明（） 經濟部中央標準局員工消費合作社印裝 下 記裁之氬 域佈氮離佈設 以 標橫域I/區子被的子在 層 輔 於的區 t 線離未雜離層 中 層層碼 Μ 元線使摻以化 字 化化 設i*位 元 以化 施氧 文 氧氧 在 的 位 程活 後‘，積 明 極極 層 層 的 製且 圖沉 說 閘閘 化 & 埋 層 化層 化視相 之 的的 氧 U 深 埋 氧化 U面液 後 厚薄 的 基 化 深 熱氧 除截 一; 往 較較 厚案 以 以的 去横成圖 於 成有 造圖於 ® 施 施厚 ，的形視 將 形具 製視 ， ， ，化 持區，面 例： ，則 ，面術 術 術 術氧 W瑪術裁 施述 術邊 術截技 技 技 技區 技設技橫 實闡 技周 技橫明·明 明 明層 明一明的 佳的 知在 知之發圖發 發：發化·，發之發上 : 較細 習， 習列本視本；本圖本氧圖本義本層 明 的詳 據區 據陣據面據圖據視據墊視據定據化 說 明更 依體 依體依截依視依面依的面依阻依氧 單發做 示憶；示憶示橫示面示截示罩截示光示墊 簡本形 顯記圖顯記顯的顯載顯橫顯遮橫顯以顯的 式圖 一讀視二讀三層四橫五的六層的七，八區 圖 列 圊唯面圊唯圊化圖的圖植圖化子圖植圊碼 裝------訂------線 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210X297公釐） 經濟部中央標準局貝工消費合作衽印製 449915 A7 B7 五、發明説明（） 圓九顯示依據本發明技術，形成一同步摻雜的複晶梦層 以定義字元線的橫截面視圖； 圊十顯示依據本發明技術，以形成一反及閘標記唯讀記 憶體的俯視圈：及 圈十一顯示依據本發明技術，繪出各種標記唯讀記億艘 的汲極電流（Id)對閘極電壓（Vg)之曲線圈。 5.發明詳麯說明： 本發明提供一具有帶與帶（band to band)低漏透穿電 流（low leakage tunneling current)特性之標記唯讀記憶 體（mask ROM)之元件的結構與製程。结構部份將先描 述，製造方法的細節容後再述，並加以討論如下： 本發明之標記唯讀記憶體示於圈九。一複數深埋層 (buried bit line)的位元線135形成於一半導體基板105 之上》每一深埋層的位元線間彼此保持一距離，而複數 個第一氡化層130皆由墊氧化層110以熱氧化法成長而 形成。複數個第二氧化層Π0也是墊氧化層Π0形成於 半導體基板105的上面。相較於第一氧化層丨3〇’第二 氧化層110是經前述熱氧化製程卻未成長的氣化層。每 一第二氧化層110皆與第一氧化層130相毗鄰*並和深 埋層的位元線135相接8 —設碼區域（c〇ding reSion)140 位於這些第二氧化層110其中的一個之下：一第三氧化 本紙張尺度適用中國國家揉率（CNS ) A4规格（2丨0X297公* > i^n ·Ί^— *·1^1 m n —ί— I C請先聞讀背面之注意事項再填寫本I) 訂 " 4 4991 5 A7 B7 經濟部令央標準局員工消費合作社印裝 五、發明説明（) 層是一液相沉積氧化層150形成於設碼區域140的上 面’以第二氡化層11〇則介於其中》—同步摻雜的複 晶矽層160形成於這些第—氧化層13〇，第二氧化層11〇 和第三氧化層150的上面 本發明之標記唯讀記憶體的製造方法如下所述： ®三示一墊氧化層110以熱氧化法或化學氣相沉積 (CVD)法在<〇〇!>矽基板1〇5上成長至5-50nm的厚度的 橫截面® β緊接著，一氮化層115以CVD的方法沉積， 首先，沉積在一薄墊氡化層110以及隔絕區104之上* 以一較佳的實施例而言，釓化層 115可以以低壓 CVD(LPCVD)的方法在約700-800。(：下沉積。 參照圔四，_光阻120覆蓋在氮化層115之上，並 經由微影的技術®案化以定義深埋層的位元線區。接著 以熱磷酸鹽溶液蝕刻以曝露出氮化層11 5。 參考圖五，以光阻為罩幕，施以一 11+深埋層的位元 線離子佈植用以形成一重摻雜區125。以一較佳的實施 例而言，η型雜子的種類可以是磷、砷或者是銻。用於 離子佈椬的能量和劑量分別約為0.5-100 keV和2><1014· 2X 1 01 e /cm2。 如圖六所示。在去除光阻110之後，一高溫的熱氧 II n LJ — —I- 1 I i (请先閲讀背面之注意^項再填寫本頁) !,, 1· 本紙張尺度適用中國國家標率< CNS ) A4规格（210X297公釐） 44991 5 A7 B7 _ 丨 ----- -— ——- — ’一 - 五、發明説明（） 化製程用以形成一厚的氧化層丨30。以一較佳的實施例 而言，熱氡化製程的溫度約800-1100 °c，1〇~1〇〇分鐘 至約50-300 nm的厚度。在重摻雜區的雜質在同一時間 也被活化並驅入半導體基舞115的内部而形成深埋層的 位元線1 3 5 » 在成長厚的氧化層130之後，所有在墊氧化層110 上的氣化層115以熱磷酸鹽溶液去除。接著一光阻145 復蓋在半導體基板105的所有區域除曝露預定之設碼區 域140 以外。為增加設碼區域140之啟始電壓以形成 一常態關閉的標記唯讀記德體’以一低剤量BF/或者B + 施以離子佈植形成設碼區140。以一較佳的實施例而言’ 離子佈植的能量和劑董分別約為10-80 keV和 5xl〇U-5χ1014 /cm2 ° 經濟部中央標準局負工消費合作社印裝 (請先聞讀背面之注意事項再填寫本頁) 圖八示，以一光阻層145為革幕，一低溫液相沉積 氡化層法用以在設碼區域140的上表面形成一氧化層 150以增加設碼之NMOS元件閘極區的氧化層厚度。以 一較佳的實施例而言，此低溫液相沉積氧化層法是在 25-150oC下沉積，並且同時加入氟原子於液相沉積軋化 層的製程之中《氧化層的厚度約為1〇-l〇0nm左右。接 著，另一高溫且快速的熱氧化製程可在氧氣的氣氛下’ 或者在N20拍氣氛下用以使氡化層緻密的製程接著實 施。實施的溫度約在800-1 100°C »Lu等人在參考資料 本紙張尺度逋用中國8家標率（CNS ) A4規格（210X297公簸） 經濟部令央標準局貝工消费合作社印袋 449915 A7 _____B7_五、發明説明（） “W‘S_ Lu et al·，in “Reliable Fluorinated Thin Gate Oxides Prepared by Liquid Phase Deposition Following Rapid Thermal Process/5 IEEE Electron Device Letter, EDL-17，p.172 (1996)”，提出氟化閘極氡化層具有良好 的硬度、抗熱載子、及高的容忍場崩溃電壓特性。 參考圖九*先去除光阻層14·5’接著*沉積一 η型 的雜質以同步摻雜於複晶矽層16〇。沉積的溫度約woes o°c> 而雜質的濃度約在5χ1019·5χ1021 /cm3 »複晶矽 層160係用以定義成字語線。 參考圖十，示一反及閘（NAND)型態的標記唯讀記憶 體的俯視圖。水平線和垂直線以實線劃的分別代表字語 線160和位元線135»除此之外，虚線140所指之處為 設碼區。反及閘之標記唯讀記億體沿A-A’線的橫截面 圈已在®三至圖九描述。 列於表一之數據係以相同的設碼區佈植條件，例如 以lOOkeV，BF2 +的佈植於25nm厚之整氧化層比較各種 設碼製程對啟始電壓的變化。由表中可以看到啟始電壓 VTH明顯的隨設碑區域佈植劑量的大小以及設碼區氣化 層的厚度而改變。試片中若同時有高劑量佈植且係厚的 氧化層在設碼區域可以看到有較高的VTH值（例如C和 F試片7.41和6.16伏）。進一步説’若試片沒有設碼佈 10 1 I I . n n n i— *1 n I n n n ^ (請先閱讀背面之注^H項再填寫本頁) 本紙張XJU4财卵家料（CNS ) (:丨㈣97公釐） ^ ^ 44991 5 A / B7五、發明説明（） 植或者厚的閘機氧化層或者兩者皆無時將示更低值的啟 始電壓VTH值（例如，試片B ' D ' E、和A分別為2,8 1 * 1.84、3.95、及 0.69 伏） 表4 各— 試片 設碼佈植 （cm)' 2 設碼區氧化層 厚（nm) Vth (V) A No No 0.69 B 1 .Ox 1 Ο14 No 2.8 1 C 1 .OxlO14 30 7.41 D No 30 1.84 E 5.Οχ 1 Ο14 No 3.95 F 5.Οχ 1013 30 6.1 6 (讀先閱讀背面之注意事項再填寫本頁} 經濟部中夬標準局員工消費合作社印製 圖十一示以不同的設碼條件，以汲極電流（Id)對閘 極電壓（Vg)的曲線圖=由圖十一和表格一的結果顯示， 低劑量硼佈植合併厚的氧化層是形成常態闕閉唯讀記憶 體的絕佳候選者" 本發明的優點包括 (1) 設碼之NMOS元件之高劑量設碼佈植所導致的 低接面崩潰電壓和高的帶與與漏電流之問題可 以經由低劑量的硼或者BF2 +離子佈植而解決。 (2) 本發明所提供之閉極氡化層的厚度遠比傳統做 法所用之厚閘極的氧化層要薄得多。 以上所述僅為本發明之較佳實施例而已，並非用以 本紙張尺度逍用中國國家揉準（CNS ) A4規格（210X297公釐）U.S. Patent No. 5.597,753, obtained by Sheu et al. On January 28, 1997, mentions that implanted dopant ions can generate lateral diffusion during annealing to activate and cause adjacent burial. The layered bit lines are doped with ions. Obviously, this will cause the bit lines in the deep buried layer to conflict with the desired width of the coding impotant region and significantly increase the series resistance of the individual bit lines. This problem is exacerbated when both adjacent areas are coded. .Line Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. Because the initial voltage of a CMOS transistor is related to the thickness of the gate rolling layer and the doping level of the channel. Therefore, in the technical literature for manufacturing the mark-reading ethics with the normally closed state, several methods have been proposed to solve the above problems. For example, Irani et al., In their patent specification, proposed a method to manufacture marked read-only memory * As shown in FIG. 1, a thick gate oxide layer 18 is grown in the read-only memory array region 30 by thermal oxidation, Even the surrounding gate oxide layer 2 is thin. However, IK Zhang Niuxiao used the Chinese National Standards (CNS) A4 secret (210X297 mm) bu 4 499 1 5 A7 I — _ B7 V. Description of the invention () It is worth noting that in their mark only read-only memory The doping level will still cause problems with leakage current and weak interface collapse performance. Sheu et al. Proposed another method in their patent specification, as shown in ffl II. A coding area 50 is deposited by lithography and photoresist technology to deposit a thick oxide layer without performing ion implantation to adjust the initial voltage. The advantage of this method is that the thick oxide layer 14 can make the adjacent bit lines have excellent electrical insulation characteristics and the problem of no leakage current between bands needs to be considered. However, in order to increase the initial voltage oxide layer, a thick layer is required (for example, to obtain a initial voltage of 5.7 volts, the thickness of the oxide layer needs to be about 80 nm. In addition, when the light on the thick oxide layer is to be removed The barrier layer, but it will not hurt the quality of the oxide layer is the most worth considering. The purpose of the invention and the description I (I n It ^ ——— In! — Order (please read the precautions on the back before filling this page) line The purpose of printing the present invention by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economics is to disclose the structure and manufacturing process of a mark-read-only memory (mask ROM) component with improved band-to-band high leakage current characteristics. 》 The structure of the mark read-only memory of the present invention is summarized as follows: a plurality of bit lines of a deep buried layer are formed on a semiconductor substrate. The paper size of each deep buried layer is applicable to the China National Kneading Rate (CMS) A4. Grid (210X297 mm) d49915 A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention () The yuan lines are kept at a distance from each other, and the plurality of first oxide layers are thermally oxidized by a cushion gasification layer Grow up Compared to the first oxide layer, the second oxide layers are those oxide layers that have not been grown by the aforementioned thermal oxidation method. Each second oxide layer is adjacent to the first oxide layer and is deeply buried. Bit lines are connected to β-the coding region is located under one of these second oxide layers; a third oxide layer is a liquid-phase deposition oxide layer formed on the top of the Shema region, with a second in the middle The oxide layer is separated. A synchronously-doped polycrystalline silicon layer is formed on the first oxide layer, the first oxide layer, and the third oxide layer. A method for marking a read-only memory device with current characteristics includes the following steps: first, forming a pad oxide layer on the semiconductor substrate; then forming a nitride layer on the pad oxide layer; Bit lines covering the nitride layer to define the deep buried layer, followed by etching the nitride layer and applying a first ion implantation to form a deep buried layer bit line implant; after removing the nitride layer, After the cover layer, the first thermal oxidation process is used to The exposed pad oxide layer is grown. Next, the remaining nitride layer is removed to expose the ungrown pad oxide layer; then, a photoresist pattern is used to cover all areas, and only the predetermined coding area is exposed; The second ion implantation is used to increase the starting voltage. Then an insulating layer is formed over the predetermined coding area; the cover layer is subsequently removed; and then another fluorine-containing oxygen or nitrogen atmosphere heat treatment process is applied. . Finally, a conductive layer is formed on all surfaces of the semiconductor substrate. ¾-- (Please read the precautions on the back before filling in this tile) Alignment II-^ ---- This paper uses the Chinese national standard ( CNS) A4 specification (210X297 mm) --4499 1 b A7 B7 V. Description of the invention () Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. In the zone supplemented by the layer, the t-line is separated from the non-heteroseparated layer in the middle layer code. The M-line is mixed with the wording and setting the i * bit to change the position of the oxygen and oxygen. Polarization of layers and layers Delamination of the visual oxygen U deep oxidized U surface fluid, the thickness of the deep basal deep thermal oxygen cut off; to the thicker case, go to the horizontal map to the map with the map to the application of the thickness The form of vision will be shaped,,, ,, and holding area, face examples:, then, facial surgery, surgery, oxygen, W, and martial arts, cutting edge technique, cutting technique, technical area, technical setting, and practical interpretation. Zhou Jihengming · Ming Mingming Ming Mingming Ming Zhiming's best knowledge is published in the Zhizhizhifa: Fahua ·, Fazhifa: More detailed exercises, the original version of this book; the original version of the oxygen map The detailed area of the data, the data, the data, the data, the data, the data, the data, the data, the data, the data, the data, the data, the data, the data, the data, the data, the data, the data, the data, the data, the data, the data, the data, the data, Shows the display cover, shows the light display pad, the simplified form, the graphic display, the graphic display, the horizontal display, the horizontal display, and the horizontal display. Figure column 圊 圊 圊 圊 圊 圊 圊 圊 图 图 图 图 图 图 植 植 植 植 植 子 子 订 装 装 装 订 订 订 订 订 线 线 请 (Please read the precautions on the back before filling this page) Applicable scale National Standard (CNS) A4 specification (210X297 mm) Printed by the Central Bureau of Standards of the Ministry of Economic Affairs, Printed 449915 A7 B7, V. Description of the invention () Yuan Jiu shows a synchronously doped complex crystal dream according to the technology of the present invention Layer to define a cross-sectional view of a character line; 圊 ten shows the top view circle of the anti-gate mark read-only memory according to the technology of the present invention: and circle eleven shows the various read-only marks drawn according to the technology of the present invention Record the curve of the drain current (Id) versus the gate voltage (Vg) of a billion ships. 5. Detailed description of the invention: The present invention provides a structure and a manufacturing process of a mark ROM device having a characteristic of low leakage tunneling current with band to band. The structural part will be described first, details of the manufacturing method will be described later, and discussed as follows: The mark read-only memory of the present invention is shown in circle nine. A plurality of bit lines 135 of a buried bit line are formed on a semiconductor substrate 105. The bit lines of each deep buried layer maintain a distance from each other, and the plurality of first halide layers 130 are formed by The pad oxide layer 110 is formed by a thermal oxidation method. The plurality of second oxide layers Π0 are also formed on the semiconductor substrate 105 on the pad oxide layer Π0. Compared with the first oxide layer, the third oxide layer 110 is a vaporized layer that has not grown through the aforementioned thermal oxidation process. Each second oxide layer 110 is adjacent to the first oxide layer 130 and is connected to the bit line 135 of the deep buried layer. 8-Coding reSion 140 is located in these second oxide layers 110. Under one: The paper size of the third oxide is applicable to the Chinese national kneading rate (CNS) A4 specification (2 丨 0X297 male * > i ^ n · Ί ^ — * · 1 ^ 1 mn —ί— IC please read first Note on the back then fill in this I) Order " 4 4991 5 A7 B7 Printed by the Consumers' Cooperative of the Central Standard Bureau of the Ministry of Economic Affairs 5. Description of the invention () The layer is a liquid-phase deposition oxide layer 150 formed on the coding area 140 On the top, a second siliconized layer 110 is interposed between them. A synchronously doped polycrystalline silicon layer 160 is formed on these first oxide layers 130, second oxide layers 110, and third oxide layers 150. The manufacturing method of the invented marked read-only memory is as follows: ® The three-layered oxide layer 110 is grown on a < 〇〇! ≫ silicon substrate 105 by a thermal oxidation method or a chemical vapor deposition (CVD) method. Cross-sections with a thickness of 5-50 nm ® β Next, a nitride layer 115 is deposited by CVD. First, a thin pad is deposited. Top layer 110 and isolation zone 104 * to a preferred embodiment, the gadolinium layer 115 may be a low pressure CVD (LPCVD) process at about 700-800. (: Underlayer deposition. Refer to Example 4. Photoresist 120 covers the nitride layer 115 and is lithographically defined to define the bit line region of the deep buried layer. Then it is etched with a hot phosphate solution to The nitride layer 115 is exposed. Referring to FIG. 5, a photoresist is used as a mask, and a bit line ion implantation of a 11+ deep buried layer is applied to form a heavily doped region 125. In a preferred embodiment In terms of the type of n-type heterozygote, phosphorus, arsenic, or antimony can be used. The energy and dose for ion cloth are about 0.5-100 keV and 2 > < 1014 · 2X 1 01 e / cm2. VI. After removing the photoresist 110, a high-temperature thermal oxygen II n LJ — —I- 1 I i (Please read the note on the back before filling this page)! ,, 1 · This paper size is applicable to China National Standard < CNS) A4 Specification (210X297mm) 44991 5 A7 B7 _ 丨 -------——--'一-5. Description of the invention () Chemical process is used to form a thick oxide layer丨 30. In a preferred embodiment, the temperature of the thermal annealing process is about 800-1100 ° C, and the thickness is from 10 to 100 minutes to about 50-300 nm. The impurities in the heavily doped region are also activated at the same time and driven into the semiconductor base dance 115 to form a deep buried bit line. 1 3 5 »After growing the thick oxide layer 130, all the pad oxide layer 110 The upper gasification layer 115 is removed with a hot phosphate solution. Then, a photoresist 145 covers all areas of the semiconductor substrate 105 except that a predetermined coding area 140 is exposed. In order to increase the starting voltage of the coding region 140 to form a normally closed mark, the read-only memory is used to form the coding region 140 with a low volume BF / or B + by ion implantation. In a preferred embodiment, the energy and dosage of ion implantation are about 10-80 keV and 5x10U-5x1014 / cm2 ° Printed by the Consumer Work Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read and read first) Note on the back side, please fill in this page again.) Figure 8 shows a photoresist layer 145 as a leather curtain and a low temperature liquid phase deposition method to form an oxide layer 150 on the upper surface of the coding region 140 to increase the design. The thickness of the oxide layer in the gate region of the NMOS device. In a preferred embodiment, the low-temperature liquid-phase deposition oxide layer method is to deposit at 25-150oC, and at the same time adding fluorine atoms to the liquid-phase deposition rolling layer. 〇-100nm. Next, another high-temperature and rapid thermal oxidation process can be performed in an oxygen atmosphere 'or in a N20 beat atmosphere to make the halide layer dense. The implementation temperature is about 800-1 100 ° C. »Lu et al. Used 8 papers in China (CNS) A4 size (210X297) as reference materials in this paper. 449915 A7 _____B7_ V. Description of the invention () "W'S_ Lu et al ·, in" Reliable Fluorinated Thin Gate Oxides Prepared by Liquid Phase Deposition Following Rapid Thermal Process / 5 IEEE Electron Device Letter, EDL-17, p.172 ( 1996) ", proposed that the fluorinated gate hafnium layer has good hardness, resistance to thermal carriers, and a high tolerance to field breakdown voltage. Refer to Figure 9 * first remove the photoresist layer 14 · 5 'and then * deposit an n-type The impurities are simultaneously doped in the polycrystalline silicon layer 160. The deposition temperature is about woes o ° c> and the concentration of the impurities is about 5 × 1019 · 5χ1021 / cm3 »The polycrystalline silicon layer 160 is used to define word lines. Reference Figure 10 shows a top view of a read-only memory of the NAND type. The horizontal and vertical lines are drawn with solid lines to represent the word line 160 and the bit line 135, respectively. The 140 refers to the coding area. The cross-section circle of the Yiyi body along the AA 'line has been described in ® 3 to Figure 9. The data listed in Table 1 are planted under the same coding area conditions, such as 100keV, BF2 + The 25nm thick oxide layer compares the changes in the starting voltage of various coding processes. From the table, it can be seen that the starting voltage VTH varies significantly with the implantation dose in the monument area and the thickness of the vaporization layer in the coding area. . If there is a high-dose implant and a thick oxide layer in the test strip at the same time, a higher VTH value can be seen in the coding area (for example, C and F test strips 7.41 and 6.16 volts). Further say 'If the test strip does not Code cloth 10 1 II. Nnni— * 1 n I nnn ^ (Please read the note on the back ^ H before filling this page) This paper XJU4 Fortune Eggs (CNS) (: 丨 ㈣97mm) ^ ^ 44991 5 A / B7 V. Description of the invention () If the implanted or thick gate oxide layer or neither is present, the lower starting voltage VTH value will be displayed (for example, the test pieces B'D'E, and A are 2 , 8 1 * 1.84, 3.95, and 0.69 volts) Table 4 Each — Test strip coding plant (cm) '2 Oxide layer thickness in coding region (nm) Vth (V) A No No 0.69 B 1 .Ox 1 Ο14 No 2.8 1 C 1. Printed by the Bureau of Consumers of the Standard Bureau, Figure 11 shows the curve of the drain current (Id) versus the gate voltage (Vg) with different coding conditions. The results shown in Figure 11 and Table 1 show that the low-dose boron The implanted and thick oxide layer is an excellent candidate for forming a normally closed read-only memory " The advantages of the present invention include (1) low interface breakdown caused by high-dose coded implantation of coded NMOS devices The problems of voltage and high band and leakage current can be solved by implanting low dose boron or BF2 + ions. (2) The thickness of the closed electrode halide layer provided by the present invention is much thinner than the thick gate oxide layer used in the conventional method. The above description is only a preferred embodiment of the present invention, and is not intended to be used in the paper size of China National Standard (CNS) A4 (210X297 mm)
44991G A7 B7 五、發明説明（ 揭述 所下 明在 發含 本包 離應 脫均 未’ 它飾 其修 凡或 ;變 圍改 範效 專之 。 請成内 申完圍 之所範 明下利 發神專 本精請 定之申 限示之 -裝 訂 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局貞工消費合作社印製 本紙張尺度適用中國國家標準（CNS) A4洗格（210X297公釐）44991G A7 B7 V. Description of the invention (disclosure does not include the release of this package and it should not be separated, it is used to decorate or modify; change the scope and effect of the special effect. Please make a statement within the scope of the internal application. The application of God ’s book is strictly bound-binding (please read the notes on the back before filling out this page) Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Zhengong Consumer Cooperative, this paper is printed in accordance with Chinese National Standard (CNS) A4 210X297 mm)