TW449780B - Transistor with silicon controlled rectifier protection device - Google Patents

Abstract

This invention is about the high voltage power transistor having silicon controlled rectifier (SCR) protection device, in which current can be completely uniformly distributed because the impedance values of SCR protection devices inside the high voltage power transistor are the same. When the electrostatic stress over the snapback voltage is invaded, the substrate current used to conduct SCR protection device can be provided. Additionally, because the current value inside each SCR protection device is the same, all of the SCR protection devices can be conducted at the same time to release the electrostatic stress so as to protect high voltage power transistor from being damaged by the electrostatic discharge (ESD).

Description

149780 V. Description of the invention (1) The present invention relates to the technology of Shi Xi controlled rectification type electrostatic protection element, especially to a silicon controlled rectification type electrostatic protection element technology with uniform current distribution. Power type integrated circuits (Power ICs) are mainly composed of high-voltage power transistors. However, taking the high-voltage NMOS transistor as an example, since the traditional parasitic diode or bipolar transistor is used as the jump-back voltage of the electrostatic protection element (Snapback voltage) is too high. Therefore, once there is an electrostatic stress intrusion, the high-voltage NM0S transistor is prone to electrostatic damage (ESD), which reduces the reliability of the device.

In order to improve the aforementioned situation, the traditional technician's disclosure—a high-voltage power transistor with a silicon-controlled rectification type electrostatic protection element, is shown in FIG. 1 as a cross-sectional structure of a conventional high-voltage protection device.

The 'high-voltage NMOS transistor HT-NM0S is formed on a semiconductor substrate 100. For example, the substrate may be a substrate composed of a silicon material doped with P-type ions. The conventional high-voltage protection device includes a pair of N-type non-electrode regions pH, j) i2, and each free N-type well region 110, 120. Wherein, the n-type well regions 110 and 120 each include a pair of N + -type heavily doped regions 132, 133 and 142, 143, and the pair of N + -type heavily doped regions 132, 133 are p + -doped heavily. Between the region ι31 and the pair of n + -type heavily doped regions 142, 143 is a p + heavily doped region ι4ι. An n-type source region S1 ′ is composed of an N + -type heavily doped region 150 and a pair of high-voltage power-type idler structures Gil and G12 are formed in the N-type source region si and the n-type non-electrode region D11, D12. The traditional technology is beneficial to form a pair of ν + type / agro-doped regions 160 and 170 on the periphery of the electrodes D11 and D12.

Page 4 44978 0 V. Description of the invention (2) A pair of P + -type heavily doped regions 180 and 190 are formed around to serve as a guard ring. In this way, an N 叩 double-carrier transistor can be formed by the N + -type heavily doped region 15 (emitter), the P-type substrate 100 (base), and the type-well region 12 (collector); and P + Doped region 141 (emitter), N-type well region 120 (base), and p-type substrate 100 (collector) constitute a __pNp bipolar transistor, both of which form a silicon-controlled rectifier static electricity Protection element SCR12. A PNP bipolar transistor is composed of a p + heavily doped region 141 (emitter), an N-type well region 120 (base), and a p-type substrate ϊ 00 (collector). Miscellaneous area 16

Electrode), P-type substrate 100 (base electrode), and N-type well region 120 (collector) constitute an NpN bipolar transistor; both of them form a silicon-controlled rectifier type electrostatic protection element SCR11. In the same way, an NPN bipolar transistor is formed by 15+ (emitter) of the heavily doped N + type, ιOO (base) of the p-type substrate, and 11 〇 (collector) of the N-type well region; and The P + heavily doped region 131 (emitter), the N-type well region 11 (base), and the p-type substrate 10 (K collector) constitute a PNP bipolar transistor, and the two form a silicon-controlled rectifier. ， Static protection element SCR13. A pNp bipolar transistor is composed of P + heavily doped region ι31 (emitter), N-type well region 11 (base), and P-type substrate 100 (collector). The miscellaneous region 17 (emitter), p-type substrate 100 (base), and N-type well region 11 (collector) constitute an NpN bipolar transistor; the two form a break-control rectifier type electrostatic protection Element SCR1 4. The above silicon-controlled rectification type electrostatic protection element allows high-voltage static electricity to be guided out of the transistor through the SCR element to avoid electrostatic damage (ESD) of the high-voltage power transistor. Among them, each of the aforementioned heavily doped regions is isolated by an insulating layer such as a field oxide layer F0X, the + -type source region is 150, the p + -type impurity-doped region is 180, and the N + -type region is

Page 5 449780

/ ^ 60 and the p + -type heavily doped region 190, and the p-type heavily doped region I " are connected to the node P of the i P-type semiconductor substrate 100, 102 and the p + -type hardly doped region as a guard ring. A parasitic resistance Rlg is formed between 180 and 190, and an impedance R1 2 is formed between each of them and the node 10 3 1 0 4, and a node 1 0 3 and a node 1 0 4 have

There is impedance R13. In the well regions Dn and D12iN-type well regions 110 and 120, the P + type heavily doped region 131, the N + type heavily doped region 132, the N + type heavily doped region 133, the P + type heavily doped region 141, N + -type heavily doped region 142 and N + -type heavily doped region ^ 143 are electrically connected to each other, and N + -type heavily doped region 132 and 133 and? ^-Type well region 110 each form a parasitic resistance R11, and N + A parasitic resistance Rn is formed between each of the heavily doped regions 142 and 1Φ3 and the N-type well region 120. :::

Because the bases of the aforementioned PNP type bipolar transistor and NpN type bipolar transistor are electrically connected to each other's collector, the base of each bipolar transistor is electrically charged by another bipolar transistor. Driven by the crystal's collector, a positive feedback loop is formed. Therefore, when an electrostatic stress exceeding the jumpback voltage invades, a substrate-induced current can be provided to conduct the aforementioned silicon-controlled rectifier electrostatic protection element, thereby releasing the electrostatic stress and avoiding high voltage Electrostatic damage (ESD) of power transistors. 'But' the aforementioned conventional structure has a disadvantage, that is, the equivalent resistances of SCR11, SCR14, SCR12, and SCR13 in the traditional high-voltage power transistor are not the same, because the equivalent resistance of SCR11 to the grounded P + heavily doped region 180 is equivalent. Is Rig, and the equivalent resistance of SCR12 to the grounded P + heavily doped region is Rlg + R12. In the same way, the situation of SCR13 and SCR14 is the same. Due to different equivalent resistances, the currents flowing through SCR11 and SCR12 will be different, which will cause the SCR elements to fail to conduct at the same time. If the SCR elements cannot conduct at the same time,

Page 6 449780 V. Description of the invention (4) When a large resistance SCK element is turned on first, due to the discharge effect, it is difficult to make the SCR element with a smaller equivalent resistance conductive, which causes the SCR element to fail to function. The ability of the SCR element to discharge static electricity is reduced, resulting in electrostatic damage to the high-voltage power transistor. In view of this, the main object of the present invention is to provide a high voltage power transistor with a silicon controlled rectification type electrostatic protection element. Since the equivalent resistance of each SCR element in the high voltage power transistor of the present invention is the same, The current distribution is fairly uniform. Therefore, it is possible to overcome the problem that the silicon-controlled rectification type electrostatic protection element in the conventional technology cannot be turned on and turned on simultaneously due to the uneven internal current distribution in the high-voltage power transistor. Therefore, it can quickly provide a large amount of substrate-induced current when electrostatic stress invades, and at the same time, all of its internal silicon-controlled rectification type electrostatic protection elements are turned on at the same time under low voltage, thereby improving ESD resistance to avoid damage to high-voltage power transistors. According to the above-mentioned object, the present invention proposes a Yuyuan power transistor with a shiki-controlled rectification type electrostatic protection element because the impedance values of the dream-controlled rectification-type electrostatic protection element inside thereof are the same as each other, so that the current can be completely uniformly distributed. When the electrostatic stress exceeding the jumpback voltage invades, it can provide the base current for conducting the silicon-controlled rectification type electrostatic protection element, and the current value inside the blL type electrostatic protection element is the same for each of the control circuits, so it can At the same time, all silicon-controlled rectifier electrostatic protection components are turned on at the same time, thereby releasing electrostatic stress to avoid electrostatic damage (ESD) of high-voltage power transistors. Brief description of the drawings: In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the attached drawings for detailed description, such as

Page 7 44978 〇 V. Description of the invention (5) '--- Τ: / 图 _ 明 ：

The Ip diagram is a schematic cross-sectional view of a high-voltage power transistor with a shi-controlled rectifier type electrostatic protection element. Fig. 2 is a schematic cross-sectional view showing a high-voltage power transistor having a silicon-controlled rectification type electrostatic protection element with evenly separated currents according to an embodiment of the present invention. Figure 3 shows the experimental results obtained when the present invention and the conventional technology are tested by a machine model method.

Fig. 4 shows experimental results obtained when the present invention and the conventional technique are tested by a manikin method. Explanation of symbols: 100, 200 ~ semiconductor substrate;

Dll, D12, D21, D22 ~ N type drain area; 110, 120, 210, 220 ~ N type well area; 132, 133, 142, 143, 150, 160, 170, 232, 133, 242, 243, 252 , 253, 260, 270 to N + -type heavily doped regions; 131, 141, 180 '190' 231 > 241 '251' 280, 290 to P + heavily doped regions;

SI, S2 ~ N type source region; KI1, Rig, R21, R2g ~ parasitic resistance; SCR11, SCR12 'SCR13, SCR14, SCR21, SCR22, SCR23, SCR24 ~ silicon controlled rectification type electrostatic protection element; 101, 102, 103, 104'201, 202, 203, 204 ~ nodes.

Page 8 44978 〇 V. Description of the invention (6) Example: Figure 2 shows a schematic cross-sectional view of a high-voltage power transistor with a silicon-controlled rectification type electrostatic protection element in the embodiment of the present invention. For the sake of this example, a high-voltage NMOS transistor formed on a P-type semiconductor substrate is taken as an example, but it should not limit the present invention.

The high-voltage NMOS transistor HV-NMOS of the present invention is formed on a semiconductor substrate 200. For example, can the substrate be doped? A substrate made of silicon material of the type ion. The high-voltage protection device includes a pair of N-type drain electrodes gD2; 1, D22, and each free N-type well area 2i0, 220. Wherein, the n-type well regions 2i0 and 220 each include a pair of N + -type heavily doped regions 23 2, 233, and 242, 243, and between the pair of N + -type heavily doped regions 232, 233 is a ρ + -type dopant. Between the doped region 231 and the pair of N + -type heavily doped regions 242 and 243 is a p + -type heavily doped region 241. An n-type source region S2 includes a pair of ^ + type heavily doped regions 252 and 253, and between the pair of N + type heavily doped regions 252 and 253 is a P + heavily doped region 251, and a pair of high voltages The power-type gate structures G21 and G22 are respectively formed between the n-type source region and the n-type non-electrode regions D21 and D22. The present invention further forms a pair of N + on the periphery of the N-type drain region ^^ and D22, respectively. Type heavily doped regions 26 and 27. An additional pair of p + type heavily doped regions 28 and 290 'are formed on the periphery of the pair of N + type doped regions 260 and 27G to serve as gUard rings. .

In this way, an NpN bipolar transistor can be formed by the N + -type heavily doped region 253 (emitter), the p-type substrate 200. (base), and the N-type well region 220 (collector), and by P The + doped region 241 (emitter), N-type well region 22 (base), and P-type substrate 200 (collector) form a PNP bipolar transistor, and the two form a silicon-controlled rectification electrostatic protection. Element SCR22. It consists of a p + heavily doped region 241 (4 4 9 7 8 0, description of the invention (7) pole), an N-type well region 220 (base), and a P-type substrate 200 (collector). A pNp bipolar transistor is an NPN bipolar transistor composed of an N + -type heavily doped region 260 (emitter), a p-type substrate 200 (base), and an n-type well region 220 (collector); two It forms a silicon controlled rectifier type electrostatic protection element SCR2l. Similarly, an NPN bipolar transistor is formed by the N + -type heavily doped region 252 (emitter), the p-type substrate 200 (base), and the N-type well region 21 (collector); and The P + doped region 231 (emitter), the N-type well region 210 (base), and the p-type substrate 200 (collector) constitute a pnp bipolar transistor, and the two form a silicon-controlled rectification electrostatic protection. Element SCR23. A PNP heavily doped region (emitter) in the N-type heavily doped region 231, an N-type well region 210 (base), and a p-type substrate 200 (collector). A PNP bipolar transistor is formed ' And an NpN bipolar transistor formed by 27+ (emitter) of n + type doped region, 200 (base) of p-type substrate, and 21o (collector) of n-type well region; both form a silicon Controlled rectification type electrostatic protection element SCR24. Wherein, each of the aforementioned heavily doped regions is isolated by an insulating layer such as a field oxide layer FOX. The N + -type heavily doped regions 252 and 253 and the p + -type heavily doped regions 251, the P + -type heavily doped regions 28 and 29, and the N + -type heavily doped regions 26 and 270 of the source region are grounded. A parasitic resistance R2g is formed between the nodes 200m and 204 of the p-type semiconductor substrate 20 () and the P + -type heavily doped regions 28 and 29 as guard rings; respectively, as the drain regions D21 and D22, In the N-type well regions 210 and 220, P + -type heavily doped regions 231, N + -type heavily doped regions 232, and 233 are electrically connected, and p + -type heavily doped region 241, N + -type heavily doped regions 242 and 243 are electrically connected. Electrically connected, and parasitic resistances R21 are formed between the… -type heavily doped regions 232 and 233 and the N-type well region 21G, and parasitic resistances are also formed between the N + -type heavily doped regions 242 and 243 and the N-type well region 2 20 R21. P-type semiconductor substrate 2000 has nodes 2002 and 203, respectively. Page 10 449780 1 Description of the invention (8)-Parasitic electricity is formed between the hetero region 251 and _2.其 $ 二 二 Description PNP type bipolar transistor and NPN type bipolar transistor have their bases electrically connected to each other's slave, so = feedback loop, therefore, the body's collector is driven to form a positive Back to supply-the substrate induces electricity; 4 =: when the electrostatic stress of the voltage is invaded, it can be mixed, and it is mixed. "别 Conducts a silicon controlled rectifier electrostatic protection element (ESD). Electrostatic stress to avoid electrostatic damage to high-voltage power transistors and the high-voltage power transistors with silicon-controlled rectification-type electrostatic protection elements provided by the present invention are equivalent to 5 (^ 21 for grounded ρ + heavily doped region 28). The resistance is R2g, and the equivalent electric resistance of the SCR22 to the ground p-doped region 251 !,) is R22. In the substrate 200, because the current paths are symmetrical and equidistant, the resistance values of R2g and R22 are the same, that is, SCR21 and 3 (^ 22 have the same equivalent resistance. When the electrostatic stress invades, the above SCR The element can be turned on at the same time under low voltage to guide the electrostatic stress to the outside of the transistor; the same is true for the case of SCR23 to SCR24. Therefore, the present invention can provide a uniformly distributed current and a symmetrical equivalent circuit, so that the high-voltage M0S power The SCR elements inside the crystal can be turned on simultaneously, which overcomes the problem that the SCR elements inside the conventional high-voltage MOS transistor cannot be turned on at the same time, which greatly improves the anti-ESD resistance of the high-voltage MOS transistor. The effectiveness of the conventional technology in anti-ESD capability is 1. The machine model method (MM) and the human body model method (HBM) are used to test the present invention and the conventional technology, and the individual test results are used to describe the present invention. Advantages.

Page 11 449780 V. Description of the invention (9) Figure 3 shows the results of the test of the present invention and the conventional technology using the machine model method (Μ! Ί). This test method is to increase the test voltage by 50 V for each test, and check whether the high-voltage NMOS transistor is damaged. As shown in Table 1. The first is the conventional technique ', which does not have a doped p + heavily doped region on its source; the second is the invention' further doped a p + heavily doped region on its source. When the machine model method (MM) test is used, the conventional technology (item 1) has no static damage at 3 5 ν ', but the electrostatic damage occurs at 400V, and the present invention (item 2) ) No static damage occurs at 800V, and no static damage occurs until 850V. Similarly, the third item is a conventional technique, and the source electrode is not doped with a P + heavily doped region; the fourth item is the present invention, and the source electrode is additionally doped with a P + heavily doped region. Conventional technology (item 3) does not occur static damage at 300V, but electrostatic damage occurs at 35ov 'and the present invention (item 4) does not occur static damage at 350V' to Static damage occurs only at 400V. , ▲ Figure 4 shows the test results of the present invention and the conventional technology using the human body model method (ΗBM). This test method is to increase the test voltage by 500 ν for each test and check whether the high-voltage NMOS transistor is damaged. As shown in table 2. The first item is a conventional technique, and the source electrode is not doped with a p + heavily doped region; the second item is that the invention is further doped with a p + heavily doped region. When using the Human Body Model (ΗBM) test, the conventional technique (item j) did not generate static electricity at 4600 ν, but the situation of static lightning occurred at 6500V, and In the present invention (item 2), there is still no issue of static electricity / static electricity at 8 :. In the same way, the outline is a conventional technology, the source of which does not have an electric two; multiple hetero regions; the fourth item is the present invention 'and its source is additionally doped with p + concentrated doping

Item 3) Immediately static electricity occurs > Ability to charge electricity from above is not used to limit the spirit of protection 449780 V. Description of Invention (发明)). Also using the human body model (ΗBM) test, the conventional technology (no electrostatic damage occurs at 500GV, but the electricity is not known at 5500V, and the present invention (item 4) does not occur at 65 () 0v, In a bad situation, the electrostatic damage does not occur until 7000v. {Experimental results show that the use of the transistor of the present invention has better static resistance than the conventional technology.-Although the present invention is disclosed in a preferred embodiment As above, it is clear that any familiarity with this skill will not depart from the two or two; a little modification and retouching, so the scope of the patent scope of the patent attached to this document shall prevail.

Claims (1)

449780 VI. Application for patent scope 1. A kind of high-voltage power electronics with silicon-controlled rectification type electrostatic protection element, including: a first plastic semiconductor substrate with a second type well region; a second type drain region by The second honeywell region is composed of a second-type source region formed in the first-type semiconductor substrate; a high-voltage power-type gate structure formed in the second-type source region and the second-type drain. Between regions; Λ a second type first heavily doped region formed in the second type well region; a first type first heavily doped region formed in the second type first-doped region &Quot; —a first type second heavily doped region, a second type second heavily doped region, and a first type semiconductor substrate; and a first type third heavily doped region periphery, 'formed in the second type In the source region; 'formed in the outer area of the second type well area' is formed in the first plastic and second condensate. It is said that the first and second area of the semiconductor substrate is composed of the Heya area, the Zhuodi type 1 ascending area, and the Zidi 1 semiconductor substrate. Type I bipolar transistor, and type source region, the first type semiconductor = two and second type bipolar transistor , A protective element composed of two ^! Open ^, and a second type composed of the first type ^ first first silicon-controlled rectification type electrostatic protection semiconductor substrate; the second type; Well flow type electrostatic protection element. Male body, both form a second silicon controlled rectifier 44978 0 VI. The scope of patent application where the first where the first where the second where the j or m '] special, the transistor described in the first item in the scope Ί *' What is the second type? Polite conduct type. 3. If the patent type of the application is a P-type conductive type, the certificate page is respectful. ^ ^ The second type is an N-type conductive type. However, in the transistor-type well region described in item 3 of the Lee Van Park, to f include-the second type of the heavily doped region. Type I: I: The transistor described in item 1 of the 范围 Li range, ☆ T 米 Mi Lei soil & /, The first type of the second heavily doped interval forms a first parasitic resistance. The transistor described in Item 1 of the patent application, wherein the first bulk substrate and the first type of third heavily doped region form a second parasitic resistance. The transistor according to item 1 of the patent application park, wherein the resistance value of the first resistor is substantially equal to the resistance value of the second parasitic resistor. ~ The transistor as described in item 7 of the scope of the patent application, wherein the second type doped region in the second region and the second type well interval form a third para-doping. In the transistor described above, the concentration of the rich / heterogeneous regions is higher than that of the first type conductor substrate and the second type well region. 10. The transistor according to item 9 of the scope of the patent application, wherein the rich / hetero regions are separated by an insulating layer. The transistor according to item 9 of the scope of patent application, wherein the first and third heavily doped regions serve as a guard ring. 12 · —A kind of high-voltage power f 449780 6. The scope of patent application includes a first plastic semiconductor substrate with a second-type hafnium region; a type-two non-polar region 'is composed of the second-type well region; a f-type source region, Formed in the first-type semiconductor substrate; a first-type open-electrode structure is formed between the second-type source region and the second-type drain region; a pair of $ 2-type first heavily doped regions, Is formed in the second type well region; a first type first heavily doped region is formed between the pair of second hetero-regions; and the above-mentioned second type heavily doped region is formed In the second-type source region; a first-type second heavily doped region formed in the second-type well first-type semiconductor substrate; and a peripheral second heavily-doped well region and the body, And a rectifier-type static second-type well-transistor controlled by the type-well region, the substrate and the first form a second ', wherein the first-type second heavily doped region is formed at the periphery of the second-type region to A first type bipolar transistor second type source composed of the first type first heavily doped region and the second type semiconductor substrate Area, the first type semiconductor substrate, and the second type of second type bipolar transistor 'both form a first silicon electrical protection element, and the first type first-concentrated doped area, the area, A first type double-carrier composed of the first type semiconductor substrate and a second type double-carrier transistor composed of the second type second heavily doped region and the first type semiconductor second type well region, both Shi Xikong rectifier type electrostatic protection element. 13. According to item 12 of the scope of patent application-the type is an N-type conductive type, and the second type is a p-type conductive type. Page 16 449780 6 'Patent Application Range 1 4. The transistor described in item 12 of the patent application range, wherein the first type is a P-type conductive type and the second type is an N-type conductive type. 15. The transistor according to item 12 of the scope of patent application, wherein the second type well region includes at least a pair of second type first heavily doped regions. 16. The transistor according to item 12 of the scope of patent application, wherein the first type and third heavily doped region serves as a guard ring. 1 7. The transistor according to item 16 of the scope of the patent application, wherein the first type semiconductor substrate and the first type third heavily doped interval serving as a guard ring form a first parasitic resistance. 18. The transistor according to item 12 of the scope of the patent application, wherein the first type semiconductor substrate and the first type second heavily doped region form a second parasitic resistor. 19. The transistor according to item 18 in the scope of the patent application, wherein the resistance value of the second parasitic resistor is substantially equal to the first parasitic resistance 20. The transistor according to item 19 in the scope of patent application Each of the second-type first heavily doped regions in the second-type well region and the second-type well interval forms a third parasitic resistance. 2 1. The transistor according to item 20 of the scope of patent application, wherein the concentration of the heavily doped regions is higher than that of the first type semiconductor substrate and the second type well region. 2 2. The transistor according to item 21 of the patent application, wherein the heavily doped regions are separated by an insulating layer. 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