14856 8 5 8 2 4 rf.doc/008 A7 B7 經濟部智慧財產局8工消費合作社印製 五、發明説明（f ) 本發明是有關一種半導體元件之結構，且特別是有關 於一種鐵電非揮發性記憶單元（Ferroelectric Non-volatile Memory Unit)之結構。 由於非揮發性記憶體（Non-vo丨atile Memory)內儲存的 資料在無電流時仍可保存，且其體積小、速度快而不怕振 動，所以應用日趨廣泛。習知常見的非揮發性記憶體有”可 抹除且可程式唯讀記憶體」（Erasable Programmable ROM ; EPROM)，「可電除且可程式唯讀記億體」（Eiectncally Erasable Programmable ROM ; E2PROM)，以及快閃記憶體 (Flash Memory)等等。上述三種非揮發性記憶體之結構主 要爲浮置閘極（Floating Gate)、浮置閘極上方的控制閘極 (Control Gate) ’以及浮置閘極與控制閘極之間的介電層 (Dielectric Layer)。上述三 種非揮發性記憶體皆是藉陷入 浮置聞極中的電子來保存資料，其寫入/抹除（Write/Erase) 資料時係使用控制閘極將電子注入/拉出浮置閘極，而讀 取記憶體中的資料時須在控制閘極上加工作電壓。然而， 這三種非揮發性記憶體各有一些問題，敍述如下= 其一，由於EPROM中的資料係以紫外光照射之方式 消除，故欲更改資料時，必須先一次抹除全部的資料，再 寫入更新之資料，而無法選擇性地更改資料。此外，由於 EPROM的外包裝須預留紫外線照射的窗口（wind〇w)，使 得包裝（Packing)上亦有不便。 另外，E2PR〇M與快閃記憶體的問題是寫入/抹除資料 的工作電壓甚高，一般會達到12V，不僅會增加耗電量， 本纸張尺度適用中國國家榡準（CNS ) A4規格（210X297公釐） --!"!1^----装------訂------嚷 (請先閲讀背面之注意事項再填寫本頁) A7 B7 448568 5824twf,doc/0〇8 五、發明説明（">) 且會縮短元件的壽命。 再者，快閃記憶體的另一個問題是欲更改資料時，必 須先一次抹除全部的資料，再寫入更新之資料，而無法選 擇性地抹除資料。 此外’由於上述三種非揮發性記憶體在讀取資料時， 皆須在控制閘外加工作電壓，因此會增加額外的耗電量。 除了以上三種非揮發性記憶體之外，近來還有一種鐵 電非揮發性記憶體，其結構爲二層鈿（Pt)電極板包夾一層 鐵電材料，且其中的下鉑電極板位於矽基底之上。此習知 之鐵電非揮發性記憶體係利用二層鋁電極板上的偏壓來改 變其中間之鐵電材料的極化値(Polarization)，此極化値之 變化會影響下鉑電極板下方通道之開/關，也就是會改變 此鐵電非揮發性記憶體中的資料値。接著，當此鐵電非揮 發性記憶體之二層鉑電極板上的偏壓消失後，則利用其中 鐵電材料的殘餘極化（Residual Polarization)特性，來保持 偏壓存在時通道之開/關狀態，也就是藉此殘餘極化作用 來儲存此鐵電非揮發性記憶體的資料値。 然而，這種鐵電非揮發性記憶體有一些缺點，略述如 下°其一，鋁電極板易與下方矽基底反應而生成矽化鉑 ,(PtSix)。另外，基底的矽容易經由鉑電極板擴散至鐵電材 料層中，而使鐵電材料層之結晶性（Crystallinity)降低，以 致減低鐵電材料層之品質。再者，因爲鉑金屬有顯著的電 荷屏蔽作用，所以下鈉電極板下方之通道難以產生。 本發明提出一種鐵電非揮發性記憶單元之結構，其可 4 --------------ί衣 f-----訂-------1 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS > A4規格（2丨οχ297公釐） A7 B7 448568 5824twf. doc/008 五、發明説明（3) 以改善EPROM ' E2PROM、快閃記憶體三者之寫入/抹除 工作電壓過高，讀取時須於控制閘極外加工作電壓，和無 法選擇性更改資料等問題；以及習知鐵電非揮發性記憶體 之下鉑電極板易與矽基底反應，基底的矽易污染到鐵電材 料層，和下鉑電極板下方之通道不易形成等問題。 本發明所提出之鐵電非揮發性記憶單元之結構適用於 一基底’其中包括一*慘雜井、一隔離層（Field Isolation)、 一閘介電層（Gate Dielectric)、由一鐵電材料層與一控制閘 極所組成之閘極結構、一源極/汲極區、以及一濃摻雜區。 其中，摻雜井位於基底之中，隔離層位於摻雜井周圍，閘 介電層位於摻雜井之上，鐵電材料合位於閘介電層之上， 控制閘極位於鐵電材料層上方，源極/汲極區位於閘極結 構兩側之摻雜井中，而濃摻雜區則位於源極/汲極區與隔 離層之間的摻雜井中，此濃摻雜區之摻雜型態與摻雜井相 同’且此濃摻雜區之摻雜濃度大於摻雜井之摻雜濃度。 在操作原理方面，本發明之鐵電非揮發性記憶單元主 要係藉由鐵電材料特有的殘餘極化（Residual Polarization) 現象’以致在無電流時仍能保存其中資料。當欲更改本發 明之鐵電非揮發性記憶單元中所儲存的資料時，係施加第 一電壓於控制閘極上，並施加第二電壓於濃摻雜區上。此 時，藉由第一電壓與第二電壓之電位差，即能改變鐵電材 料層之極化値，而使閘介電層下方之通道(Channel)所帶的 電荷改變，即是使通道呈開/關狀態，也就是寫入資料値0 或1。 5 本紙張尺度適用中國国家榡準（CNS) Α4胁（21〇><297公着） -------Λ------訂------嘷 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 / A7 B7 448568 5824twf.doc/〇〇8 五、發明説明（π ) 接著，當第一電壓與第二電壓所造成之電位差消失 後，鐵電性材料仍會保留比電位差存在時之極化値稍小的 殘餘極化値，此殘餘極化値仍會影響閘介電層下方通道所 帶之電荷，而能使通道保持在加電壓時的開/關狀態。因 此，本發明之鐵電非揮發性記憶單元在無電流時仍能保存 資料。此外，在讀取本發明之鐵電非揮發性記憶單元中的 資料時，係於控制閘極與濃摻雜區皆未施電壓的情形下， 以通道之開/關作爲資料値0/1的判讀依據。 如上所述，由於在更改本發明之鐵電非揮發性記憶單 元中的資料値時，僅藉由操控鐵電材料層之殘餘極化値的 方式，而非注入/拉出電子的方式，故只須比EPROM、 E2PROM、與快閃記憶體低上許多的工作電壓，而得以減 少耗電量，並增加元件之壽命。另外，由於在讀取本發明 之鐵電非揮發性記憶單元中的資料時，不必於控制閘極外 加工作電壓，故能再降低耗電量。 另外，在使用本發明之鐵電非揮發性記憶單元時，只 要在控制閘極上施加第一電壓，並在濃摻雜區上施加第二 電壓，即可更改特定記憶單元的資料値。因此，本發明之 鐵電非揮發性記憶體可以選擇性地更改資料，不像EPROM 與快閃記憶體般必須先一次抹除全部的資料，才能輸入更 新後的資料。 除此之外，如與習知二層鈿電極板包夾一層鐵電材料 之鐵電非揮發性記憶體相較’由於本發明之鐵電非揮發性 記憶單元之控制閘極僅位於鐵電材料層之上，而非位於基 6 本紙張尺度適用中國國家標準（CNS > A4規格（21〇X：297公釐） -----------4------訂------41 (請先聞讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作杜印製 A7 B7 448568 5824twf.doc/008 五、發明説明（t) 底之上，所以不用考慮控制閘極與矽基底反應的問題。另 外，在本發明之鐵電非揮發性記憶單元中，由於鐵電材料 層與矽基底之間係以閘介電層相隔，而基底中的矽不易穿 透閘介電層而進入鐵電材料層，所以可避免鐵電材料層之 結晶性受到破壞，而能提升鐵電材料層之品質。再者，由 於鐵電材料層與基底之間係以閘介電層相隔，故不會有習 知技藝中鉛電極板的電荷屏蔽問題，使得基底中的通道容 '易形成。 總結來說，與EPROM、E2PROM、及快閃記憶體相較， 本發明之鐵電非揮發性記憶體之寫入/更改資料値的工作 電壓低，且讀取時不需在控制閘極外加工作電壓，故能增 加元件的壽命，且能降低元件的耗電量。而與EPROM與 快閃記憶體相較時，本發明之鐵電非揮發性記憶體則有可 以選擇性更改資料値的好處。另外，如與習知鐵電非揮發 性記憶體相較，本發明之鐵電非揮發性記憶體則有以下優 點：可以避免控制閘極與矽基底反應，可以避免基底的矽 污染到鐵電材料層，以及使通道易於形成等等。 爲讓本發明之上述目的、特徵、和優點能更明顯易懂， 下文特舉一較佳實施例，並配合所附圖式，作詳細說明如 下： 圖式之簡單說明： 第1圖所繪示爲本發明之較佳實施例中，鐵電非揮發 性記憶單元之結構。 第2A圖所繪示爲由<100>方向所見之鉛锆酸鈦（PZT) 7 ---rl—.l----A------訂------嗓 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作杜印製 本紙張尺度適用中國國家標準（CNS)A4規格（210X297公釐）~ ~"" 經濟部智慧財產局8工消費合作社印製 448 56 8 A7 5824twf.doc/008 五、發明説明（L ) 單位晶格(Unit Cell)的結構。第2B-2C圖顯示電場對PZT 單位晶格中的Τβ位置，以及電場對單位晶格之電偶極 (Electric Dipole)方向的影響。 第3圖所繪示爲鐵電材料之電滯曲線（Hysteresis Curve)，其顯示出控制閘極與濃摻雜區之電位差變化對鐵 電材料之極化値及殘餘極化値的影響。. 第4A-4C圖所繪示爲本發明之較佳實施例中，鐵電非 揮發性記憶單元之操作原理示意圖。 圖式之標號說明： 100 :基底 102 :隔離層 11 〇 :摻雜井 120 :閘介電層 130 :鐵電材料層 140 :控制閘極 142 :阻擋層 150 :間隙壁 160 :源極/汲極區 170 :濃摻雜區 1 80 :閘極結構 210、220 :電偶極 Λ、hA :極化値 Λ，、户3,殘餘極化値 Ah、Ar2、AG :電位差 8 (請先閱讀背面之注意事項再填寫本頁) 訂 本紙張尺度適用中國國家標準（CNS ) A4現格（210XW7公釐） 經濟部智慧財產局員工消費合作社印製 4 48 5 6 8 A7 5824twftdoc/008 d /五、發明説明（？） F,、Κ2 :電壓 較佳實施例說明 請參照第1圖，其所繪示爲本發明之較佳實施例中， 鐵電非揮發性記憶單元之結構。此結構包含基底100、隔 離層102、摻雜井110、閘介電層120、鐵電材料層130、 控制閘極140、間隙壁150、源極/汲極區160、以及濃摻 雜區170。 在上述之鐵電非揮發性記憶單元的各部分中，鐵電材 料層130、控制閘極140、以及間隙壁150合稱閘極結構 180，摻雜井110位於基底100之中；隔離層102位於摻 雜井Π0周圍；閘介電層120位於摻雜井110之上；鐵電 材料層130位於閘介電層120之上；控制閘極140位於鐵 電材料層130上方；間隙壁150位於鐵電材料層130與控 制閘極140之側壁；源極/汲極區160位於閘極結構180 兩側的摻雜井Π0之中；而濃摻雜區170係位於源極/汲 極區160與隔離層102之間的摻雜井110中： 另外，在上述之鐵電非揮發性記憶單元的各部分中， 隔離層102例如爲氧化矽材質之淺溝渠隔離層。當此記憶 單元爲Ν通道元件時，摻雜井110之摻雜型態爲Ρ型；當 此記憶單元爲Ρ通道元件時，摻雜井Π0之摻雜型態爲Ν 型。聞介電層120例如爲以熱氧化法（Thermal Oxidation) 所形成之氧化矽層，濃摻雜區170之摻雜型態與摻雜井110 之摻雜型態相同，且濃摻雜區170之摻雜濃度大於摻雜井 110之摻雜濃度。 9 本紙張尺度適用中國國家標準（CNS)A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 4 48 56 8 __^2"wf.doc/00S B7 " —— . __ 五、發明説明（1 ) 此外’上述之控制閘極14〇例如爲一多晶较層 (Polysilicon)或一金屬層，而此金屬層之材質例如爲鋁 (Aluminum)或鈾（Platinum)。當控制閘極14〇之材質爲多 晶矽或鋁時，尙須於鐡電材料層丨3〇與控制閘極mo之間 形成一層阻擋層142，如第丨圖所示，以防止控制閘極14〇 對鐵電材料層130造成破壞。當控制閘極140爲一多晶砂 層時’阻擋層丨42爲厚度5〇A〜6〇A之一氧化砂層，其目 的係爲防止多晶矽材質之控制閘極140與鐵電材^層13〇 發生反應，以免破壞鐵電材料層130的結晶性。.另外，當 控制閘極M0之材質爲鋁時，阻擋層M2則爲厚、虔 5〇〇A〜6〇〇A之一氮化鈦（TiN)層’其係作'爲一阻障層(Barrier Layer)以防止鋁材質之控制閘極140產生尖峰現象 (Spiking)，以免破壞鐵電材料層Π0。 除此之外’在本發明之鐵電非揮發性記憶單元結構 中，鐵電材料層130的材質例如爲鉛銷酸鈦（(pb^;ri_x)_ ΤΑ ; PZT)、SrBl2Ta209(SBT)、以及鉛鈮锆酸鈦 ((PbxNbyZr^.yynO:, ; PNZT)。這些鐵電材料的共同特徵是 其單位晶格在電場下會形成偶極矩甚大的電偶極，且皆具 有顯著的電滯特性，此處僅以PZT爲例說明如下。 請參照第2A圖，其所繪示爲由<100>方向所見之PZT 單位晶格的結構。在常溫下，PZT之單位^格爲矩形晶格， 且爲一面心（Face Center)結構，其中骨架原子（Framework Atom) Pb與Zr係位於單位晶格的角落（Corner)，◦原子係 位於單位晶格的面心位置；而非骨架(non_Framework)的四 10 本紙張尺度適用中國國家標準（CNS ) A4说格（210X297公釐） ---1----,水------ir------^ I (請先閱讀背面之注意事項再填寫本I) A7 B7 5824twf.doc/008 五、發明説明（1 ) 價鈦離子（Ti4+)則位於單位晶格的體々(Body Center)位置。 請參照第2B圖，當PZT材料處於電場中時，單位晶 格中的·Π4+會依電場方向改變其位置，而使單位晶格形成 與電場方向同向的電偶極。如第2Β圖所示，當電場爲戽 時（第2Β圖左邊箭頭方向），Ti4+會往電場方向移動至位置 A ’此時單位晶格即等同於圖右所示之電偶極210，其指 向（由負到正）與電場方向相同。 反之，請參照第2C圖，當電場方向爲與尽相反之艮 時(第2C圖左邊箭頭方向），Ti4+移動方向即相反而移至位 置B，且單位晶格之電偶極220的指向（由負到正）亦與尾 相同。當電場之大小與方向隨時間改變時，鐵電材料單位 晶格的電偶極變化會有一種電滯現象（Hysteresis)。如以鐵 電材料層130之整體來看，即表示電場改變時’鐵電材料 層130之極化値變化會表現出電滯現象，下文中將對此電 滯現象作詳細之說明。 請參照第3圖，其所繪示爲一般鐵電材料之電滯曲線， 顯示出鐵電材料層130兩端之電位差（〇(鐵電材料層130 中的電場強度與此電位差成正比）的變化與鐵電材料極化 値(//C7cm2，其中C1爲庫侖（Coulomb))及殘餘極化値之關 係。如第3圖與第1圖所示，當鐵電材料層130兩端之起 始電位差爲ΔΚ時，鐵電材料之極化値爲& ;當電位差由 漸減時，鐵電材料之極化値會循箭號方向變小；而當 電位差爲0時，則會殘留殘餘極化値（Residual Polarization)/^ 〇 11 -------------A------訂------Ψ {請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙浪尺度適用中國固家榡隼（CNS ) A4规格（210x297公釐） 448568 5 8 2 4 ,d o c / 〇 〇 8 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（ο ) 另外，當開始電位差爲比ΔΚ,大的AK2時，極化値& 之値也比P,大’且在一定電位差範圍內，極化値約與電 位差成正比，即;當電位差由漸減至1 時，極化値即隨箭號方向禮小，而留下殘餘極化値p ， 其値亦比Pu大’且户°另外，當電位产爲 負値之Δ6時，鐵電材料之極化値爲負値之^ ;當電位差 由Δ6漸增時，鐵電材料之極化値即循箭號方向變化；當 電位差爲〇時，還會殘留負値之殘餘極化値ρ^。本發曰^ 之鐵電非揮發性記憶單元即是利用鐵電材料的電'滯丨生胃$ 記憶資料，下文中將對其操作情形作詳細說曰月。 請參照第4A-4C圖’其所繪示爲本發明之較佳實施例 中，鐵電非揮發性記憶單元之操作情形的示意圖，其中第 4Α圖所繪示爲此鐵電非揮發性記億單元的等效電路。如 第4A-4C圖所示’當欲更改本發明之鐵電非揮發性記憶單 元中資料時，係於控制閘極140上施以電壓，並在濃 摻雜區Π0上施以電壓h。另外，在此第4B_4C圖中， 鐵電材料層Π0感應到其兩端電位差時的電偶極指向約與 閘介電層120及控制閘極140之平面垂直。如以ρΖΤ材質 之鐵電材料爲例，即表示其單位晶格的<001>方向，即單 位晶格之長軸方向與閘介電層120及控制閘極140之平面 垂直。另外，爲淸楚顯示鐵電材料之極化方向的變化，在 第4B與4C圖中所示之鐵電材料層130中，電偶極的大小 比例(等於一個單位晶格的大小比例)遠大其真正比例。 此處僅以N通道之元件爲例，說明本發明較佳實施例 ----ί -----,水------、1Τ------球 (諸先閲讀背而之注意事項再填寫本頁) 本紙張尺度適用中國國家榡準（CNS ) A4规格（210X297公釐) 經濟部智慧財產局負工消費合作杜印製 448 5 6 8 5824 twf.doc/008 ---_— β2____ 五、發明説明（L () 之鐵電非揮發性記憶單元的操作原理。請同時參照第4A 與4B圖，其中第4B圖所繪示爲n通道鐵電非揮發性記 億單元之通道打開時的情形。如第4A圖所示，當控制閘 極M0所施電壓F,大於濃摻雜區17〇所施電壓匕時，即 鐵電材料層130上下之電位差ΔΡ12(Ξκ_ί/2)爲正値時， 其中每一個單位晶格皆會形成與電場方向相同的電偶極， 亦即指向朝下的電偶極，而閘介電層下方的通道區也 會感應出負電荷。如果此正電位差AF,2之値夠大，使得 單位晶格之極化値夠大，即使得通道區之負電荷夠多，便 成使N型通道打開。反之，如果正電位差之値不夠 大，甚或ΔΚ12爲負値時’則通道不會打開。例如，請參 照第4C圖，當Ν型鐵電非揮發性記憶單元的控制閘極ι4〇 所施電壓h小於濃摻雜區170所施電壓h時，通道區會 帶有正電荷，而使N型通道關閉。因此，經由控制閘極14〇 所施電壓之變化，即可達成更改資料値之目的。 接著，請參照前文中對鐵電材料之電滯特性的說明， 並比對第3圖。由於在鐵電材料層130兩端電位差消失後， 鐵電材料層130中尙留有一殘餘極化値，其値略小於電位 差存在時的極化値，所以當先前外加之電位差夠大，而使 得殘留極化値夠大時，即可在元件不通電的情形下’保持 通電時通道打開的狀態，也就是說可以保存資料値(0/1中 的一個）。反之，如殘餘極化値不夠大，或爲負値時’則 通道會一直保持關閉的狀態，也就是可以保存與開啓狀態 資料値相異之另一資料値。另外，在讀取本發明之鐵電非 13 本紙張尺度適用中_國家標準（CNS ) A4规格（210X297公麓） ---^----±衣------’玎------^ (請先閲讀背面之注意事項再填寫本頁) A7 B7 經濟部智慧財產局員工消費合作社印製 448 56 814856 8 5 8 2 4 rf.doc / 008 A7 B7 Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and printed by the 8th Industrial Cooperative Cooperative V. Description of the Invention (f) The present invention relates to the structure of a semiconductor element, and in particular to a ferroelectric Structure of a volatile memory unit (Ferroelectric Non-volatile Memory Unit). As non-volatile memory (Non-vo 丨 atile Memory) data can be stored in the absence of current, and its small size, fast speed without fear of vibration, it is increasingly widely used. Common non-volatile memories include "erasable and programmable read-only memory" (Erasable Programmable ROM; EPROM), and "electrically programmable and read-only memory" (Eiectncally Erasable Programmable ROM; E2PROM ), And Flash Memory. The structures of the above three non-volatile memories are mainly a floating gate, a control gate above the floating gate, and a dielectric layer between the floating gate and the control gate ( Dielectric Layer). The three types of non-volatile memory mentioned above are stored by the electrons trapped in the floating sense electrode. When writing / erasing data, the control gate is used to inject / pull electrons out of the floating gate. When reading the data in the memory, a working voltage must be added to the control gate. However, each of the three non-volatile memories has some problems, which are described as follows: First, because the data in the EPROM is erased by ultraviolet light, you must erase all the data at one time before changing the data. Write updated data without selectively changing the data. In addition, since the outer package of EPROM must be reserved with a window (window) for ultraviolet irradiation, there is also inconvenience in packaging. In addition, the problem with E2PROM and flash memory is that the working voltage for writing / erasing data is very high, which will generally reach 12V, which will not only increase power consumption. This paper is applicable to China National Standards (CNS) A4 Specifications (210X297mm)-! &Quot;! 1 ^ ---- install -------- order ------ 嚷 (Please read the precautions on the back before filling this page) A7 B7 448568 5824twf , doc / 0〇8 5. Description of the invention (" >) and shorten the life of the component. In addition, another problem with flash memory is that if you want to change the data, you must erase all the data at once, and then write the updated data. You cannot selectively erase the data. In addition, because the three non-volatile memories mentioned above all need to apply a working voltage to the control gate when reading data, additional power consumption will be added. In addition to the above three non-volatile memories, recently there is also a ferroelectric non-volatile memory, which is structured as a two-layer rhenium (Pt) electrode plate sandwiching a layer of ferroelectric material, and the lower platinum electrode plate is located in silicon Above the substrate. This conventional ferroelectric non-volatile memory system uses the bias voltage of the two-layer aluminum electrode plate to change the polarization (Polarization) of the intermediate ferroelectric material. This change in polarization will affect the channel below the lower platinum electrode plate. On / off, it will change the data in this ferroelectric non-volatile memory. Then, when the bias voltage on the two-layer platinum electrode plate of the ferroelectric non-volatile memory disappears, the residual polarization characteristic of the ferroelectric material is used to maintain the channel open / Off state, that is, the data of this ferroelectric non-volatile memory is stored by residual polarization. However, this ferroelectric non-volatile memory has some disadvantages, as briefly described below. For one, the aluminum electrode plate easily reacts with the underlying silicon substrate to generate platinum silicide (PtSix). In addition, the silicon in the substrate is easily diffused into the ferroelectric material layer through the platinum electrode plate, and the crystallinity of the ferroelectric material layer is reduced, so that the quality of the ferroelectric material layer is reduced. Furthermore, because platinum has a significant charge shielding effect, it is difficult to generate channels under the sodium electrode plate. The present invention proposes a structure of a ferroelectric non-volatile memory unit, which can be 4 -------------- ί clothing f ----- order --------- 1 (please (Please read the notes on the back before filling this page) The paper size printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs applies to Chinese national standards (CNS > A4 size (2 丨 οχ297 mm) A7 B7 448568 5824twf. Doc / 008 5 3. Description of invention (3) To improve the writing / erasing working voltage of EPROM 'E2PROM and flash memory, the working voltage must be added to the control gate when reading, and the data cannot be selectively changed; And the conventional platinum electrode plate under the ferroelectric non-volatile memory is easy to react with the silicon substrate, the silicon on the substrate is easy to contaminate the ferroelectric material layer, and the channels under the lower platinum electrode plate are not easy to form. The structure of the ferroelectric non-volatile memory unit is suitable for a substrate, which includes a miscellaneous well, a field isolation layer, a gate dielectric layer, a ferroelectric material layer and a control gate. Gate structure, a source / drain region, and a heavily doped Where the doped well is located in the substrate, the isolation layer is located around the doped well, the gate dielectric layer is positioned above the doped well, the ferroelectric material is positioned above the gate dielectric layer, and the control gate is positioned above the ferroelectric material layer. The source / drain regions are located in the doped wells on both sides of the gate structure, while the heavily doped regions are located in the doped wells between the source / drain region and the isolation layer. It is the same as the doped well, and the doped concentration of this heavily doped region is greater than the doped concentration of the doped well. In terms of operating principle, the ferroelectric non-volatile memory cell of the present invention is mainly made by the residual characteristic of the ferroelectric material. Residual Polarization phenomenon 'so that the data can be stored when there is no current. When you want to change the data stored in the ferroelectric non-volatile memory unit of the present invention, a first voltage is applied to the control gate, and A second voltage is applied to the heavily doped region. At this time, the potential difference between the first voltage and the second voltage can change the polarization of the ferroelectric material layer, and make the channel below the gate dielectric layer The change in the charge is to make the It is on / off, that is, write data 値 0 or 1. 5 This paper size is applicable to China National Standards (CNS) Α4 threat (21〇 > < 297 public) ------- Λ- ----- Order ------ 嘷 (Please read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs / A7 B7 448568 5824twf.doc / 〇〇8 V. Invention Explanation (π) Then, after the potential difference caused by the first voltage and the second voltage disappears, the ferroelectric material will still retain a slightly smaller residual polarization than the polarization when the potential difference exists, and this residual polarization will still be Will affect the charge on the channel under the gate dielectric layer, and can keep the channel on / off when the voltage is applied. Therefore, the ferroelectric non-volatile memory unit of the present invention can retain data even in the absence of current. In addition, when reading the data in the ferroelectric non-volatile memory cell of the present invention, when the control gate and the heavily doped region are not applied with voltage, the channel on / off is used as the data. 0/1 The basis of interpretation. As described above, when changing the data volume in the ferroelectric non-volatile memory cell of the present invention, only the manner of controlling the residual polarization of the ferroelectric material layer is used, rather than the manner of injecting / pulling out electrons. It only needs a much lower operating voltage than EPROM, E2PROM, and flash memory to reduce power consumption and increase component life. In addition, when reading the data in the ferroelectric non-volatile memory cell of the present invention, it is not necessary to apply an operating voltage to the control gate, so the power consumption can be reduced again. In addition, when using the ferroelectric non-volatile memory cell of the present invention, as long as a first voltage is applied to the control gate and a second voltage is applied to the heavily doped region, the data of a specific memory cell can be changed. Therefore, the ferroelectric non-volatile memory of the present invention can selectively modify data, unlike EPROM and flash memory, which must erase all data at once before inputting updated data. In addition, compared with the conventional ferroelectric non-volatile memory in which a layer of ferroelectric material is sandwiched by the conventional two-layer rhenium electrode plate, since the control gate of the ferroelectric non-volatile memory unit of the present invention is located only in the ferroelectric Above the material layer, not on the base 6 This paper size applies the Chinese national standard (CNS > A4 specification (21 ×: 297 mm)) ----------- 4 ------ Order ------ 41 (Please read the notes on the back before filling out this page) Consumption Cooperation by Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by A7 B7 448568 5824twf.doc / 008 V. Description of Invention (t) Therefore, it is not necessary to consider the problem of controlling the reaction between the gate and the silicon substrate. In addition, in the ferroelectric non-volatile memory cell of the present invention, since the ferroelectric material layer and the silicon substrate are separated by a gate dielectric layer, the substrate The silicon in it is difficult to penetrate the gate dielectric layer and enter the ferroelectric material layer, so the crystallinity of the ferroelectric material layer can be prevented from being damaged, and the quality of the ferroelectric material layer can be improved. Furthermore, because the ferroelectric material layer and the substrate They are separated by a gate dielectric layer, so there is no problem of the charge shielding of the lead electrode plate in the conventional technology. The channel capacity in the substrate is easy to form. In summary, compared with EPROM, E2PROM, and flash memory, the write / modify data of the ferroelectric non-volatile memory of the present invention has a lower operating voltage, and It is not necessary to add an operating voltage to the control gate when reading, so it can increase the life of the component and reduce the power consumption of the component. Compared with EPROM and flash memory, the ferroelectric non-volatile memory of the present invention It has the advantage of being able to selectively change the data frame. In addition, compared with the conventional ferroelectric non-volatile memory, the ferroelectric non-volatile memory of the present invention has the following advantages: it can avoid controlling the gate and silicon The substrate reaction can avoid silicon contamination of the substrate to the ferroelectric material layer, and facilitate the formation of channels, etc. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below. In conjunction with the accompanying drawings, detailed descriptions are as follows: Brief description of the drawings: Figure 1 shows the structure of a ferroelectric non-volatile memory unit in a preferred embodiment of the present invention. Figure 2A shows For < 100 > Leading titanium zirconate (PZT) seen in the direction 7 --- rl—.l ---- A ------ Order ------ Voice (Please read the precautions on the back before filling this page ) Consumption cooperation between employees of the Intellectual Property Bureau of the Ministry of Economic Affairs and Du Duan This paper is produced in accordance with the Chinese National Standard (CNS) A4 (210X297 mm) ~ ~ " " Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs 8 Industrial Consumer Cooperative 448 56 8 A7 5824twf.doc / 008 5. Description of the invention (L) Structure of the unit cell. Figures 2B-2C show the electric field versus the position of Tβ in the PZT unit lattice, and the electric field versus the electric dipole of the unit lattice ( Electric Dipole) direction. The hysteresis curve of the ferroelectric material is shown in Fig. 3, which shows the effect of controlling the potential difference between the gate and the heavily doped region on the polarization and residual polarization of the ferroelectric material. 4A-4C are schematic diagrams illustrating the operation principle of a ferroelectric non-volatile memory unit in a preferred embodiment of the present invention. Description of the symbols of the drawings: 100: substrate 102: isolation layer 11 〇: doped well 120: gate dielectric layer 130: ferroelectric material layer 140: control gate 142: barrier layer 150: spacer 160: source / drain Polar region 170: heavily doped region 1 80: gate structure 210, 220: electric dipole Λ, hA: polarization 値 Λ, 户 3, residual polarization 値 Ah, Ar2, AG: potential difference 8 (please read first Note on the back, please fill in this page again.) The paper size of the paper is applicable to the Chinese National Standard (CNS) A4 (210XW7 mm). Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 48 5 6 8 A7 5824twftdoc / 008 d Description of the invention (?) F, K2: Description of a preferred embodiment of voltage Please refer to FIG. 1, which shows the structure of a ferroelectric non-volatile memory unit in a preferred embodiment of the present invention. This structure includes a substrate 100, an isolation layer 102, a doped well 110, a gate dielectric layer 120, a ferroelectric material layer 130, a control gate 140, a spacer 150, a source / drain region 160, and a heavily doped region 170. . In each part of the above-mentioned ferroelectric non-volatile memory unit, the ferroelectric material layer 130, the control gate 140, and the spacer 150 are collectively referred to as the gate structure 180, and the doping well 110 is located in the substrate 100; the isolation layer 102 Located around the doped well Π0; the gate dielectric layer 120 is located above the doped well 110; the ferroelectric material layer 130 is located above the gate dielectric layer 120; the control gate 140 is located above the ferroelectric material layer 130; the spacer 150 is located The side wall of the ferroelectric material layer 130 and the control gate 140; the source / drain region 160 is located in the doped well Π0 on both sides of the gate structure 180; and the heavily doped region 170 is located in the source / drain region 160 In the doped well 110 between the isolation layer 102 and the isolation layer 102: In addition, in each part of the above-mentioned ferroelectric non-volatile memory cell, the isolation layer 102 is, for example, a shallow trench isolation layer made of silicon oxide. When the memory cell is an N-channel element, the doping pattern of the doping well 110 is P-type; when the memory cell is a P-channel element, the doping pattern of the doping well Π0 is N-type. The dielectric layer 120 is, for example, a silicon oxide layer formed by a thermal oxidation method. The doped pattern of the heavily doped region 170 is the same as the doped pattern of the doped well 110, and the heavily doped region 170. The doping concentration is greater than the doping concentration of the doped well 110. 9 This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 48 56 8 __ ^ 2 " wf .doc / 00S B7 " ——. __ V. Description of the invention (1) In addition, the above-mentioned control gate 14 is, for example, a polysilicon layer or a metal layer, and the material of the metal layer is, for example, Aluminum (Aluminum) or uranium (Platinum). When the material of the control gate 14 is polycrystalline silicon or aluminum, it is necessary to form a barrier layer 142 between the electric material layer 30 and the control gate mo, as shown in the figure, to prevent the control gate 14 〇 Damage to the ferroelectric material layer 130. When the control gate 140 is a polycrystalline sand layer, the 'barrier layer' 42 is an oxide sand layer having a thickness of 50A to 60A. The purpose is to prevent the control gate 140 and the ferroelectric material layer 130 of the polycrystalline silicon material from occurring. Reaction so as not to damage the crystallinity of the ferroelectric material layer 130. In addition, when the material of the control gate M0 is aluminum, the barrier layer M2 is a thick, titanium nitride (TiN) layer, which is one of 500A to 600A, and its system is a barrier layer. (Barrier Layer) to prevent spiking of the control gate 140 made of aluminum, so as not to damage the ferroelectric material layer Π0. In addition to this, in the ferroelectric non-volatile memory cell structure of the present invention, the material of the ferroelectric material layer 130 is, for example, lead pin titanium oxide ((pb ^; ri_x) _ TA; PZT), SrBl2Ta209 (SBT), And lead niobium titanium zirconate ((PbxNbyZr ^ .yynO :,; PNZT). The common feature of these ferroelectric materials is that their unit lattice will form an electric dipole with a very large dipole moment under an electric field, and they all have significant electrical properties. The hysteresis characteristic is explained here by taking PZT as an example. Please refer to FIG. 2A, which shows the structure of the PZT unit lattice as seen from the <100> direction. At normal temperature, the unit of the PZT is rectangular. The lattice is a face center structure, in which the framework atoms (Pb and Zr) are located at the corner of the unit lattice. The atomic system is located at the face-center position of the unit lattice; not the skeleton ( non_Framework) four 10 paper sizes are applicable to the Chinese National Standard (CNS) A4 grid (210X297 mm) --- 1 ----, water ------ ir ------ ^ I (Please Read the notes on the back before filling in this I) A7 B7 5824twf.doc / 008 V. Description of the invention (1) Valence titanium ions (Ti4 +) are located in the unit lattice body (Body Center) position Please refer to Figure 2B. When the PZT material is in an electric field, the · Π4 + in the unit lattice will change its position according to the direction of the electric field, so that the unit lattice will form an electric dipole in the same direction as the direction of the electric field. As shown in Figure 2B, when the electric field is 戽 (in the direction of the arrow on the left of Figure 2B), Ti4 + will move to the direction of the electric field to position A 'At this time, the unit lattice is equivalent to the electric dipole 210 shown on the right. Its direction (from negative to positive) is the same as the direction of the electric field. Conversely, please refer to Figure 2C. When the direction of the electric field is opposite (the direction of the arrow on the left of Figure 2C), Ti4 + moves in the opposite direction and moves to position B. The orientation (from negative to positive) of the electric dipole 220 of the unit lattice is also the same as the tail. When the magnitude and direction of the electric field change with time, there will be a kind of hysteresis when the electric dipole of the unit lattice of the ferroelectric material changes. Hysteresis. If the ferroelectric material layer 130 is viewed as a whole, it means that the polarization of the ferroelectric material layer 130 when the electric field changes will show a hysteresis phenomenon, which will be described in detail below. Please refer to Figure 3, where Shown as the hysteresis curve of a general ferroelectric material, showing the change in the potential difference across the ferroelectric material layer 130 (0 (the electric field strength in the ferroelectric material layer 130 is proportional to this potential difference) and the polarization of the ferroelectric material 値 ( // C7cm2, where C1 is Coulomb) and the residual polarization). As shown in Figure 3 and Figure 1, when the initial potential difference between the two ends of the ferroelectric material layer 130 is Δκ, the ferroelectric material The polarization 値 is &; when the potential difference decreases gradually, the polarization 铁 of the ferroelectric material becomes smaller in the direction of the arrow; and when the potential difference is 0, residual polarization (Residual Polarization) / ^ 〇 11 ------------- A ------ Order ------ Ψ (Please read the notes on the back before filling out this page) Employees ’Cooperatives, Bureau of Intellectual Property, Ministry of Economic Affairs Printed paper scales are applicable to China Gujia Ao (CNS) A4 specifications (210x297 mm) 448568 5 8 2 4, doc / 〇8 A7 B7 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs ) In addition, when the initial potential difference is AK2 larger than ΔK, the polarization 値 & is also larger than P, and within a certain potential difference range , The polarization 値 is approximately proportional to the potential difference, that is, when the potential difference decreases from 1 to 1, the polarization 値 decreases with the direction of the arrow, leaving a residual polarization 値 p, which is also larger than Pu 'and In addition, when the potential production is Δ6 of negative 値, the polarization 値 of the ferroelectric material is 値; when the potential difference gradually increases from Δ6, the polarization 値 of the ferroelectric material changes in the direction of the arrow; when the potential difference is At 0 °, a residual polarization 値 ρ ^ of negative 値 also remains. The ferroelectric non-volatile memory unit of the present invention is a memory data that uses electricity from ferroelectric materials to stagnate the stomach. The operation will be described in detail below. Please refer to FIGS. 4A-4C, which shows a schematic diagram of the operation of a ferroelectric non-volatile memory unit in a preferred embodiment of the present invention, and FIG. 4A shows the ferroelectric non-volatile memory. 100 million units of equivalent circuit. As shown in FIGS. 4A-4C, when the data in the ferroelectric non-volatile memory cell of the present invention is to be changed, a voltage is applied to the control gate 140, and a voltage h is applied to the heavily doped region Π0. In addition, in this figure 4B_4C, the orientation of the electric dipole when the ferroelectric material layer Π0 senses the potential difference between its ends is approximately perpendicular to the planes of the gate dielectric layer 120 and the control gate 140. For example, taking the ferroelectric material of ρZΤ as an example, it means the < 001 > direction of the unit lattice, that is, the long axis direction of the unit lattice is perpendicular to the planes of the gate dielectric layer 120 and the control gate 140. In addition, in order to show the change in the polarization direction of the ferroelectric material, in the ferroelectric material layer 130 shown in Figures 4B and 4C, the size ratio of the electric dipole (equal to the size ratio of a unit lattice) is very large. Its true proportions. Here, only the components of the N channel are taken as an example to illustrate the preferred embodiments of the present invention ---- ί -----, water -----, 1T ------ balls Note: Please fill in this page again.) This paper size is applicable to China National Standards (CNS) A4 size (210X297 mm). Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperation Du printed 448 5 6 8 5824 --_— β2 ____ 5. Description of the invention (L () The operating principle of the ferroelectric non-volatile memory unit. Please refer to Figures 4A and 4B at the same time, where Figure 4B shows the n-channel ferroelectric non-volatile memory When the channel of the 100 million unit is opened. As shown in FIG. 4A, when the voltage F applied to the control gate M0 is greater than the voltage applied to the heavily doped region 170, the potential difference ΔP12 above and below the ferroelectric material layer 130 ( When Ξκ_ί / 2) is positive, each of the unit lattices will form an electric dipole in the same direction as the electric field, that is, the electric dipole pointing downward, and the channel area under the gate dielectric layer will also be induced. Negative charge. If the positive potential difference AF, 2 is large enough to make the polarization of the unit lattice large enough, that is, if the negative charge in the channel region is large enough, N becomes The channel is open. On the contrary, if the positive potential difference is not large enough, or even when ΔΚ12 is negative, the channel will not open. For example, refer to Figure 4C, when the control gate of the N-type ferroelectric non-volatile memory cell is ι4〇 When the applied voltage h is less than the applied voltage h of the heavily doped region 170, the channel region will have a positive charge and the N-type channel will be closed. Therefore, by controlling the change in the applied voltage of the gate electrode 14 to change the data The purpose of 値. Next, please refer to the previous description of the hysteresis characteristics of the ferroelectric material, and compare with Fig. 3. Since the potential difference between the two ends of the ferroelectric material layer 130 disappears, a ferroelectric material layer 130 remains. Residual polarization 値, its 値 is slightly smaller than the polarization 差 when the potential difference exists, so when the previously applied potential difference is large enough to make the residual polarization 大 large enough, you can 'keep the channel on when the component is not energized'. The open state, that is, the data can be saved (one of 0/1). On the other hand, if the residual polarization 値 is not large enough, or is negative ', the channel will always remain closed, that is, you can save and Open State data (different another data). In addition, reading the ferroelectric non 13 paper sizes of the present invention is applicable _ National Standard (CNS) A4 specification (210X297 male feet) --- ^ ---- ± Clothing ------ '玎 ------ ^ (Please read the precautions on the back before filling out this page) A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 448 56 8
5824tivf.doc/〇〇S 五、發明説明q V) 揮發性記憶單元中的資料時，係直接以殘餘極化値所造成 的通道開/關來決定資料値，而不必在控制閘極14〇與濃 摻雜區170上施加工作電壓。 如上所述’由於在本發明較佳實施例之鐵電非揮發性 記憶單元中，資料値之更改係由鐵電材料層之極化値變化 來控制，而非EPROM、E2PROM、及快閃記憶體所使用之 注入/拉出電子於浮置閘極的方式，因此可以使用較低的 工作電壓，而得以減少耗電量，並增加元件之壽命。 另外，由於在本發明較佳實施例之鐵電非揮發性記憶 單元中，係利用鐵電材料的殘餘極化作用來保持通道的開 /關狀態’所以在其後的讀取動作時，控制閘極上不必施 加工作電壓，即能夠以通道之開/關來判斷資料値，因此 亦可減少耗電量。 除此之外’如與習知二層鉑電極板包夾一層鐵電材料 之鐵電非揮發性記憶體相較’由於本發明之鐵電非揮發性 記憶單兀之控制鬧極僅位於鐵電材料層之上，而非位於基 底之上’所以不用擔心控制閘極與敢基底反應的問題。另 外’在本發明之鐵電非揮發性記憶單元中，由於鐵電材料 層與矽基底之間係以閘介電層相隔，而基底中的砂不易穿 透閘介電層而進入鐵電材料層’所以可避免鐵電材料層之 結晶性受麵壞。再者’ __材料_顏之間係以 Γ甲 1介電層相隔’故不會有習知技藝中I白電極板的電荷屏蔽 問題，使得通道容易形成。 總結來説，與E PROM及快閃記憶體相較，本發明較 本紙張尺度適用中囷國家標準（CNS ) A4規格（210X297公嫠） (請先閱讀背面之注意事項再填寫本頁}5824tivf.doc / 〇〇S V. Description of the invention q V) When the data in the volatile memory unit, the data is directly determined by the channel on / off caused by the residual polarization, instead of controlling the gate 14. An operating voltage is applied to the heavily doped region 170. As described above, because in the ferroelectric non-volatile memory cell of the preferred embodiment of the present invention, changes in data are controlled by changes in the polarization of the ferroelectric material layer, rather than EPROM, E2PROM, and flash memory. The method of injecting / pulling out electrons into the floating gate used by the body can use a lower operating voltage, which can reduce power consumption and increase the life of the component. In addition, in the ferroelectric non-volatile memory cell of the preferred embodiment of the present invention, the residual polarization of the ferroelectric material is used to maintain the on / off state of the channel. Therefore, during subsequent reading operations, the control It is not necessary to apply a working voltage to the gate, that is, the data can be judged by the on / off of the channel, so the power consumption can also be reduced. In addition, 'as compared with the conventional ferroelectric non-volatile memory in which a layer of ferroelectric material is sandwiched by a conventional two-layer platinum electrode plate', Above the layer of electrical material, not on the substrate 'so don't worry about controlling the gate to react with the substrate. In addition, in the ferroelectric non-volatile memory cell of the present invention, since the ferroelectric material layer and the silicon substrate are separated by a gate dielectric layer, the sand in the substrate cannot easily penetrate the gate dielectric layer and enter the ferroelectric material. Layer ', so that the crystallinity of the ferroelectric material layer can be avoided. In addition, the __material_face is separated by a dielectric layer of Γα, so there is no problem of the charge shielding of the white electrode plate in the conventional art, which makes the channel easy to form. In summary, compared with E PROM and flash memory, the present invention is more suitable for this paper size than the Chinese National Standard (CNS) A4 specification (210X297). (Please read the precautions on the back before filling this page}
d4856 8 5 8 2 4 twf , doc/008 A7 B7 五、發明説明（b) 佳實施例之鐵電非揮發性記憶單元的寫入/抹除之工作電 壓低，且讀取時不需工作電壓，故能增加元件的壽命，且 能降低元件的耗電量。另外，與EPROM與快閃記憶體相 較時，本發明之鐵電非揮發性記憶單元具有可選擇性更改 資料的優點。再者，如與習知鐵電非揮發性記憶體相較， 本發明較佳實施例之鐵電非揮發性記憶體則有以下優點： 避免控制閘極與矽基底反應，避免基底的矽污染到鐵電材 料層，以及使通道易於形成等等。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 -------Π----Λ------訂------戈 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 Ϊ 5 本紙張尺度適用中國國家標牟（CNS ) Α4規格（2丨ΟΧ297公釐〉d4856 8 5 8 2 4 twf, doc / 008 A7 B7 V. Description of the Invention (b) The working voltage of the write / erase of the ferroelectric non-volatile memory cell of the preferred embodiment is low, and no working voltage is required for reading , So it can increase the life of the component, and can reduce the power consumption of the component. In addition, compared with EPROM and flash memory, the ferroelectric non-volatile memory cell of the present invention has the advantage of being able to selectively modify data. Furthermore, if compared with the conventional ferroelectric non-volatile memory, the ferroelectric non-volatile memory of the preferred embodiment of the present invention has the following advantages: Avoid controlling the gate electrode to react with the silicon substrate, and avoid silicon contamination of the substrate To ferroelectric material layers, and easy channel formation. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. ------- Π ---- Λ ------ Order ------ Ge (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Ϊ 5 This paper size is applicable to China National Standards (CNS) Α4 specification (2 丨 〇 × 297 mm)