TW447205B - Multiple network protocol encoder/decoder and date processor - Google Patents

Abstract

A multiple network protocol encoder/decoder comprising a network protocol layer, data handler, O. S. state machine, and memory manager state machines implemented at a hardware gate level. Network packets are received from a physical transport level mechanism by the network protocol layer state machine which decodes network protocols such as TCP, IP, user datagram protocol (UDP), PPP, and raw socket concurrently as each byte is received. Each protocol handler parses and strips header information immediately from the packet, requiring no intermediate memory. The resulting data are passed to the data handler which consists of data state machines that decode data formats such as email, graphics, hypertext transfer protocol (HTTP), Java, and hypertext markup language (HTML). Each data state machine reacts accordingly to the pertinent data, and any data that are required by more than one data state machine is provided to each state machine concurrently, and any data required more than once by a specific data state machine, are placed in a specific memory location with a pointer designating such data (thereby ensuring minimal memory usage). Resulting display data are immediately passed to a display controller. Any outgoing network packets are created by the data state machines and passed through the network protocol state machine which adds header information and forwards the resulting network packet via a transport level mechanism.

Description

447 20

V. Description of the invention (1) Background of the invention The present invention relates to the present invention. The present invention relates to packet processing and packet processing without any expense. In addition, the present invention stacks cache data packets' communication protocols and data packets. More precisely, network protocol decoding and data miscellaneous items implemented in time-consuming software or software / hardware implementations allow one-time analysis of the data, eliminating the need to use different memory. Description of related technologies Computer network needs often, a computer network is connected to each other and can communicate. Data packets are used to transmit and receive data through various communication protocols. A system that includes equipment such as computers, printers, and other computer peripherals. Data is sent between these devices, and the data packets are communicated through a network using a protocol standard ...- ,, ... ~ An example of a popular protocol is the Internet Protocol (IP) , Internet Packet Exchange (IPX), Sequential Packet Exchange (SPX), Transmission Control Protocol (TCP) and Point-to-Point Protocol (PPP). Each network device contains a combination of hardware and software that translates protocols to process data. An example is an electrical device connected to a local area network (LAN) system. One of the network devices uses hardware to handle the connection layer protocol, uses a network, transmits protocols, and processes information. Network ^ Restricted connections: The computer only goes to the hardware of that particular local area network protocol ... a connection layer protocol. -Once the data passes through the network device hardware g

d47 20 V. Description of the invention (2) System memory, the software program that processes data implements a connection layer agreement. Once data is transferred to system memory through network device hardware, software programs that process the data implement higher-level protocols, such as networking, transmission, and communication protocols, and data processors. The benefit of this implementation is that it allows the use of a general-purpose device such as a computer in many different network settings and supports any random network application that may be required. However, the result of this implementation is that the system requires a high processor cost A large amount of system memory requires complex settings on the computer user side to coordinate different software protocols and the computer's operating system and the data processor of the computer and network hardware. In 1996] U.S. Patent No. 5 4 8 5 4 6 0 issued to Schrier et al. On 16th, teaches a method of operating multiple software protocols stacked on a device to achieve the same protocol, and illustrates the processing in This high expense is required in time. This implementation is used in a disk operating system (DOS) machine running Microsoft Windows software. In normal operation, once the hardware verifies the transmission or connection layer agreement, the resulting data packet is sent to a software layer that determines the packet format and strips off any specific packet headers. The packets are then sent to different protocol stacks that are evaluated by a particular protocol. However, packets may be sent to several protocol stacks before they are received or rejected. The time delay created by the software protocol stack prevents real-time processing of sound and image transmission: data must be cached before recovery. Obviously, the processing cost required to process an agreement is very high and cumbersome, and it is only suitable for applications with a powerful central processing unit (CPU) and large memory. Consumer products that are inappropriate for the traditional model of network equipment are entering the market. A few examples of these products are pagers, mobile phones, game consoles,

Page 9 447 20 涔 彡 5. Description of the invention (3) Smart phones and TVs Most of these products have a small footprint, 8-bit controller, limited memory or require a very limited actual height. These consumer products are simple and require low consumption and electricity. The implementation of the above agreement requires too much hardware and processor power to meet these requirements. The complexity of this implementation is difficult to include in a consumer product in an economical way. If Internet access can be simplified, it may be easy to mass-produce on a device with low power consumption, low power consumption, and a small practical height. These products can access Internet services such as the Internet. Summary of the invention The low group of this code. This network can reduce the processing of a single network memory management layer and machine at the same time. Buy and strip it to the next invention. Provide a less memory and provide a consumption, low power consumption, easy to manufacture, small practical. High inventions include a message protocol and a system memory cost. The best protocol layer state machine invented. Receiving network seals such as TCP, network protocol to remove header information, a protocol layer or an efficient protocol to decompose network access modules, a multi-component system that decodes in a byte stream in parallel, due to software central processing The hardware collective and actual height requirements for packet data also eliminates the need for the embodiment to include a state machine in a hardware, data processor, operating system-like network protocol layer from a packet. IP, User Network Packet Protocol (UDP) code as each byte is received. Each contract processor immediately removes the need for intermediate memory. Results The data processor, which includes the state machine implemented on the example gate level, and the physical transmission, protocol status, PPP and original packet analysis, and the data is passed, such as e-mail

Page 10 4 47 20 ^ V. Description of the invention (4) A data state machine for decoding data formats of graphics, Hypertext Transfer Protocol (HTTP), Java, Hypertext Markup Language (HTML ·). Each data state machine responds according to the corresponding data, and the data required by any multiple data state machines is provided to each state machine at the same time. Any data that is requested multiple times by a particular data state machine is placed in a particular memory unit with a pointer to such data (thus ensuring minimal memory usage). The resulting display data is immediately transferred to a display controller. The data state machine creates all output network packets, adds information to the packets, verifies header information, and forwards the resulting network packets through a physical transport layer mechanism through the network protocol state machine. The preferred embodiment does not necessarily require a central processing unit and software to process network packets, thereby greatly reducing system costs. The hardware gate-level implementation provides a module that can be embedded in the design, so the designer may choose the functions required for a particular application and still maintain low consumption, low power consumption, and small actual height. Brief description of the diagram FIG. 1 is a high-level data flow chart of a core system according to the present invention; FIG. 2 is a high-level block diagram of a system according to the present invention; FIG. 3 is a functional block diagram of a complete system according to the present invention; A is a functional block diagram of the upper memory area memory controller according to the present invention; FIG. 4 illustrates a time comparison diagram of a conventional structure and the data task time requirements of the present invention; FIG. 5 illustrates the possibility of an application program according to the present invention process;

Page 11 447 20 ^ 5. Description of the invention (5) Figure 6 illustrates the concept of an Internet tuner according to the present invention; Figure 7 illustrates two implementations according to the present invention; Figure 8 illustrates a network personal computer according to the present invention Implementation; Figure 9 illustrates a handheld device implementation in accordance with the present invention; Figure 10 illustrates a smart phone implementation in accordance with the present invention; Figure 11 illustrates a smart TV, cable box, video recorder (VCR), digital in accordance with the present invention Implementation of a video disc (DVD) and a game machine; Figure 12 is a time chart of sharing a received packet according to the present invention; and Figure 13 is a signal showing a packet of patent application range 12 according to the present invention A block diagram of the principle of the flow; Detailed description of the invention Referring to FIG. 1, the present invention includes a network protocol layer 1 0, a data processor 10 2 ', a memory control implemented at a hardware gate level, respectively. Module 103, and an operating system state machine module 104. The network communication protocol layer 101 decodes the input and output network packets. Network protocol layer 101 contains a number of state machines, which represent different network protocol stacks (for example, ppp, TCp, IP ′ U D P, and original jack) that decode the network packets in turn at the same time. The gate-level logic circuit implements protocol stacking, allowing network packets to be decoded in real time when network packets are received, so temporary memory storage is not required. After the state machine has stripped and verified the header information of all packets, the result data is passed to the data processor 102, which contains numerous state machines. They each process a specific data type (for example

^ 44720 ^? V. Description of the Invention (6) For example, Η TTP, various e-mail formats (Mail Protocol (POP3) 'Internet Message Access Protocol Fourth Edition (〖ΜΑΡ4), Simple Mail Transfer Protocol ( STMP)), graphics standards (Contract Graphic Experts Organization (jpeg), Graphics Interchange Format (GIF)) 'Java and Η TML). Gate-level implementation of data processing allows the present invention to process the received data in parallel and in real time, and is particularly suitable for applications where data streams are processed on a daily basis. For example, ja νa, Η TML, POP3 email, and audio and video Application to provide the data required by any multiple data state machines in a parallel manner. Any data requested by a data state machine multiple times is placed in a specific memory unit with a pointer to this data, and all memory accesses are arbitrated through the memory control module. Any result data is routed through the memory control module. The operating system state machine 104 acts as an arbiter between all resource control, system and state machines of the user interface. Any user input is interpreted by the operating system state machine and routed to the data processor 102. h As an example, a data processor that interprets HTML format can use a cyclic repeat check (CRC) calculation to decode the HTML markup. The HTML format contains a substring called ‘handwriting’, which is used to control the formatting of a sequential block of text when displayed on a video carousel device. By generating a cyclic repetitive check number for a given tag, these tags can be efficiently decoded and the above number used to allow a format instruction ◊ such a solution ^ ^ ^, still at the gate level implementation and make an HTML encoded file in a video The output t is displayed faster than it is now. ° Although the invention is described at the hardware gate level, those skilled in this technology understand that these functions may

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(PALs), general array logic (GALs), read-only memory (ROMs), and other methods of software. In addition, a specific protocol and data type are marked, and those skilled in this technology can easily obtain that the modularity of the present invention is not limited to a specific protocol and data type. 5. Description of the invention σ) Turn to Figure 2 and illustrate the invention in a high-level block diagram. This figure illustrates the task of each module in the complete implementation of the invention. The operating system state machine 2 0 8 contains the logic and device control interface of system 1 and 1 and acts as an M traffic police between the state machines of other modules. "The Netcom 1 protocol layer 207 contains the protocol for TCPMP 'UDP, the original Jack, and PPP status machine 1. § The memory control module 206 contains the logic of the unified memory structure (jj Μ A) that allows the system and video display to reside in the same memory area. — A display controller 205 provides control of a video graphics array (VGA), television standard or other type of display. In this implementation, four data processors are used. An e-mail data processor 201 interprets mail communications Protocol Office (POP3) and Internet Message Access Protocol Version 4 ([MAP4) format. Translator 2 0 2 is used to decode jPEG and 01 卩 formats (business and telephone standards can also be decoded) ° It also contains a A Java machine to interpret the bytecodes of the Java language 203 'World Wide Web (wtfw) browser 204 contains a Ding Dong decoder / accelerator' HTTP data processor and an integrated email state machine. As a Examples' Suppose a system using a modem physical wheel tracks an input jPEG image packet. The request starts when the user indicates downloading a specific JpEG image packet by typing on the keyboard 32 i. The request starts when the user passes on the keyboard 3 21 Input indicates when a particular JPEG image is expected. Keyboard interface 316 interprets this input

Page 14 44720) ^ 5 V. Description of the invention ¢ 8) and passed to the operating system state machine 3 1 5. The operating system state machine 3 1 5 processes the input and passes it as a command to the TTP client 31 1. The HTTP client creates a request packet and passes it to the Transmission Control Protocol (TCP) layer 308 via the port decoder 309. The TCP layer processes the appropriate TCP header and passes it to the IP layer 307. The IP layer then processes the appropriate IP header and passes the packet to the PPP layer 306. The PPP layer processes the appropriate headers, adds an FCS, and passes the data to the physical transmission interface 305. The physical transmission interface serializes the data into a bit stream and passes the packet to the modem unit 304. When the host server receives the request, it sends the requested contract graphics expert organization (JPEG) image to the client system. MODEM3 0 4 which indicates that the data arrives to the physical transmission interface 3 0 5 receives the data first. Then the physical transmission interface reads the bit string data from the MODEM, converts it into a parallel byte data, and indicates to the PPP layer 3 0 6 that the data has arrived. The PPP layer reads the received data. When it detects a valid start byte, it starts analyzing the input bytes. When the byte stream reaches the P p p region, it is decoded by the p p p layer, and in this example the embedded packet is decoded as the I p type. In response to this protocol byte, the PPP layer allows the IP layer 307 and indicates to it that IP data is being received. All subsequent data received are passed directly to the I p layer. Then the IP layer starts to analyze the input data bytes. When it reaches the IP header agreement area, it determines which higher-level agreement is allowed. In this example, the p layer decodes the protocol area as a TCP type. At this point, the ip layer allows the TCP layer 308 and indicates to it when it receives Tcp data. When this indicator is activated, 'all the data bytes in the next received packets are passed to the IP and TCp layers (the P layer needs data bytes to complete the checksum calculation). Then the TCP layer starts to analyze the input data.

4 4 7 2 0 V. Description of the invention (9) Material rank group. When it reaches the TCP header destination cockroach area, it determines which feed processor is allowed. In this example, the port area gives Ding Ding ^ client 3 1 1 at this time: the decoder allows Ding "the client to indicate to it when it receives the requested data. Then the HTTP client starts analyzing the received data bit =. When HTTP When the client determines that the packet is a special type of contract graphics, the HTTP client is allowed to call the decoder 313. At this time, several groups are routed to the JPEG decoder 313. Then the JpEG decoder receives the next input data byte and processes the image separately. Remember the system to make a cry q 1 9 诎 ,,, u, break the decoding of the game ★ reached the display memory, so that the display system is 324 for processing and then output to the display device 326. All = Secondary 2 to see a variety of needs to save Take the shared memory resources. The memory access is controlled by a single memory controller. This is because all the masters are shared in a single memory buffer unit = f body buffer ... This memory controller is needed Two actuators = controller 312 receives read and write requests from various layers, and plans to arbitrate such requests as described in Figure 3A. In 302A and D3 3 0 / / In the illustrated setting, device D2

Eight; "'3A requests memory access at the same time, Extender 307A Ϊ: K to a device that has not recently accessed memory. Then the arbiter decides to get the input of arbiter spoon A. If the secondary B input. To enter, the request is passed to the arbiter's 31 OA memory. The A input on the ancient arbiter 31〇A is idle and the request is passed to ^ Some arbitration determinations are performed using mixed logic, so if no

Page 16 44720 V. Description of the invention u〇) Any other memory request eliminates any wait states for any device. Priority is assigned by setting the arbitration tree structure. In Figure 3 A, device [3] 0 0 A and device D 1 3 0 1 A each have a priority of 25%. This means that if all devices request a fixed memory usage, they will each receive 25% of arbitration time. Devices D2 302A, D3 303A, D4 304A and device D5 305A each have a priority of 12.5%. Simplify the memory controller design by having each single arbitration unit have the same logical structure. In this scheme, it is easy to set the number of requesting devices by adding and arranging arbitration units, and their priority level. Turning to Figure 4 ', the speed provided by the present invention is much faster than the conventional structure currently used. Figure 4 shows the time required to complete each task. For a series of packets requiring an HTML download 401, HTML decoding 40 2, JPEG download 403, JPEG decoding 4 04, JAVA download 405, JAVA byte decoding 4 06, and streaming audio 407, pictured above All the time required for the conventional structure 408 and the present invention (iReady structure) 409 to complete these tasks are indicated. For these tasks, the present invention 409 is significantly faster than the conventional structure 408. Turning to Figure 5 'shows the progress of this network access application. At present, the Internet client using traditional mode, namely computer 501. Internet personal computer 502 user equipment concept ‘Handheld device 503, Smart phone 504, Set-top appliance 505, and Smart TV 506 are now becoming facts. The present invention provides these products economically, quickly, and using network access that saves electricity. Referring to Fig. 6, the present invention works much like a TV 602 or a radio tuner 6 1 1 'signal (packet) is processed immediately without delay and sent to a display or audio output. The present invention will be described using the Internet conditioner 608 as

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ΑΛΙ 20 AS V. Description of the invention (11) A processing device similar to this kind of signal. The Internet conditioner 608 acts as an interface between the Internet signal 609 and, for example, a smart TV 604, a set-top appliance 6 0 5 'smart phone 6 0 6 and a handheld device 6 0 7. It is like a TV 6 0 2 and a radio 6 1 1-it processes the Internet signal 609 ° in real time. Figure 7 illustrates the complete implementation of the present invention, one using the operating system state machine 7 0 1 'network protocol layer 7 02, memory The body control 703, the display controller 704 ', the e-mail data processor 708, the translator 707, the Java 708, and the global information browser 705 may be divided into two separate modules. The modularity of the present invention allows, for example, the functions of the data processor 71 3 (email data processor 7 1 7 'interpreter 7 1 6, Java machine 7 1 5, and global information browser 7 1 4) for some application It can be separated and placed in a high-level read-only memory program. The following application examples further illustrate the versatility of the module design of the present invention. Figure 8 illustrates a possible network personal computer setup of the present invention. One variation includes operating system state machine 801, network protocol layer 802, memory control 803 'display controller 804, email data processor 808, translator 807, and Java machine. 8 0 6 and World Wide Web browser 8 0 5. E-mail data processor 8 1 7, translator 8 1 6, J ava machine 8 1 5, and World Wide Web browser 8 can be programmed into high-level read-only memory running on a microprocessor 8 13 1 4 codes to change. The microprocessor 8 1 3 communicates with the network and display functions through the operating system state machine; 80 9. The third variation allows the microprocessor 8 ^ to operate without third-party read-only memory 8 2 3 in order to explain

"720 Task 5 V. Description of the invention (12) Data from the fixed layer 8 1 9 and the operating system state machine 8 1 8. Turn to Figure 9 'A handheld device may only use the network protocol layer 9 0 1, and Combine it with a client transport mechanism 902 and an existing microcontroller 904. It is possible to add e-mail functionality by including an e-mail data processor 905 in the setup. This further demonstrates the modularity of the present invention and may increase the network The protocol layer 9 11 and the Java machine 9 10 are connected to a handheld device, so it is allowed to process the Java applet. Referring to FIG. 10, the smart phone can implement the operating system state machine 1 0 0 1 'Network Protocol layer 1 0 02, memory control 1 0 3, e-mail data processor 1 0 6 'display controller 1 0 4 to add e-mail function. Display controller 1 0 4 can control light emitting diodes (L ED), liquid crystal display (LCD) or large projection display. Optionally, a physical transmission control 1 0 0 5 can be added, depending on the connection requirements of the smart phone. The operating system state machine 1 0 0 7 ' Network protocol Tier 1 008, memory controller 1 009 to a smart phone with an existing microcontroller 1 0 1 0. The microcontroller 丨 〇 丨 〇 uses a third-party email client code 丨 〇 丨 1 to Perform the e-mail function. Finally turn to Figure II 'Smart TV, Cable Box' Recorder (VCRS) 'Digital Video Disc (DVD) and game console can use the network accessibility provided by the present invention. Operating system State machine 1102, network protocol layer 1 1 03 'Memory control 1 1 04' World Wide Web browser 丨 i 07, Java machine 1 1 0 6 and (optionally) display controller 丨 丨 〇 5 is connected to an existing controller 1 1 0 1 ° If there is no controller 丨 丨 丨 use the display controller 丨 丨 5. Because of the modularity of the present invention, it is easy to add email 丨 丨 5 Success month b. As mentioned above, 'optionally add e-mail data processor

Page 19, 44720 ^ 5 V. Description of the invention (13) 1124, translator 1123, Java 1122, and global browser 1121 code into high-level read-only memory running on a microprocessor 1 1 2 0 . The microprocessor 1 1 2 0 communicates with the network and display functions through the operating system state machine 1 1 6 and the example of packet reception. Figure 12 depicts a received network packet. The packet contains the following items shown from left to right: PPP header IP header TCP header JPEG data PPP field checksum (FCS) When detected and shown in the figure When a valid start byte is generated in the ppp block in 1 3, the line indicating the point to the protocol layer enable (PPP LAYER ENABLE) is activated. Once this line rises, the remaining PPP blocks are activated. In the PPP header is a field indicating the type of the protocol that encapsulates the PPP packet. In an uncompressed PPP header 'these bytes are 4 and 5 (calculation start byte 0 X 7e) ° In Figure 12' these bytes indicate that the encapsulated data is 0 of the p packet X 0 0 and 〇 2 1. After decoding this area, the PPP block activates the p-layer enable and PPP data area signals, which together allow the IP block in Figure 13. The PPP protocol area allows line decoding to the IP layer. The ppp data area line indicates that the input data bit stream is in the data area portion of the network packet. In order to allow the p-block above, these two must always be activated. Once the 1 p-block is allowed, it starts to analyze the input f-level groups. Referring back to FIG. 12, the data immediately following the ppp header is the I p heart. The I p header indicates the type of data encapsulated in the I p

Page 20 44720 lights V. Description of invention (14) area. In Figure 12, this area indicates that the encapsulated data is a TCP packet of 0 X 0 6 ° In response to decoding the IP block in this area, the Transmission Control Protocol Allow (τ 丨 IE TCP LAYER ENABLE) line is activated ° IP data The area is also activated after a few bytes' because there are some bits between the IP header agreement area and the beginning of the IP data area. The IP data area signal indicates that the input data bytes are in the data area of the IP. In order to allow the TCP block in Figure 13 the TCP layer enable and IP data area lines must be activated. Once the τ c p block is allowed, it starts analyzing the regions of the input data bytes. This field indicates which application or data processor the packaged data refers to. In FIG. 12, 'this area decodes port 0x0003. In FIG. 13, 'Port 3 is assigned an HTTP port. After decoding the destination area in the TCP header, the HTTP Allow line is activated, and the HTTP data area line is activated after several bytes, because there are two lines in the destination port area and the TCP data area. Once the HTTP block is allowed, it begins to analyze the input data bytes. When it decodes the header, it allows the JPEG decoder block in Fig. 13. Once the JPEG decoder is enabled, it starts processing the input bytes. The allow line is the only factory root line required to allow JPEG blocks. Although the present invention has been described here based on the best two examples, those skilled in the art will readily understand that beans may replace these statements without departing from the spirit and scope of the present invention. ^ Therefore, the scope of the present invention is limited only by the scope of patent applications contained below. 101102 Network Protocol Data Processor Layer

44720 E 5

Page 22 V. Description of the invention (15) 103 Memory control module 104 Operating system state machine module 201 E-mail data processor 202 Translator 203 J a va machine 204 Browser 205 Display controller 206 Memory control module 'Group 207 Network protocol layer 208 Operating system state machine 304 Modem unit 305 Physical communication 11 Interface 306 PPP layer 307 IP layer 308 Transmission control protocol (TCP) layer 309 Port decoder 311 Client 312 Memory control 313 JPEG decoder 315 operating system state machine 316 keyboard interface 321 keyboard 324 display controller 326 display 5 and 44720 ^ 3 page 23 401 HTML download 402 HTML decode 403 JPEG download 404 JPEG decode 405 JAVA download 406 JAVA bytes Decoding 407 stream audio 408 traditional structure 409 i Ready structure 501 computer 502 network personal computer 503 handheld Preparation 504 wise type phone 505 opposite the top by having 506 wisdom type TV 602 TV 604 wise type TV 605 opposite the top with a device 608 Internet modulation i.e. 609 Internet signal 611 radios 701 jobs system state machine 702 mesh path agreement layer 703 in mind, memory and control

4 47 2 0 ^ V. Description of the invention (17) 704 Display controller 705 Global information viewer 706 Java machine 707 Translator 708 E-mail data processor 713 Data processor 714 Global information browser 715 Java machine 716 Explanation 717 E-mail data processor 801 Operating system state machine 802 Network protocol layer 803 Memory control 804 Display controller 805 WWW browser 806 Java machine 807 Translator 808 E-mail data processor 809 Operating system status Machine 813 Microprocessor 814 World Wide Web Browser 815 Java Machine 816 Translator 817 Email Data Processor

4 47 2 0 ^ .5 V. Description of the invention (18) 818 Operating system state machine 819 Network protocol layer 822 Microprocessor 8 2 3 Read-only memory 90 1 Network protocol layer 9 0 2 Client transmission mechanism 9 0 4 Microcontroller 90 5 Email data. Processor 9 10 J ava machine 911 Network protocol layer 1001 Operating system state machine 1 002 Network protocol layer 1 0 0 3 Memory control 1 0 0 6 Email data Processor 1 0 0 4 Display controller 1 0 0 5 Physical transmission control 1 00 7 Operating system state machine 1 0 0 8 Network protocol layer 1 0 0 9 Memory controller 1010 Microcontroller 1011 Email client code 1101 Control 1102 operating system state machine 1103 network protocol layer

Page 25 4 4720 _ V. Description of the invention (19) 1104 Memory control 1105 Display controller 110 6 J ava machine 1107 World Wide Web browser 1115 Email 1116 Operating system state machine 1120 Microprocessor 1121 Global information browser. 112 2 J ava machine 1123 translator 1124 email data processor

Page 26 44720 ^ Simple illustrations Page 27

Claims (1)

44720 々 々, patent application scope, patent application scope 1. A device for decoding and encoding network protocols and data: It includes a network processor layer data processor that decodes and encodes network packet bytes. Modules; a memory control module; and an operating system state machine module. According to the device described in Patent Application 1, the network protocol layer contains a plurality of state machines representing different network protocols. According to the device described in Patent Scope 2, the network protocol layer presents one or more of the following network protocol: point-to-point protocol, network packet, transmission control protocol, original jack, and / or user network packet Concordance group 2. Root packet 3 Root solid seal 4. Root cover 5. Root cover 6. Root cover 7. Root is 8. According to the device described in the scope of patent application 2 ...-Instant processing. The device described in patent application 2 processes in parallel. According to the device described in patent application range 2, the bytes are processed serially. The device described in patent application 1 has a hardware gate-level circuit. According to the device described in the scope of patent application 1, the network packet byte, the network packet byte, the network packet byte, and the network protocol layer are each specified by Page 28 44720 Six 'Patent Application Scope · The information requested by the complaint machine multiple times is placed in a specific β-and a pointer points to the memory unit. Earlier in the '9, according to the device described in the scope of patent application 1, said 5, 1, and the upper corner processor to the master v one to process a specific data type state machine. 3 1 0 According to the device described in the scope of application patent 9, the Shen-Xi-Xi-Jia, & Bayer processor processes one or more of the following data types: Hypertext Transfer Protocol (Ηττρ) 'Hypertext Markup Language (HTML) 'Mail Protocol (ρ〇ρ3), Internet Message Access Protocol, Fourth Edition (丨 MAP4)' Simple Mail Transfer Protocol (STMP) 'Protocol Graphic Experts Organization (jPEG), Graphic Exchange " Format ^ (GIF) 'and / or java language. 2 1 1. According to the device described in the scope of patent application 9, the data type is processed. ^ 2 'The data types according to the apparatus described in Patent Scope 9' are processed in parallel. 1 3. The data type according to the device 'described in the patent application range 9 is serially processed by bytes. 1 4 _ According to the device in scope of the claimed patent, the data processing community is a hardware gate-level circuit. ° 1 5 According to the device described in patent application range 9, the data processor is a high-level read-only memory program. 1 p * According to the device described in the scope of patent application 9, any data shared by the state machine or requested by a particular state machine multiple times is placed in a special memory unit, and a pointer points to all Mentioned memory unit. Article 29 苋 VI. Scope of Patent Application 1 7 According to the device described in the scope of Patent Application 9 ', any data shared by the state machine is provided to the state machine in parallel. 1 8. According to the device of claim 1, the memory control module arbitrates all memory accesses. 1 9 · The device according to the scope of the patent application 'The memory control module includes a unified memory structure that allows the system and video memory to stay in the same memory area. 2 0. The device according to claim 1, wherein the memory control module includes one or more arbiter logic blocks, and one of the arbitration blocks performs arbitration between two devices according to a dynamic rotation algorithm. 21. Root, the device described in the scope of patent application 1, said memory control module ^ S or more arbiter logic blocks' The logic blocks are based on a certain arbiter tree structure for each memory The access device is arranged in a manner that assigns a priority to the mouth. 2 2. Root, declare that the device described in patent scope 1 'the operating system state machine is used for resource control, the system and the user interface, the data processor and the memory control module of the network layer Arbitration between 23. According to the scope of patent application! The device further comprises: a display controller. Only according to the device described in the stated patent range 23, the display controller controls one of the following display types: VGA, TV 'liquid crystal display, or light emitting diode. Page 30 44720 ^ VI. Scope of patent application The data processor, the memory control, the operating system state machine and the display controller are a hardware gate-level circuit. 2 6. The device according to claim 1 which acts as an Internet tuner for the consumer. 2 7. A method for decoding and encoding network protocols and data, the method comprising the steps of:-encoding and decoding network packet bytes,-processing packet data bytes;-controlling memory access; and- Controls state machine sequencing. 28. According to the method described in patent application range 27, the step of encoding and decoding network packet bytes further includes the step of using a plurality of state machines to represent different network communication protocols. 2 9. According to the method of claim 28, the step of encoding and decoding network packet bytes further comprises the steps of: encoding and decoding one or more of the following network communication protocols: point-to-point protocol, network packet , Transmission control protocol, original jack, and / or user network packet protocol. 30. According to the method of claim 28, the step of encoding and decoding network packet bytes further includes the step of processing the network packet bytes in real time. 3 1. The method for encoding and decoding network packet bytes according to the method described in the scope of application patent 2 7 further includes the step of processing the network packet bytes in parallel. Page 31 4 4 7 2 0 ^ VI. Patent Application Range 3 2. According to the method described in Patent Application Range 2 7, the step of encoding and decoding network packet bytes further comprises the steps of: byte serialization Way to deal with network packet bytes. 3 3. According to the method described in patent application range 27, the step of decoding and encoding network packet bytes is a hardware gate-level circuit. 34. According to the method of claim 27, the step of processing packet data bytes further comprises the step of processing a specific data type with at least one state machine. 3. 5. According to the method described in patent application range 34, the step of processing packet data bytes further comprises the step of using a CRC algorithm to decode the data area. 36. The method according to claim 34, wherein the step of processing the packet data bytes further comprises the steps of: processing one or more of the following data types: Hypertext Transfer Protocol, Hypertext Markup Language, Mail Protocol, Four versions of Internet Message Access Protocol, Simple Mail Transfer Protocol, Protocol Graphics Experts Organization, Graphics Interchange Format, and / or Java language. 37. According to the method of claim 34, the step of processing the packet data bytes further includes the step of processing the packet data bytes in real time. 3 8. According to the method described in the scope of patent application 34, the step of processing the packet data bytes further comprises the step of processing the packet data bytes D 3 in parallel 9. According to the method described in the scope of patent application 34, The step of processing packet data 4 4 7 2 〇, JT application for patent scope, and byte steps further includes the steps of: processing packet data 4 0 in a byte serial manner. According to the application detection and tuple 4 1. According to the application Bytes 4 2. According to the application, each specific memory unit 4 3. According to the application, the steps 4 4. According to the application, the steps are taken together 4. 4. Between the byte and the resource step 4 6. Control the material byte according to the steps of the application sequence. Patent range 34 steps are a hard patent range 34 steps are a process patent range 34 steps are step by step. The state memory memory unit patented step by step is patented further patented further video recorded patented further steps source Controlling the progress of the secondary patent, including the information contained in step 34, step 27, step memory, step 27, said, the system is tailored. The block-level gate-level sequence of the stepper pattern contained in the block 27. The described method contains a step machine multiple times, and the described method: the described method: used in the same method: in the processing packet and user method, the processing packet data circuit. Method, said processing packet data method, any data required for said processing packet data is placed in a pointer to the notation, the control memory storage method is determined, and the control register structure allows A unified memory method, wherein the packaged data interface controls a memory area. Describe the steps of controlling the code and unpacking the memory state machine coding network seal, the method of physical access, the control state machine stepping, explaining the system and user input to group, and the network Protocol layer module. Page 33 d 4720 ^, ^ _ VI. Patent Application Range 4 7. According to the method described in Patent Application Range 27, the method further includes the steps of: displaying output data. 4 8. According to the method described in Patent Application Range 47, the step of displaying and outputting data further includes the step of controlling one of the following display types: VGA, TV, liquid crystal display, or light emitting diode. 4 9. According to the method described in patent application range 4 7, the processing is a hardware gate-level circuit. 50. The method according to claim 27, wherein the process is an Internet tuner for a consumer. Page 34