TW447074B - A method to form narrow and wide shallow trench isolations with different trench depths to eliminate isolation oxide dishing - Google Patents

Abstract

A method of forming trenches having different depths for us in shallow trench isolations is achieved. Dishing problems due to isolation oxide thinning over wide trenches is eliminated. A silicon substrate is provided. A pad oxide is grown. A polishing stop of silicon nitride is deposited. An oxide layer is grown overlying the silicon substrate. The oxide layer, polishing stop layer, and pad oxide layer are etched through to the silicon substrate to form openings for planned first trenches. A polysilicon layer is deposited overlying the oxide layer and filling the openings for the planned first trenches. The polysilicon layer is polished down to the top surface of the oxide layer such that the polysilicon layer remains only in the openings of the planned first trenches. The oxide layer, polishing stop layer, and pad oxide layer are etched through to the silicon substrate to form openings for planned second trenches. The silicon substrate and the polysilicon layer are simultaneously etched to complete the first trenches and the second trenches, with the second trenches deeper than the first trenches, and with the oxide layer a hard mask, and the integrated circuit device is completed.

Description

447 0 7 4 __Case No. 88119090 V. Explanation of the invention (1) [Background of the invention] 〇) Field of invention _ The present invention relates to a method for manufacturing a silicon substrate, especially a narrow and wide substrate with different depths. The formation of the shallow trench isolation layer removes the recessed portion of the isolation oxide layer. (2) The use of conventional technology for the formation of shallow trench isolation layers for integrated circuit isolation, due to the reduced surface area and improvement of STI when compared to traditional regional silicon oxide structures (Locos) However, progress has been made, and there will be a problem with the depression of the oxide layer during the use of the STI. To some extent, the occurrence of the recessed portion of the oxide layer is 'because of the deformation of the polishing pad in the chemical mechanical polishing process used for the flat STI structure.' The reason for the recessed portion is because the STI isolation oxide layer has a recessed shape. As the oxide layer in the trenches becomes thinner by the CMP process, the recesses particularly represent large or wide s < n structures, due to the flatness effect and because the isolation oxide layer covering these trenches is typically covered by deposition The oxide layer on the narrow trench is thinner, and the narrower STI structure shows a small amount or no depression. Refer to Figure 1, which shows a cross-sectional view of a partially completed conventional integrated circuit. It shows a silicon substrate i 0, and a pad oxide layer i 9 is overlaid on the silicon substrate 10 'a silicon nitride layer 2 0 series. Overlapping on the pad oxide layer 19 and using this as a polishing stop, two narrow trenches 丄 4 and one wide trench 丄 8 are etched into and pass through the pad oxide layer 丄 9 and the silicon nitride layer. 20, and entering the surface of the silicon substrate 10, the trenches have the same trench depth L1 because they are all processed by the same active ion etching process (RIE).

Page 6 447074 --- Case No. 88119090 V. Description of the invention (2)

/ 2 0 and fill the trench 'It is necessary to pay attention to the trench mode here will affect the isolation: the mode of the chemical layer 2 2' is where the isolation oxide layer 2 2 is connected to the trench 丄 4, which is equivalent here; | In contrast, the barrier oxide layer 2 2 covering the wide trench 丄 8 is relatively thin. ^ See Figure 3, which shows the results of chemical mechanical polishing (CMp). The isolation oxide layer 22 has been ground to the top surface of the nitride nitride layer 20 to complete the shallow trench isolation layer. However, if the towel is ground in this way, it will produce visible visible depressions 2 and 4 covering the wide grooves! The upper part of the upper part 8 will increase the leakage current and decrease the inter-oxygen breakdown voltage}. These problems in the active area interface will reduce the yield of the device. Company = a conventional technical method to expose a method for manufacturing trenches with different depths on a substrate, such as taught in U.S. Patent No. 5,776,8 1 7 (Uang)-methods for forming different depth trenches, including There are: forming sacrificial refractory metal with different thicknesses to anneal the metal layer to produce metallization layers of different depths on the base substrate, and then removing the refractory metal and the metallurgy layer to expose trenches of different depths: U.S. Patent No. 0'814, 347 (Chang) discloses a method for engraving trenches with a microloading effect to v trenches of different depths. U.S. Patent No. 5,851,928 (Aripe) discloses a method for engraving different depths and openings of different sizes by using a mask layer in a single wet isotropic etching step. U.S. Patent No. 3 '15 7' 003 (Tsui et al.) Teaches a method of etching trenches of different depths. The selected exposed phenolic positive photoresist is used to define the etching area. Two etching steps are performed to form two shallow trenches of different depths. [Objective and Summary of the Invention]

v 447074 ----- Plug No. 88119090__Year Month and Amendment ___ V. Description of the invention (3) The main purpose of the present invention is to provide a shallow trench isolation layer in the manufacture of integrated circuits. The present invention is effective Another method of the present invention is a method of layering, which can remove oxygen. Another object of the present invention is a method of forming a width smaller than a narrow trench. Another object of the present invention is to make shallow trenches of different depths. According to the purpose of the present invention, it is a novel method. It provides a silicon substrate. A polishing barrier layer is formed and deposited on the polishing barrier layer for oxidation. The layer is etched through the opening of the silicon-based first trench. A polycrystalline silicon fills the opening of the designed first trench. The top surface is such that the polycrystalline layer has only an oxide layer, a polishing barrier layer, and a top surface of the pad. To form the designed substrate and be engraved with money at the same time to complete the first trench system is etched compared to the first trench;) t | $ curtain, an isolation oxide layer deposition trench and a second trench, isolation oxide wear resistance layer Top surface,% circuit: And very manufacturable method. It is to provide a recess for manufacturing a shallow trench isolation layer. The invention is to provide a trench in a shallow trench isolation layer and to remove an isolation oxide recess. The invention is to provide a method in the same etching step. The result is a manufacturing of a shallow trench isolation layer. A pad oxide layer is formed overlying the silicon over the pad oxide layer, an oxide layer 'oxide layer, abrasion barrier layer' and the top surface of the fascia to form the design. The layer deposition is overlaid on the oxide layer, and the polycrystalline silicon system is ground until the oxide layer stays in the designed trench opening, and the oxide layer is etched through to the trench opening of the oxide layer. The polycrystalline stone layer, a stone channel and a second channel, here the second and here the oxide layer is used as a money engraved mask on the oxide layer, and the first groove and the oxide layer are filled to be polished Until the shallow trench isolation layer is developed, and the integrated body is completed 447074 amendment-case number 88Π9090 V. Description of the invention (4) 4 Drawing number comparison description] • 0 silicon substrate 1 4 narrow trench 8 nine trench 1 9 塾 oxidation Layer 0 4 Silicon nitride layer recess 2 2 Isolation oxide layer 0 Silicon substrate 3 1 Pad oxide layer 2 Abrasive barrier layer 3 4 Oxide layer 8 Opening 4 2 Polycrystalline debris layer 6 Opening 5 Isolation oxide layer 4 Wide trench 5 8 Wide trench area [Detailed description of the invention] Now refer to FIG. 4, which illustrates a cross-sectional view of a partially completed integrated circuit component. The silicon substrate 30 is preferably composed of single-crystal silicon, and a pad of oxygen is used. Layer 3 1 is grown overlying the Shi Xi substrate 3 ′, and the “塾 oxidized layer 3 1” contains silicon dioxide ′ is grown by a thermal oxidation process of the silicon substrate 3 ′. A polishing barrier layer 3 2 is deposited Covered on the pad oxide layer 3 丄, the polishing barrier layer 3 2 includes a layer deposited by CVD The silicon nitride layer, an oxide layer ^ 4 is deposited on the polishing barrier layer 32, and the oxide layer 3 4 is silicon dioxide, which is deposited by a CVD process. 0 in 4 1. Grind the junction of the barrier layer 32 and the oxide layer 34. The purpose is to produce different depths: J = sign; ^ 5 In particular, the depth of the grooves with a width of 胄 ': Grooves thin cover wide

^ 9-^-447074 correction

8811 ΑΠΡη 5. Description of the invention (5) Isolation oxide layer 'In this way, the recesses covering the trenches will also be removed. As can be seen in the figure, the thickness L of the combined stack is controlled to be narrow. And the depth difference I between the wide trenches, which is very beneficial, because the conventional method can be used to accurately control the mat layer and the oxide layer 34 in combination with the layer "L2: here In the preferred embodiment, the thickness of the pad oxide layer 3 is between y Angstroms, the thickness of the abrasive barrier layer 32 is between two Angstroms and the thickness of the oxide layer 34 is between two Angstroms and 100 Angstroms. To 300 angstroms. Typically, a 'wide trench' is about 1 micrometer to 100 micrometers wide, and a narrow trench is about 0.24 micrometers to 0.5 micrometers in width. The initial conditions of the process vary, and the total thickness consisting of the pad oxide layer 3 丄, ground X grind =% 2 3 2 and the oxide layer 3 4 will depend directly on the narrow groove: f degree. In this preferred embodiment, The thickness of the hybrid stack is between 1/2 and 3/4 of the depth of the thin groove. Now referring to FIG. 5, the oxide layer 3 4, the polishing barrier layer 3 2, and the oxide layer 3 1 are etched through a place that is not protected by a mask (not shown) to the top surface of the silicon substrate 30 In order to form the designed wide trench = 23.8 'oxidation etching step is performed by conventional reactive ion etching (RIE) or plasma dry etching. Now referring to FIG. 6, the polycrystalline silicon layer 4 2 is deposited on the oxide 9 f 4 and fills the opening 3 8 of the designed wide trench. The polycrystalline silicon layer 4 is less = good use of the conventional low-pressure chemical vapor deposition process (LPCVD). ) And the deposition, said the layer 4 2 is deposited to a thickness of 2,000 Egyptian 4,000 angstroms. The thickness of the polycrystalline stone 4 2 is based on the pad oxide layer 3 1 and the polishing barrier layer 4 881〗 卯 Such as the fifth, the description of the invention (6) ± _ Ά That is, the thickness of the mixed stack of correction 2 and oxide layer 3 4 depends. Said Shi Xizheng referring to FIG. 7, which shows another important point of the present invention, 4 2 is ground to the top surface of the oxide layer 2 4, so that polycrystalline silicon is left in the opening of the designed wide trench 3 8 This step is best done by mechanical polishing (CMP), which can be selectively polished after f and stopped at the silicon oxide. 'It can also be seen in the figure' that the oxide layer in the CMP step 3 4 The thickness of the polishing barrier layer 3 2 and the pad oxide layer 31 is mixed to create a thickness of the polycrystalline silicon layer 42. 〇 ^ Referring now to FIG. 8, the oxide layer 34, the polishing barrier layer 32, and the pad emulsifying layer 31 are etched through a place that is not protected by a mask (not shown until the top surface of the silicon substrate 30). Form the designed narrow trench = opening 4 6. This etching step is preferably performed by conventional oxidation etching or a dry silver etch. Now referring to FIG. 9, it shows another important aspect of the present invention. A: The silicon layer 4 2 is engraved through the surname, and the silver-etched stone substrate 30 is used. The oxide layer 3 4 is used as a hard mask. This etching step completes the wide trench and the narrow trench. The polycrystalline silicon layer 4 2 is completely Etched away, narrow trench on silicon substrate '

The etched depth of 〇 is larger than that of the wide trench. The better active ion etching process (R 丨 E) for A and A trench etching is the use of a conventional etching chemical containing HBr, C1 2 and 02. This type of material is used on silicon substrates 30 and polycrystalline silicon layers 4 2 The etching rate is almost the same. Therefore, the difference between the narrow trench depth L4 and the wide trench depth L3 is only the thickness L2 of the crystalline silicon layer 42. As mentioned before, the thickness of the polycrystalline silicon layer 4 2 = 2 is the same as the thickness of the hybrid stack. Therefore, the difference in the thickness of the trench is determined by the combined thickness of the oxide layer 34, the polishing barrier layer 32, and the pad oxide layer 31.

IH1 Page 11

447074 ___88119Q9Q Year, month and day of amendment V. Description of invention (7) Controlled by degree L2, for example, narrow grooves and wide grooves can range from 1000 Angstroms to 3000 Angstroms. Now refer to Figure 10, an oxide barrier layer 3 4 and a silicon substrate On 30, it is best to deposit an oxide layer of 50 series with a chemical gas oxide layer to reach 5000. Here you can also see the difference between different trench depths. The deeper the width of the trench, the shallower the depth. The isolation oxide layer 50 without the isolation oxide layer 50 is also shown in FIG. 11 at the same time. Isolation polishing is performed until the top of the polishing barrier layer 32. This polishing step uses integrated circuit components of chemical mechanical polishing technology, and the important groove area On 58, the leakage current of this recessed part increases, and the gate breakdown voltage decreases. As shown in the preferred embodiment, the shallow trench isolation layer of the present invention is effective and highly tailored. It can remove the isolation oxide layer. Although the present invention Reference has been made to its better description, but those skilled in the art can make changes without departing from the present invention between 300,000 Angstroms and 500 Angstroms deep, between deep '' '50 from the oxide layer deposition Covers and fills wide and narrow trenches It is deposited by phase deposition (CVD) to isolate the thickness between Angstrom and 1000 Angstrom. It is important because it can be thinned compared to the area narrowly connected to the wide trench 54. The dents are removed by thinning. The oxide layer 50 and the oxide layer 3 4 are 'completed to complete the shallow trench isolation layer, and then completed' and then completed. As is customary, no depressions can be seen in the wide grooves, and the depressions will be removed, resulting in fewer components. Yield reduction issues. Ming provides a manufacturing process with different depths of creativity, which is in the integrated circuit depression; the embodiment is specifically shown and explained in a variety of forms and details in the spirit of public domain.

447074 Case No. 88119090 3 3 Brief description of the modified diagram In the drawings, you will learn the materials listed in this specification, including: · Figures 1 to 3 are used to describe the circuit components in the product II A partial cross-sectional view of the shallow trench isolation layer of the conventional technology is completed. 4 to 11 are cross-sectional views illustrating a preferred embodiment of the present invention:

Page 13

Claims (1)

447074 Case number 88119090 "Fang Gan" Zhizhong Formation has two different deep Tang Zhao 16 16 5 patent application Fanyuan a method for manufacturing φ newspapers and earthenware plates in integrated circuit components' includes the steps of: providing a silicon substrate; deposition An oxide layer is overlaid on the silicon substrate; etching through the oxide layer to the opening of the first trench of the top design of the silicon substrate; @W & Design brother-trench opening; grind the polycrystalline silicon layer to the top surface of the oxide layer, so that the silicon layer stays only in the opening of the designed first trench; after that, etch through the oxide layer to the silicon The top surface of the substrate to form the opening of the designed second trench; ′ simultaneously etch the silicon substrate and the polycrystalline silicon to complete the first trench and the second trench, wherein the etching forms the second trench ratio The first trench is deep, and the oxide layer is used as a hard cover; and the manufacturing of integrated circuit components. The method according to item 1 of the patent application range, wherein the oxide layer is deposited to a thickness between 100 angstroms and 300 angstroms. That is, the method as described in item 1 of the scope of the patent application, wherein the crystal fracture layer is deposited to a thickness between 2000 and 4000 Angstroms. The method according to item 1 of the patent application scope, wherein the second groove is wider than the first groove. The method according to item 1 of the patent application scope, wherein the step of grinding the polycrystalline silicon layer is performed by chemical mechanical polishing. No. 14 1 447 074 Case No. 88119090 Rev. 6, application for patent scope 6, as described in the first patent application method, the silicon substrate and the polycrystalline yarn from this step is used for one moment, the activity Ion etching uses HBr 'etching chemicals. 7 · A method for forming a shallow trench in manufacturing integrated circuit elements, comprising the steps of: providing a substrate; growing a pad oxide layer overlying the silicon substrate; depositing a polishing barrier layer overlying the pad oxide Layer; deposit an oxide layer overlying the abrasive layer; etch through the oxide layer, the abrasive stop layer and the top surface of the oxygen pad to form a designed first trench, and deposit a polycrystalline silicon layer overlying the layer On the oxide layer and the opening of the first trench; grind the polycrystalline silicon layer to the top of the oxide layer, and the 'crystal stone layer only stays behind the designed first trench' passes through the oxidation in the rest Layer, polishing barrier layer up to the top surface of the silicon substrate to form the opening; at the same time, the stone substrate and polycrystal are etched at the same time; a layer to complete and a second trench, wherein the etching forms the second trench The groove is deep, and the hardened layer is used as a hard mask #etching pattern, and the second groove is deeper than the first groove, which is a hard mask; the living iions #, (: I 2, and 02 are simultaneously etched in the middle. Layer of the isolation layer until the opening of the base; The design surface, so the multi-opening; Sook and radon layer, the first trench a second trench design of the screen than the first trench, where the tank and the oxide layer as 447074 An isolation oxide layer is deposited overlying the oxide layer and the silicon substrate, and fills the first trench and the second trench; grinding the isolation oxide layer and the oxide layer until the polishing barrier layer is completed, Shallow trench isolation layer; and complete fabrication of integrated circuit components. 8. The method according to item 7 of the scope of the patent application, wherein the pad oxide layer is grown to a thickness between 100 Egypt and 200 Angstroms. 9. The method according to item 7 of the application, wherein the abrasive barrier layer includes silicon nitride, and the silicon nitride-based deposit reaches a thickness between 2000 Angstroms and 2000 Angstroms. 10. The method according to item 7 of the scope of the patent application, wherein the oxide layer is deposited to a thickness of between 1,000 Egyptian and 300 Angstroms. 11 · = The method described in item 7 of the scope of the patent application, wherein the $ crystalline silicon layer is deposited to a thickness between 2000 Egypt and 4,000 Angstroms. 12 * The method according to item 7 of the scope of patent application, wherein the first trench is wider than the second trench. 13. The method as described in item 7 of the Chinese Patent Application, wherein the step of grinding the polycrystalline stone is performed by chemical mechanical grinding. 14. The method as described in item 7 of the scope of patent application, wherein the step of simultaneously etching the Shixi substrate and the polycrystalline silicon uses an active ion etching, and the active ion etching uses HBr, c 1 2, and 〇2 Etching chemicals. lb. The method as described in item 7 of the scope of the patent application, wherein the isolation oxide layer is deposited by chemical vapor deposition ' to achieve a range of 500 angstroms — Page 16 447074 _ plug No. 88] TflnQn_ VI. Patent application scope: Correct the thickness between 16 17 and 10000 Angstroms. The method described in item 7 of the patent scope, wherein the step of grinding the lice-inhibiting layer is by chemical mechanical grinding. A method for forming a shallow trench isolation layer in integrated circuit manufacturing includes the steps of: providing a silicon substrate; growing an oxide layer overlying the silicon substrate; and depositing a siliconized abrasive resistance layer overlying Depositing an oxide layer overlying the polishing stop layer; etching through the oxide layer, the polishing stop layer and the pad oxide layer until the top surface of the silicon substrate is formed to form the design After opening the wide trench, a multi-wide trench is deposited to grind the polycrystalline polycrystalline silicon layer. After the polishing system, the layer is etched until the slot opening simultaneously etches the narrow trench and the deposition is isolated. The silicon layer is covered on the oxide layer and fills the designed opening; the silicon layer is up to the surface of the crotch of the oxide layer, so it only stays in the opening of the designed wide trench, in which chemical machinery is used Grinding: The top surface of the silicon substrate is oxidized through the oxide layer, the polishing barrier layer and the pad to form the designed narrow trench «1 silicon substrate and the polycrystalline silicon layer to complete the wide trench and wherein the etching As a hard mask into the narrow trench than the depth of the wide trench in the oxide layer; and an oxide layer overlying contact with the oxide layer and the silicon based plate, and Page 17 447074 ---. Case No. 88119090__Year Month Day_Amendment_ VI. The scope of patent application fills the wide trench and the narrow trench; · Grind the isolation oxide layer and the oxide layer until the grinding resistance Layer to complete the shallow trench isolation layer 'wherein the polishing is performed using chemical mechanical polishing; and the manufacturing of integrated circuit components is completed. "18 · The method as described in item 17 of the scope of patent application, wherein the polishing. Barrier layer system grows To a thick production between 100,000 Egypt and 200 Angstroms. 19. The method as described in item 17 of the scope of patent application, wherein the oxygen = layer system grows to a thick household between the door of Egypt and Egypt 300,000 = = method of item 17, In the same two steps of i, the step of the Shi Xinu plate and the polycrystalline layer is performed by using an active ion to etch the activity, and the ion etching uses an etching chemical including HBr, Cl2, and O2.