TW447031B - A method for planarizing a shallow trench isolation - Google Patents

Abstract

The present invention discloses a method for planarizing a shallow trench isolation in which the dishing and the erosion phenomena occurred in the prior art can be alleviated for obtaining a uniform step height. The method disclosed by the present invention is that high planarity slurry is used to perform a chemical mechanical polishing for planarizing the surface of the oxide layer before the silicon nitride mask layer (or ""polishing stop layer"" shown in the prior art) is exposed. Thereafter, (1) the redundant oxide layer can be removed by etching, or alternatively (2) using a highly selective slurry to perform a polishing until the mask layer is exposed.

Description

447031 V. Description of the invention (1) [Field of the invention] The present invention relates to semiconductor process technology, and in particular, to a novel method for planarizing shallow trench isolation, which can reduce the conventional knowledge. The shallow dishing and erosión phenomena encountered by the technology, obtain a uniform step height. [Background of the Invention] In recent years, with the development of semiconductor integrated circuit manufacturing technology, the number of components contained in wafers has continued to increase, and the size of components has been continuously reduced due to the increase in the degree of accumulation. From sub-micron to quarter-micron or even finer size range. Regardless of how the component size is reduced, each component in the wafer must still be properly insulated or isolated to obtain good component properties. This technology is generally called device isolation technology. Its main purpose is to form spacers between components, and to ensure a good isolation effect, minimize the area of the spacers in order to free more More chip area to accommodate more components. Among the various element isolation technologies, local fragmentation oxidation method (Locos) and shallow trench isolation process are the two most commonly adopted technologies, especially the latter has a small isolation area and is completed. The advantages of maintaining the flatness of the substrate are the semiconductor manufacturing technologies that have received much attention recently. Traditionally, the chemical vapor deposition (C V D)

Page 4 14703 1 V. Description of the invention (2) The dielectric layer is filled into the trench of the substrate, and then the chemical dielectric polishing process (CMP) is used to remove the excess dielectric layer on the surface to complete the trench isolation region process. . Referring now to Figures 1A and 1B, the problems encountered when processing conventional semiconductor substrates with shallow trench isolation regions (ST 丨) using conventional polishing techniques are discussed in existing CMP practices. An & oxide layer 110 is formed on the upper surface of the semiconductor substrate 100. On the pad oxide layer 110, a layer of silicon nitride is deposited to form a grinding stop layer 1 15. An optical lithography mask (not shown) is formed on the polishing stop layer 115. The above-mentioned optical lithography mask is subjected to an exposure / lighting procedure to form a pattern defining shallow grooves 105a, 105b, 105c, and 105d, and then the optical lithography mask is subjected to a development procedure to expose the semiconductor substrate 100. The areas where the shallow trenches 105a, 105b, 105c, and 105d are formed, "exposing the surface of the semiconductor substrate 10 () to an etchant" sequentially removes the polishing stop layer 115 and the pad oxide layer 11 0, and a part of the semiconductor substrate, thereby forming shallow trenches, 5a, 105b, 105c, and 105d. Thereafter, a silicon oxide filler is deposited on the surface of the semiconductor substrate 100. This step of depositing the silicon oxide filler is usually accomplished by the OfTEOS chemical vapor deposition (CVD), or spin-on-glass (SOG) procedure, which is well known to those skilled in the art. Then, the silicon oxide filler 1 2 0 is removed by the procedure described above. The step of grinding and removing the oxidized stone filler is performed until the surface thereof is at the same height as the polishing stop layer 115. However, the conventional CMP procedure causes three types of problems on the surface of the semiconductor substrate 100. The first problem is shown in section I in Figure 1B. The surface of the semiconductor substrate 100 was excessively 447031. V. Description of the invention (3) Grinding 'caused the polishing stop layer 115 made of silicon nitride to suffer erosion and thinning. The second problem is shown in the section Liao in the figure. The surface of the semiconductor substrate 100 was over-polished again and caused shallow dishing. This shallow dish depression phenomenon occurs in the area where large shallow trenches 105c * 105d are distributed ', which completely removes the polishing stop layer. The second question is shown in section m of Figure 1B. The surface area of the semiconductor substrate 100 is insufficiently polished, so a silicon oxide filler 1 2 0 remains on the surface of the semiconductor substrate 100. In order to make the planarization technology of the shallow trench isolation region more perfect, it is necessary to seek improvement in response to the above problems. [Summary of the Invention] In view of this, a flattening method, another method of the present invention, to avoid another method of the present invention, to avoid (dishing). The object of the present invention is to provide a shallow trench isolation region to obtain a uniform step height on the substrate surface. This purpose is to provide a flat abrasive stop layer with shallow trench isolation areas that are eroded. = Purpose, is to provide a kind of shallow trench isolation area. Flat shallow trench isolation area has a large area. Shallow dishing occurs in another area of the present invention. In the present invention, a method is described to avoid the silicon remaining in the polishing. Purpose: A shallow trench isolation region is above the planarization semi-conductive stop layer. Dry conductor substrates will be partially oxygenated. The method of the present invention first uses a high flatness of 447031. V. Description of the invention (4) The slurry is chemically and mechanically polished to expose the silicon nitride shielding layer (or what is known in the art). Before the polishing stop layer 11), the surface of the oxide layer is planarized; then, the excess oxide layer on the substrate is removed by etching until the shielding layer is exposed.

The method for planarizing a shallow trench isolation region of the present invention includes the following main steps: (a) providing a semiconductor substrate whose surface is at least covered by a shielding layer; and having a plurality of shallow trenches formed in the substrate; (b) ) Depositing an insulating layer on the substrate to fill the shallow trenches; (c) performing chemical mechanical polishing with a high-level polishing slurry, flattening the surface of the insulating layer before the shielding layer is exposed, and (d) engraving Remove the excess insulating layer on the substrate until the shielding layer is exposed and leave the insulating layer filled in the shallow trenches to form a shallow trench isolation area. According to the method of the present invention, (1). Because the grinding is stopped before the grinding termination layer is reached, the erosion and dishing caused by excessive grinding can be avoided, thereby obtaining a uniform Step height, ° (2). Furthermore, because the excess oxide layer on the substrate is finally removed by etching, chemical mechanical polishing can be avoided due to the effect of the underlying pattern, resulting in uneven polishing speed. (3). In addition, since it is not necessary to use silicon nitride as the polishing stop layer in this method, the above-mentioned shielding layer can also be made of materials other than silicon.

In another aspect of the present invention, two-stage grinding is used to achieve planarization. In other words, in step (c), chemical mechanical polishing is also first performed with a high-flatness polishing slurry to flatten the surface of the insulating layer above the shielding layer; and step (d) uses a polishing slurry with a 咼 selectivity. Polish until the masking layer (polishing stop layer) is completely exposed. In this method,

44703 Ί V. Description of the invention ¢ 5) (Grinding stop layer) · The thickness of the polishing slurry that reduces the height difference of the shielding layer can reduce the difference and reduce the oxidation of the grooves for the above and other purposes, features, And advantages can be more obvious and easy to understand 'the following is a description of the preferred embodiment, with the accompanying detailed description as follows: Khan [Simplified Description of the Figures] Figure 1 1B is a series of cross-sectional views' to show the formation of shallow trenches Problems caused by departure and known methods. Figures 2A to 2C are a series of cross-sectional views, which are used to explain the process of manufacturing a shallow trench isolation region according to a preferred embodiment of the present invention. [Symbol description] 100, 200 ~ semiconductor substrate; 110, 21〇 ~ pad oxide layer; 115, 215 ~ silicon nitride layer; 105, 105b, 105c, 10 5d, 20 5a, 205b, 20 5c, 20 ~ shallow trench; 120, 220, 220a, 220b ~ oxide layer. [First embodiment] Please refer to Figs. 2A to 2C, and Figs. 2A to 2C are diagrams for explaining a preferred embodiment of the shallow trench isolation process of the present invention. First, referring to FIG. 2A, the shallow trench isolation process of the present invention is applied to a semiconductor substrate 200, the surface of which is covered by a shielding layer 215, and a plurality of shallow trenches 205a, 205b, 205c, and 205d are formed on In the base. The shallow trenches 205a, 205b, 205c, 205 can be formed in the following manner:

447031 V. Description of the invention (6) * ~ First, a chemical oxide deposition (CVD) method or a thermal oxidation growth method is used to form a pad oxide layer 21 with a thickness of 50A and 200 people on the surface of the substrate 2000. A silicon nitride layer 215 having a thickness ^ between 500 A and 2000 A is deposited on the surface of the hafnium oxide layer 210 by CVD as a mask for etching the shallow trench f. Its-man 'forms an optical lithographic mask (not shown) on the nitrided layer 215. The above-mentioned optical lithography mask is subjected to an exposure procedure to form a pattern defining shallow trenches 205a, 205b, 205c, and 205d, and then the optical lithography mask is subjected to a development procedure to expose the semiconductor substrate. A shallow trench 205a will be formed , 205b, 205c, and 205d. After that, the silicon nitride layer 2 i 5, the pad-oxide layer 210, and a part of the semiconductor substrate 2000 are sequentially removed by a method such as reactive ion etching (RIE) to form a shallow trench 205 a, 205b, 205c, and 205d. Generally speaking, the depth of a shallow trench is between 3000A and 5000A. After that, a silicon oxide filler 220 is deposited on the surface of the semiconductor substrate 200 and fills the shallow trenches described above. The silicon oxide filler 2 220 can be produced by methods well known to those skilled in the art. These methods include: using various chemical vapor deposition (CVD) procedures, such as atmospheric pressure chemical vapor deposition (APCVD). Chemical vapor deposition (SACVD), low pressure chemical vapor deposition (LPCVD), or high density plasma chemical vapor deposition (HDPCVD) procedures, etc. Deposited as raw materials; or formed by spin-on-glass (SOG) technology. In addition, before the oxide layer 220 is deposited, a thin pad oxide layer (1 ini ng ox i de) can usually be formed on the bottom and sidewalls of the trench by thermal oxidation to ensure the interface quality of S i / S i 02 .

Page 9 44703 1 V. Description of the invention (7) Please refer to FIG. 2B 'to perform a chemical mechanical polishing procedure with a highly flat polishing slurry to planarize the surface of the oxide layer 220. The difference between the present invention and the above-mentioned conventional technique is that the grinding process is stopped before the nitrided stone layer 21 5 is exposed, leaving the remainder of the oxide layer 2 20a as shown in the figure. Note that the surface is still high. The surface of the silicon nitride layer 215 is exposed. Therefore, there is no problem of excessive grinding causing erosion of the nitrided dream layer 215 or formation of oxide dishing. The high flatness polishing slurry used in accordance with the present invention is one whose grinding thickness difference is less than 400 A, and the standard deviation of its uniformity is preferably less than 3%. For example, a slurry of HS-800 5 and HS-8102GP manufactured by Hitachi can be used for this grinding process. In addition, in order to achieve high flatness, in addition to using a high-flatness polishing liquid, it is best to perform under the conditions of low turntable pressure (3 ~ 5psi) and high turntable speed (80 ~ 120 r pm). . Referring to FIG. 2C, the portion of the oxide layer higher than the surface of the silicon nitride layer 2 1 5 is removed by wet etching (such as HF) or dry etching (such as CF4) until the silicon nitride layer 21 5 is exposed. The portion remaining in the shallow trench forms an element isolation region 220b. By removing the excess oxide layer on the substrate in this remaining step, it is possible to avoid uneven polishing speed caused by chemical mechanical polishing due to differences in underlying patterns. Finally, after the nitrided sand layer 2 15 and the pad oxide layer 2 10 are not removed by the wet etching method, a shallow trench isolation region with a uniform step height can be obtained. [First embodiment]

44703 1 V. Description of the invention (8) --- According to another preferred embodiment of the present invention, two-stage grinding is adopted to achieve flatness. As shown in FIG. 2B, in the first stage of polishing, the chemical mechanical polishing is also performed with a polishing slurry having a high flatness. After the surface of the oxide layer 22a is flattened, the second stage of polishing is performed. As shown in Fig. 2c, in this stage, the paddle liquid with high polishing selectivity is used for polishing until the silicon nitride layer 215 is completely exposed. In order to achieve a high selectivity, the grinding at this stage is preferably performed under conditions of a low turntable pressure (3 to 5 psi) and a low turntable speed (30 to 50 rpm). The polishing slurry with a high selectivity suitable for this embodiment is a silicon oxide / silicon nitride polishing selection ratio greater than 50, for example, GPL-C S2 11 5 manufactured by Shawa Deuk〇. The polishing selection ratio of silicon nitride is as high as 240_1. Therefore, using such a high-selectivity polishing slurry to perform subsequent polishing 'can greatly reduce the thickness difference of the silicon nitride layer 21 5 in different regions, and reduce the step height difference of the trench oxide 220a. Finally, after the silicon nitride layer 21 5 and the pad oxide layer 210 are removed by wet etching, a shallow trench isolation region with a uniform step height can also be obtained. In summary, the present invention is mainly to first planarize the surface of the oxide layer on the substrate with a high-flatness polishing slurry, and then use (1) etch-back or (2) high-selectivity chemical mechanical polishing to remove the excess on the substrate. An oxide layer to reduce the phenomenon of di shing and erosion caused by excessive grinding, and achieve a uniform step height. In addition, the method of the present invention can also cooperate with the conventional reverse tone pattern process, that is, add a lithography and remaining process to remove the oxide layer on the wide active area first, and then Chemical mechanical polishing will further improve page 11 of the table " ~ '4470 3 1 V. Description of the invention (9) The flatness of the surface. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application.

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Claims (1)

447031 1. A method for planarizing a shallow trench isolation region, comprising the following steps: (a) providing a semiconductor substrate whose surface is covered by at least a shielding layer, and a plurality of shallow trenches are formed in the substrate; (b) ) Depositing an insulating layer on the substrate to fill the shallow trenches; (c) performing chemical mechanical polishing with a polishing slurry having a local flatness, and planarizing the surface of the insulating layer before exposing the shielding layer; and (d) ) Etching to remove the excess insulating layer on the substrate until the shielding layer is exposed, leaving the insulating layer filled in the shallow trenches to form a shallow trench isolation region 2. A shallow trench as described in item 丨 of the scope of patent application A method of planarizing an isolation region 'wherein the shielding layer includes a nitride layer. 3. The method for planarizing a shallow trench isolation region according to item 1 of the scope of the patent application, wherein before step (b), the method further includes: forming a lining oxide on the bottom of the shallow trenches and the sidewalls. . 4. The method for planarizing a shallow trench isolation area as described in item 1 of the scope of patent application, wherein the material of the insulating layer is silicon oxide. 5 _ The method for planarizing a shallow trench isolation region as described in item 1 of the scope of patent application ', wherein the polishing slurry having a high flatness is one having a thickness difference of less than 400 A. ', 6. The flattening method for the shallow trench isolation area as described in Item 5 of the patent application park, wherein the high-flatness grinding slurry has a grinding thickness difference of less than 400 A' and a uniformity standard deviation of less than 3% By. '7. A method for planarizing a shallow trench isolation region as described in item 6 of the scope of the patent application', wherein the high flatness grinding liquid is a mixture of HS-800 5 and HS-8102GP manufactured by Hitachi. 447031 8. If the scope of the patent application is 1 / Bu Gubing, the method of isolating the shallow trenches of the basin by Feng…, where step (d) is a dry etching method 9, as described in the first scope of the scope of patent application Describing the method, "Step ⑷ is a method of flattening a shallow trench isolation area by using wet etching to isolate the area as described in item 1 of the scope of the patent, wherein after step 更, it further includes: removing the mask Floor. 11. A method for planarizing a shallow trench isolation region, suitable for use in a semiconductor substrate. The method includes the following steps: (a) Ki, a semiconductor substrate whose surface is covered by at least one shielding layer, and has a plurality of shallow trenches. Formed in the substrate; (b) depositing an insulating layer on the substrate to fill the shallow trench; (ct mechanically and mechanically polishing with a high-flatness slurry, the insulating layer is exposed before the shielding layer is exposed Surface flattening; and (d) chemical mechanical polishing with a high selection ratio polishing slurry until The shielding layer is exposed and the insulating layer filled in the shallow trenches is formed to form a shallow trench isolation region. 12. The flattening method for a shallow trench isolation region according to item 11 of the patent application, wherein the shielding layer includes a silicon nitride layer. 13. The method for planarizing a shallow trench isolation region as described in the item of the patent application, wherein before step (b), the method further comprises: forming a lining oxide layer on the bottom of the shallow trenches and the sidewall. oxide). 14. The method of flattening a shallow trench isolation region as described in item 11 of the patent scope of Shen Qing, wherein the material of the samarium insulating layer is silicon oxide. 15. The level of the shallow wide trench isolation area as described in item 11 of the Shenjing patent scope. Page 14 447031 VI. Scope of patent application Tanning method, where the grinding polymer with high flatness is the one whose grinding thickness difference is less than 40G A. 1 6. The method for planarizing a shallow trench isolation region as described in item 15 of the scope of the patent application, wherein the high-flatness polishing slurry is one having a thickness difference of less than 400 A and a standard deviation of uniformity of less than 3% . 1 7. The method of flattening a shallow trench isolation area as described in item 16 of the scope of patent application, wherein the high-flatness grinding slurry is a mixture of HS-8005 and HS-8102GP manufactured by Hitachi. 18 The flattening method for a shallow trench isolation region as described in item 11 of the scope of the patent application, wherein the polishing slurry with a high selection ratio is a silicon oxide / nitride grinding selection ratio greater than 50. 1 9. The flattening method for a shallow trench isolation area as described in item 11 of the scope of the patent application, wherein the polishing slurry with a high selection ratio is GPL-C S2115 manufactured by 诎 〇 ^ Deuk〇. 20. The method of flattening a shallow trench isolation region according to item U of the patent application, wherein after step (i), the method further comprises: removing the shielding layer. % 15 ^ 1 " " " '