445641 經濟部中央標準扃員工消費合作社印製 3992twi'.d〇c/008 Λ ^ ____ B7____ 五、發明説明（丨） 本發明是有關於一種半導體元件之製造方法’且特別 是有關於一種快閃記憶體之製造方法。 快閃記憶體是一種可抹除可編程唯讀記億體 (E2PROM)，其屬於一種非揮發性記憶體（non-volatile memory)結構。通常快閃記憶胞結構包括有兩個閘極’包 括用來儲存電荷的浮置閘（floating gate)，以及用來控制資 料存取的控制閘（control gate)。浮置閘位於控制閘下方， 其通常處於”浮置”的狀態，沒有和任何線路相連接，而控 制閘則通常與字元線相接。快閃記億胞的特色在於可以進 行” 一塊接著一塊’’(block by block)方式的抹除（erase)動 作’約在1到2秒之間即可完成。與傳統的E2PROM胞比 較起來，其是進行”一個位元接著一個位元”(bit by bit)方 式的抹除動作，至少要約數分鐘才能完成。因此，快閃記 憶胞比傳統的E2PROM胞的操作速度要快很多，使得快閃 記憶胞成爲積體電路元件中極受歡迎的一種記憶胞結構。 第1A圖至第1C圖是習知一種快閃記憶胞之部份製程 的俯視圖。爲淸楚描述起見，第1A圖至第1C圖之II-II 剖面圖繪示於第2A圖至第2C圖。 首先，請同時參照第1A圖和第2A圖，在所提供之基 底1〇〇上，形成塊狀的淺溝渠隔離結構102，以定義元件 出的主動區104。 接著，請同時參照第1Β圖和第2Β圖，於基底100的 主動區104上依序形成隧穿氧化層106和閘極導體層1〇8。 典型的方法係以熱氧化法形成隧穿氧化層106之後，在隧 3 本紙張適用中關家操準（CNS )八4麟· ( 21GX297^t] ' (請先閱讀背面之注意事項再填寫本頁) 445641 3992twf.doc/〇〇8 A7 B7 五、發明説明（7 ) 穿氧化層106上形成·一多晶矽層，然後再以傳統的微影蝕 刻方法’將多晶砂層圖案化，以形成閘極導體層108。 其後，請同時參照第1C圖和第2C圖，形成快閃記憶 胞的閘極結構114。典型的形成方法如下··首先以化學氣 相沈積法，在閘極導體層108上形成層一材料爲氧化矽-氮化矽-氧化矽（ΟΝΟ)之介電膜層110。之後在介電膜層110 上以化學氣相沈積法形成另一層多晶矽層112。然後，以 傳統的微影蝕刻技術，定義多晶矽層112、介電層110和 閘極導體層108，形成快閃記憶閘極結構114，其中多晶 矽層Π2作爲控制閘，閘極導體層ι〇8作爲浮置閘。接著 以離子植入法，對基底100進行摻雜，使形成源/汲極區 Η6、118，完成快閃記憶胞之製作。 由上述習知方法製作之快閃記憶胞，具有許多缺點。 請參照第3圖，其繪示習知快閃記憶胞局部結構的上視圖。 淺溝渠隔離結構102和主動區1〇1係在製作閘極導體層108 前形成的，因此在形成閘極導體層108時，便有對不準 (Misalign )問題產生。一般都會將閘極導體層之寬度 124製作略大於主動區104，使其與淺溝渠隔離結構102， 在邊緣處有些微重疊（如第3圖之標號120)，以避免對不 準問題。然而，如此卻使積集度無法提高。 此外’與閘極導體層108相似，控制閘層丨12亦受到 對不準問題之困擾，容易因對不準而超出隔離結構104之 外’而使得主動區與閘極導體層108之間重疊的面積改變 (如第3圖標號122所示），造成相鄰的記憶胞之間的耦合 (請先閲讀背面之注意事項再填寫本瓦) -5 經濟部中央標準局員工消費合作社印製 本纸張尺度適用中國國家橾率（CNS ) A4現格（21〇X29*j公釐） 1 經濟部中央標準局負工消費合作耔印製 445641 a 7 3992t\vf doc/008 B7 五、發明説明（π ) 比（Coupling Ratio)不同，產生奇-偶（Odd-Even)現象。 再者，爲提高集積度，淺溝渠隔離結構102之間的距 離愈小愈好。然而淺溝渠隔離結構102之間的距離128愈 小，則其源/汲極區116的面積變小，使阻値愈高（電阻與 面積成反比），而多晶矽層Π2之間的距離126受到淺溝 渠隔離結構102之間距離128的限制，不能縮小，造成積 集度無法提高。 因此本發明的目的就是在提供一種快閃記憶體之製造 方法。其方法可提高元件之積集度，避免對不準問題，而 且形成每個快閃快記憶胞之控制閘和浮置閘的耦合比相 等，可避免奇-偶的問題產生。 根據本發明之上述目的，提出一種快閃記憶體之製造 方法，其簡述如下：在基底上依序形成一隧穿氧化層、一 第一導體層、第一罩幕層和一第一氧化層。然後定義第一 導體層、第一氮化矽層和第一氧化層，以形成一閘極層。 接著在基底上形成與基底共形之第二氧化層。然後在依附 於閘極層側壁之第二氧化層外側形成一間隙壁。之後以閘 極層、依附於閘極層側壁之第二氧化層和間隙壁爲罩幕， 進行-第·摻離步驟，以在基底中形成第一摻雜區。之後， 去除間隙壁，並在基底上形成已圖案化之一第二罩幕層， 其中第二罩幕層垂直於閘極層。接著以閘極層和第二罩幕 層爲罩幕，在基底中形成一淺溝渠隔離結構，其中定義在 該閘極層下方之該基底爲行主動區，在該第二罩幕層之下 方之該基底爲列主動區。然後去除第一罩幕層和第二罩幕 5 (請先閱讀背面之注意事項再填寫本頁) 裝.445641 Central Standard of the Ministry of Economic Affairs, printed by employee consumer cooperatives 3992twi'.doc / 008 Λ ^ __ B7____ V. Description of the Invention (丨) The present invention relates to a method for manufacturing a semiconductor device, and particularly to a flash Manufacturing method of memory. Flash memory is an erasable and programmable read-only memory (E2PROM), which belongs to a non-volatile memory structure. Generally, the flash memory cell structure includes two gates', including a floating gate for storing electric charge, and a control gate for controlling data access. The floating gate is located below the control gate. It is usually in the "floating" state and is not connected to any line. The control gate is usually connected to the word line. The feature of flash memory is that it can be performed in a "block by block" erase operation in about 1 to 2 seconds. Compared with the traditional E2PROM cell, its It is a "bit by bit" erasing action that takes at least a few minutes to complete. Therefore, the flash memory cell operates much faster than the traditional E2PROM cell, making the flash memory much faster. Memory cells have become a very popular memory cell structure in integrated circuit components. Figures 1A to 1C are top views of some processes of a conventional flash memory cell. For the sake of description, Figures 1A to 1 Section II-II of Figure 1C is shown in Figures 2A to 2C. First, please refer to Figures 1A and 2A at the same time to form a block-shaped shallow trench isolation on the provided substrate 100 The structure 102 defines the active area 104 of the device. Next, referring to FIG. 1B and FIG. 2B, a tunnel oxide layer 106 and a gate conductor layer 108 are sequentially formed on the active area 104 of the substrate 100. Typical method is thermal oxidation After layer 106, in the tunnel 3 papers are applicable to Zhongguanjiaquan (CNS) 8 4 Lin (21GX297 ^ t) '(Please read the precautions on the back before filling this page) 445641 3992twf.doc / 〇〇8 A7 B7 5 7. Description of the Invention (7) A polycrystalline silicon layer is formed on the through-oxide layer 106, and then the polycrystalline sand layer is patterned by the traditional lithographic etching method to form the gate conductor layer 108. Thereafter, please refer to 1C at the same time Figure and Figure 2C, the gate structure 114 of the flash memory cell is formed. A typical formation method is as follows. First, a layer is formed on the gate conductor layer 108 by a chemical vapor deposition method. A material is silicon oxide-silicon nitride. -A silicon oxide (ON) dielectric film layer 110. Then, another polycrystalline silicon layer 112 is formed on the dielectric film layer 110 by a chemical vapor deposition method. Then, a conventional lithographic etching technique is used to define the polycrystalline silicon layer 112, the dielectric The electrical layer 110 and the gate conductor layer 108 form a flash memory gate structure 114, in which the polycrystalline silicon layer Π2 is used as a control gate, and the gate conductor layer ι8 is used as a floating gate. Then, the substrate 100 is subjected to ion implantation. Doping to form source / drain regions Η6,118, complete The production of flash memory cells. The flash memory cells produced by the above-mentioned conventional methods have many disadvantages. Please refer to FIG. 3, which shows a top view of the local structure of the conventional flash memory cells. The shallow trench isolation structure 102 and The active region 101 is formed before the gate conductor layer 108 is produced, so when the gate conductor layer 108 is formed, a misalignment problem occurs. Generally, the width 124 of the gate conductor layer is made slightly. Larger than the active area 104, it is slightly overlapped with the shallow trench isolation structure 102 at the edges (such as 120 in FIG. 3) to avoid misalignment. However, this does not improve the degree of accumulation. In addition, 'similar to the gate conductor layer 108, the control gate layer 12 is also plagued by the problem of misalignment, and it is easy to exceed the isolation structure 104 due to the misalignment', so that the active area and the gate conductor layer 108 overlap. The area change (as shown in the third icon number 122), resulting in coupling between adjacent memory cells (please read the precautions on the back before filling in this tile) -5 Printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Paper size applies to China's national standard (CNS) A4 (21 × 29 * j mm) 1 Central Government Bureau of Ministry of Economic Affairs and Consumer Cooperative Printing 445641 a 7 3992t \ vf doc / 008 B7 V. Description of the invention The (π) ratio is different, resulting in an Odd-Even phenomenon. Furthermore, in order to improve the degree of accumulation, the smaller the distance between the shallow trench isolation structures 102 is, the better. However, the smaller the distance 128 between the shallow trench isolation structures 102, the smaller the area of the source / drain region 116, the higher the resistance (resistance is inversely proportional to the area), and the distance 126 between the polycrystalline silicon layers Π2 is affected by The limitation of the distance 128 between the shallow trench isolation structures 102 cannot be reduced, so that the accumulation degree cannot be improved. It is therefore an object of the present invention to provide a method for manufacturing a flash memory. The method can improve the accumulation degree of components, avoid misalignment problems, and form the coupling ratio of the control gate and floating gate of each flash memory cell to be equal, which can avoid the odd-even problem. According to the above object of the present invention, a method for manufacturing a flash memory is provided, which is briefly described as follows: a tunneling oxide layer, a first conductor layer, a first mask layer, and a first oxide are sequentially formed on a substrate. Floor. Then define a first conductor layer, a first silicon nitride layer and a first oxide layer to form a gate layer. A second oxide layer conforming to the substrate is then formed on the substrate. A gap wall is then formed on the outside of the second oxide layer attached to the side wall of the gate layer. Then, the gate layer, the second oxide layer attached to the sidewall of the gate layer, and the spacer wall are used as a mask to perform a first-doping step to form a first doped region in the substrate. After that, the spacer wall is removed, and a patterned second mask layer is formed on the substrate, wherein the second mask layer is perpendicular to the gate layer. Next, a gate layer and a second mask layer are used as a mask to form a shallow trench isolation structure in the substrate. The substrate defined below the gate layer is a row active area, and is below the second mask layer. The base is the active area. Then remove the first cover and the second cover 5 (Please read the precautions on the back before filling this page).
iT 本紙張尺度適用中國國家標牟（CNS ) A4規格（210X297公釐） 經濟部中失標準局員工消費合作私印聚 445641 3 y 9 2 l v\ 1'. d 〇 c / 0 0 8 五、發明説明（C ) 層，暴露出第一導體層。接著形成一介電膜層於基底整面 上。之後形成一第二導體層於基底上，定義第二導體層、 介電膜層和閘極層，以使第二導體層形成一控制閘層，且 該閘極層形成一浮置閘層，其中該控制閘層與列主動區部 份重疊。最後，進行一第二摻雜步驟完成快閃記憶胞之製 作。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1A圖至第1C圖是習知一種快閃記憶胞之部份製程 的俯視圖； 第2A圖至第2C圖是第1A圖至第1C圖之II-II剖面 圖； 第3圖是第1C圖中習知快閃記憶胞局部結構的上視 圖； 第4A圖至第4H圖爲根據本發明之一較佳實施例，一 種快閃記憶胞之製程示意俯視圖； 第5A圖至第5H圖爲第4A圖至第4H圖之V - V剖面 圖； 第6圖爲第4D圖之VI-VI剖面圖；以及 第7圖爲第4H圖的VH-W剖面圖。 圖式之標記說明： 100、200 :基底 6 裝 訂r (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 445641 經濟部中央標準局員工消費合作社印製 五、發明説明（t) 102、224 :隔離結構 104 :主動區 106、202 :隧穿氧化層 108、206 :閘極導體層 110、228、228a、230a :介電膜層 112 ;控制閘層 114 :快閃記憶閘極結構 116、1 18 :源/汲極區 120 :浮置閘層與隔離結構重疊區 122 :控制閘對不準之面積偏差 124 :浮置閘層寬度 126 ' 236 :控制閘距離 128、234 :隔離結構之距離 201 :行方向 203 :列方向 204 :閘極層 206a :浮置閘層 208、218 :罩幕層 210、212 :氧化層 214 :間隙壁 216 :離子植入步驟 217 :第一摻雜區 219 :行主動區 220 :列主動區 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 445 6 4 1 3^92t wl'.doc/008 A7 B7 五、發明説明（) 222 :溝渠 226 :襯氧化層 23(^導體層 232 :列主動區未被控制閘層遮蓋之區域 235 :源/汲極區 實施例 第4A圖至第4H圖其繪示依照本發明一較佳實施例， 〜種快閃記憶胞之部份製程的俯視圖。爲淸楚描述起見， 第4A圖至第4C圖之V，V剖面圖繪示於第5A圖至第5C 圖；第4D圖之νι_νι剖面圖繪示於第6D圖；第4E圖至 第4H圖之V-V剖面圖繪示於第5E圖至第5H圖：第4H 圖的W-Vn剖面圖繪示於第7圖。 首先，請同時參照第4Α圖和第5Α圖，提供一基底200， 基底200上已形成一層隧穿氧化層202。在基底200上具 有一行方向201和一列方向203。典型的基底200之材質 包括矽，例如，ρ型矽。較佳的隧穿氧化層202之材質例 如爲二氧化矽，其形成的方法例如爲熱氧化法。接著在燧 穿氧化層上形一閘極層204，使閘極層2〇4平行於行方向 201，其中此閘極層204自下而上依序爲導體層206、罩幕 層208和氧化層210。閘極層2〇4較佳的形成方式爲在隧 穿氧化層202上依序形成導體層、罩幕層和氧化層結構（圖 中未繪出），再定義導體層、罩幕層和氧化層以形成閘極 層2〇4。例如以化學氣相沈積法形成一多晶矽層於隧穿氧 化層202上。接著，例如以化學氣相沈積法在多晶矽層上 8 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） c請先閲讀背面之注意事項再填寫本頁) Τ 經濟部中央棹準局員工消費合作社印装 A7 B7 445 64 3992twi' doc/()08 五、發明説明（1) 形成氮化矽層。然後，例如以化學氣相沈積法在氮化矽層 上形成二氧化矽層。最後例如以乾蝕刻法定義二氧化矽 層、氮化矽層和多晶矽層，以形成閘極層204。 請同時參照第4B圖和第5B圖，接著，在閘極層204 和基底2〇0的表面上形成氧化層212。氧化層212的材質 例如是二氧化矽，形成的方法例如爲化學氣相沈積法。然 後，在依附於閘極層204側壁之氧化層212的外側，形成 間隙壁2丨4。閘隙壁的材質例如爲氮化矽，其形成的方法 例如是先以化學氣相沈積法在氧化層212表面上形成氮化 矽層，再以非等向性蝕刻法回蝕刻此氮化矽層，則可形成 間隙壁214之結構。 然後，請同時參照第4C圖和第5C圖，以閘極層2〇4、 依附在閘極層204側壁之氧化層212和間隙壁214爲罩幕， 對基底200進行摻離步驟216，以在基底200中形成第一 摻雜區217，例如以離子植入法植入n型離子（比如磷或 砷）1植入的深度較佳約爲500-1500A左右。 請參照第4D圖、第5D圖和第6圖，其中第5D圖係 爲第4〇圖之乂-¥剖面圖，第6圖爲第40圖之'\/1-¥1剖面 圖。接著去除間隙壁214，並在基底200上形成圖案化之 罩幕層218，其中罩幕層218平行於列方向203。去除間 隙壁214的方法例如爲濕式蝕刻法。罩幕層218的材質例 如爲氮化矽，其形成方法例如先以化學氣相沈積在基底200 整個表面上形成一氮化矽層，再以傳統的微影蝕刻法將氮 化矽層圖案化，以形成罩幕層218。爲方便區別，定義在 9 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ¢3 (請先閱讀背面之注意事項再填寫本頁)iT This paper size is applicable to China National Standards (CNS) A4 specification (210X297 mm). Employees ’cooperation cooperation of the China Bureau of Standards and Loss Standards, Private Printing 445641 3 y 9 2 lv \ 1 '. d 〇c / 0 0 8 V. Description of the invention (C) layer, exposing the first conductor layer. A dielectric film layer is then formed on the entire surface of the substrate. Forming a second conductor layer on the substrate, defining the second conductor layer, the dielectric film layer and the gate layer, so that the second conductor layer forms a control gate layer, and the gate layer forms a floating gate layer, The control gate layer partially overlaps the active area of the column. Finally, a second doping step is performed to complete the fabrication of the flash memory cell. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is described below in detail with the accompanying drawings as follows: Brief description of the drawings: FIG. 1A Fig. 1 to Fig. 1C are top views of a part of a conventional flash memory cell manufacturing process; Figs. 2A to 2C are II-II cross-sectional views of Figs. 1A to 1C; Fig. 3 is a drawing of Fig. 1C. Top view of the local structure of the flash memory cell; Figures 4A to 4H are schematic top views of a flash memory cell process according to a preferred embodiment of the present invention; Figures 5A to 5H are Figure 4A Section V-V to Figure 4H; Figure 6 is a VI-VI Section of Figure 4D; and Figure 7 is a VH-W Section of Figure 4H. Explanation of drawing marks: 100, 200: base 6 binding r (please read the notes on the back before filling this page) This paper size applies to China National Standard (CNS) A4 size (210X297 mm) 445641 Central Bureau of Standards, Ministry of Economic Affairs Printed by the employee consumer cooperative V. Description of the invention (t) 102, 224: Isolation structure 104: Active area 106, 202: Tunneling oxide layer 108, 206: Gate conductor layer 110, 228, 228a, 230a: Dielectric film layer 112; control gate 114: flash memory gate structure 116, 1 18: source / drain region 120: floating gate layer and isolation structure overlap area 122: area deviation of control gate misalignment 124: floating gate layer Width 126 '236: Control gate distance 128, 234: Distance of isolation structure 201: Row direction 203: Column direction 204: Gate layer 206a: Floating gate layer 208, 218: Mask layer 210, 212: Oxide layer 214: Spacer wall 216: Ion implantation step 217: First doped region 219: Row active region 220: Column active region (please read the precautions on the back before filling this page) This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 445 6 4 1 3 ^ 92t wl'.doc / 008 A7 B7 five Description of the invention (222): trench 226: lining oxide layer 23 (conductor layer 232: area where the column active area is not covered by the control gate layer) 235: source / drain region embodiment 4A to 4H. According to a preferred embodiment of the present invention, a top view of a part of a flash memory cell manufacturing process. For the sake of description, the V and V cross-sectional views of FIGS. 4A to 4C are shown in FIGS. 5A to 5 Figure 5C; Section νι_νι of Figure 4D is shown in Figure 6D; Sections VV of Figures 4E to 4H are shown in Figures 5E to 5H: Figure W-Vn of Figure 4H is shown It is shown in Fig. 7. First, please refer to Figs. 4A and 5A simultaneously to provide a substrate 200. A layer of tunneling oxide layer 202 has been formed on the substrate 200. The substrate 200 has a row direction 201 and a column direction 203. Typical The material of the substrate 200 includes silicon, for example, p-type silicon. The preferred material for the tunneling oxide layer 202 is, for example, silicon dioxide, and the method for forming it is, for example, a thermal oxidation method. Then, a gate is formed on the pierced oxide layer. Layer 204, so that the gate layer 204 is parallel to the row direction 201, wherein the gate layer 204 is a conductor layer 206, The mask layer 208 and the oxide layer 210. The gate electrode layer 204 is preferably formed by sequentially forming a conductor layer, a mask layer, and an oxide layer structure (not shown) on the tunneling oxide layer 202, and then The conductor layer, the mask layer and the oxide layer are defined to form the gate layer 204. For example, a polycrystalline silicon layer is formed on the tunneling oxide layer 202 by a chemical vapor deposition method. Then, for example, by chemical vapor deposition on a polycrystalline silicon layer, 8 paper sizes are applicable to the Chinese National Standard (CNS) A4 (210X297 mm) c. Please read the precautions on the back before filling in this page) Τ Central Ministry of Economic Affairs A7 B7 445 64 3992twi 'doc / () 08 printed by the Consumer Cooperatives of the Bureau V. Description of the invention (1) Forming a silicon nitride layer. Then, a silicon dioxide layer is formed on the silicon nitride layer by, for example, a chemical vapor deposition method. Finally, the silicon dioxide layer, the silicon nitride layer, and the polycrystalline silicon layer are defined by, for example, a dry etching method to form the gate layer 204. Please refer to FIG. 4B and FIG. 5B at the same time, and then, an oxide layer 212 is formed on the surfaces of the gate layer 204 and the substrate 2000. The material of the oxide layer 212 is, for example, silicon dioxide, and a method of forming the oxide layer 212 is, for example, a chemical vapor deposition method. Then, on the outside of the oxide layer 212 attached to the side wall of the gate layer 204, a partition wall 21-4 is formed. The material of the gate gap wall is, for example, silicon nitride, and the formation method is, for example, first forming a silicon nitride layer on the surface of the oxide layer 212 by chemical vapor deposition, and then etching back the silicon nitride by anisotropic etching. Layer, the structure of the partition wall 214 can be formed. Then, referring to FIG. 4C and FIG. 5C at the same time, with the gate layer 204, the oxide layer 212 attached to the side wall of the gate layer 204, and the spacer 214 as a mask, a doping step 216 is performed on the substrate 200 to A first doped region 217 is formed in the substrate 200. For example, an n-type ion (such as phosphorus or arsenic) is implanted by an ion implantation method. The implantation depth is preferably about 500-1500A. Please refer to Figure 4D, Figure 5D and Figure 6, where Figure 5D is a 乂-¥ cross-section view of Figure 40, and Figure 6 is a '\ / 1- ¥ 1 cross-section view of Figure 40. Then, the spacer 214 is removed, and a patterned mask layer 218 is formed on the substrate 200, wherein the mask layer 218 is parallel to the column direction 203. A method of removing the spacer 214 is, for example, a wet etching method. The material of the mask layer 218 is, for example, silicon nitride, and a method for forming the mask layer 218 is, for example, first forming a silicon nitride layer on the entire surface of the substrate 200 by chemical vapor deposition, and then patterning the silicon nitride layer by a conventional lithographic etching method. To form a cover layer 218. In order to facilitate the distinction, it is defined in 9 paper sizes that apply the Chinese National Standard (CNS) A4 specification (210X297 mm) ¢ 3 (Please read the precautions on the back before filling this page)
T 乡 經濟部中央梯準局—工消費合作社印聚 445641 3992[\\ Γ :/008 A7 B7 經濟部f央榡準局員工消費合作社印家 五、發明説明（） 閘極層2〇4下方之基底200爲行主動區219，在罩幕層218 下方之基底200爲列主動區220。 請同時參照第4E圖和第5E圖，然後在未被閘極層204 和罩幕層218所遮蓋的部份基底200中形成溝渠222。例 如以閘極層204和罩幕層218爲罩幕，對基底200進行非 等向性乾蝕刻法，去除未被閘極層204和罩幕層21S所遮 蓋的部份基底200，以在基底200中，形成溝渠222。其 中被閘極層204和罩幕層218所遮蓋的區域爲主動區（亦 即行主動區219和列主動區220之總和）。 然後，請同時參照第4F圖和第5F圖，在溝渠222中 形成淺溝渠隔離結構224，並去除罩幕層21S、氧化層210 和罩幕層208，暴露出導體層206之上表面。淺溝渠隔離 結構224的形成方式爲在暴露於溝渠222之基底200表面 上，先形成一襯氧化層226。再形成一氧化層於整個基底 200表面並塡滿溝渠222，然後去除溝渠222以外之氧化 層以形成淺溝渠隔離結構例如先進行一熱氧化法， 以形成襯氧化層226，再以化學氣相沈積法形成二氧化矽 層塡滿溝渠222，之後例如以化學機械硏磨法（CMP)去除 溝渠222以外之二氧化矽層’而形成淺溝渠隔離結構224。 然後例如利用濕式蝕刻法以導體層206爲蝕刻終點，去除 罩幕層218、氧化層210和罩幕層208，暴露出導體層2〇6 表面。 在第4E圖 '第4F圖、第5E圖和第5F圖中所顯示之 步驟，係用以定義出元件的主動區和隔離區。由於在此主 料賴家鮮（CNS )八4胁(210X297公釐） r^— 訂r (請先閱讀背面之注意事項再填寫本育) 445641T Township Central Government Bureau of the Ministry of Economic Affairs—Industrial and Consumer Cooperatives Cooperative Printing 445641 3992 [\\ Γ: / 008 A7 B7 Ministry of Economic Affairs and Central Government Procurement Bureau Staff Consumer Cooperatives Cooperatives 5. Description of the Invention () Below the gate layer 204 The substrate 200 is a row active region 219, and the substrate 200 below the mask layer 218 is a column active region 220. Please refer to FIG. 4E and FIG. 5E at the same time, and then form a trench 222 in a part of the substrate 200 not covered by the gate layer 204 and the mask layer 218. For example, using the gate layer 204 and the mask layer 218 as a mask, the substrate 200 is subjected to anisotropic dry etching to remove a part of the substrate 200 that is not covered by the gate layer 204 and the mask layer 21S. In 200, a trench 222 is formed. The area covered by the gate layer 204 and the mask layer 218 is the active area (that is, the sum of the row active area 219 and the column active area 220). Then, referring to FIG. 4F and FIG. 5F at the same time, a shallow trench isolation structure 224 is formed in the trench 222, and the mask layer 21S, the oxide layer 210, and the mask layer 208 are removed to expose the upper surface of the conductor layer 206. The shallow trench isolation structure 224 is formed by first forming a liner oxide layer 226 on the surface of the substrate 200 exposed to the trench 222. An oxide layer is formed on the entire surface of the substrate 200 and fills the trench 222, and then the oxide layer outside the trench 222 is removed to form a shallow trench isolation structure. For example, a thermal oxidation method is first performed to form a liner oxide layer 226, and then a chemical vapor phase is used. The deposition method forms a silicon dioxide layer to fill the trench 222, and then, for example, a chemical mechanical honing method (CMP) is used to remove the silicon dioxide layer outside the trench 222 to form a shallow trench isolation structure 224. Then, the wet etching method is used to remove the mask layer 218, the oxide layer 210, and the mask layer 208 with the conductor layer 206 as an etching end point, and the surface of the conductor layer 206 is exposed. The steps shown in Figures 4E, 4F, 5E, and 5F are used to define the active and isolated regions of the component. As the main ingredients here is Lai Jiaxian (CNS) Ya 4 threats (210X297 mm) r ^ — order r (please read the precautions on the back before filling in this education) 445641
3992ixvf.doc/00X A7 B7 五、發明说明（"ί ) 動區係以閘極層204以及罩幕層218作爲罩幕而形成，故 所形成之主動區與閘極層204和罩幕層218下方之基底完 全重疊（亦即行主動區219與閘極層204下方之基底完全 重疊，列主動區220與罩幕層218下方之基底完全重疊p 且其淺溝渠隔離結構224亦因此而具有自動對準之功能， 而可免於習知的對不準之問題。 接著，請同時參照第4G圖與第5G圖，形成一層介 電膜層228於基底200的整個表面上，介電膜層228之材 質例如爲氧化矽-氮化矽-氧化矽結構（ΟΝΟ)，形成的方法 比如爲化學氣相沈積法。然後，在介電膜層228上形成一 層導體層230，例如是以化學氣相沈積法沈積之多晶矽層。 之後，請同時參照第4Η與第5Η圖，定義導體層230、 介電膜層228和導體層206，以使導體層230形成控制閘 層230a，導體層206形成浮置閘層206a。例如以傳統的 微影蝕刻法進行蝕刻，以將導體層230 '介電膜層228和 導體層206圖案化。其中形成之控制閘層230a平行於列 方向203，且控制閘層2：30a與浮置閘層之間爲介電膜層 228a。控制閘層230a與列主動區220有部份重疊。之後， 進行一摻雜步驟，將列主動區220和行主動區219中，未 被控制閘層230a遮蔽之區域植入離子，以在部份行主動 區219中形成源/汲區235，及在列主動區220，未被控制 閘層230a遮蔽之區域232形成一共源極（或汲極）結構而導 電，完成本發明快閃記憶胞之製作。 由於本發明之主動區係與閘極層204同時形成，其所 本紙張尺度適用中國國家標牟（CNS) A4規格（2I〇X297公釐） ^^i-n · - ^^^1 1^1 ^^^1 —Lr -- - -I (請先閱讀背面之注意事項存填寫本頁) 、tr 經濟部中央標準局貝工消費合作社印袋 445 64 3992tw l'.(ioc/008 A7 B7 五、發明説明（γ) 主動區與閘極層204 —致，當後續形成控制閘時，即使在 對準時產生誤差，其浮置閘與基底重疊之面積不會改變而 不會有奇偶問題產生。 . 請參照同時參照第4Η圖與第7圖，其中第7圖爲第 4Η圖中的VH-W剖面圖。由於列主動區；220的寬度234(亦 即兩淺溝渠隔離結構102間的距離234)在控制閘230a製 作前已經形成，而後續製作控制閘230a時，控制閘230a 間的距離236，較不會受到列主動區220的寬度234之限 制，故控制閘230a之間的距離236可小於淺溝渠隔離結 構202間的距離234，而不會增加在形成列主動區220之 共源極(或汲極）之阻値，故可提高積集度。 由上述本發明較佳實施例可知，應用本發明具有下列 優點： 1. 在定義主動區和隔離結構前，先形成閘極層，再依 閘極層之位置定義隔離結構。由於主動區係以閘極層爲罩 幕進行定義，其所定義出之主動區與閘極層一致，故具有 自對準功能，而可免於習知的對不準之問題。 2. 控制閘層之間的距離可小於隔離結構之間的距離， 可提高元件的積集度而不降低形成在列主動區之共源極 (或汲極）之阻値。 3. 由於主動區與閘極層相當一致，故當控制閘層對準 產生誤差時，其控制閘層與浮置閘層重疊的面積還是不 變。因此，不會如習知方法因控制閘層對不準而產生耦合 比不同，故可避免造成奇偶問題。 12 本紙張尺度適用中國固家標準（CNS ) A4规格（2丨0X297公4 ) I I I n n n -- .- ' 1/ n n n (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消費合作社印製 445641 洲丨'、，心屬 A7 B7 五、發明説明（（（） 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標率局員工消资合作社印製 本紙張尺度適用中國國家標率（CNS ) A4規格（210X297公釐）3992ixvf.doc / 00X A7 B7 V. Description of the invention (") The active region is formed by using the gate layer 204 and the mask layer 218 as the mask, so the active region formed with the gate layer 204 and the mask layer The substrate below 218 completely overlaps (that is, the row active region 219 and the substrate below the gate layer 204 completely overlap, the row active region 220 and the substrate below the mask layer 218 completely overlap p, and its shallow trench isolation structure 224 also has automatic The alignment function can avoid the conventional problem of misalignment. Next, please refer to FIG. 4G and FIG. 5G at the same time to form a dielectric film layer 228 on the entire surface of the substrate 200. The dielectric film layer The material of 228 is, for example, a silicon oxide-silicon nitride-silicon oxide structure (ONO), and the formation method is, for example, chemical vapor deposition. Then, a conductive layer 230 is formed on the dielectric film layer 228, for example, using chemical gas. Polycrystalline silicon layer deposited by phase deposition method. After that, please refer to Figures 4 and 5 to define the conductor layer 230, the dielectric film layer 228, and the conductor layer 206, so that the conductor layer 230 forms the control gate layer 230a and the conductor layer 206 is formed. Floating gate layer 206a. The lithographic etching method is used to pattern the conductive layer 230 ′, the dielectric film layer 228, and the conductive layer 206. The control gate layer 230a formed therein is parallel to the column direction 203, and the control gate layer 2: 30a and the floating gate layer are formed. Between them is a dielectric film layer 228a. The control gate layer 230a partially overlaps with the column active region 220. Then, a doping step is performed to shield the column active region 220 and the row active region 219 without being shielded by the control gate layer 230a. Ions are implanted in the regions to form source / drain regions 235 in part of the row active regions 219, and in the column active regions 220, the regions 232 uncovered by the control gate layer 230a form a common source (or drain) structure. It is conductive to complete the production of the flash memory cell of the present invention. Since the active region of the present invention is formed at the same time as the gate layer 204, its paper size is applicable to the Chinese National Standards (CNS) A4 specification (2IO × 297 mm) ^ ^ in ·-^^^ 1 1 ^ 1 ^^^ 1 —Lr---I (Please read the notes on the back and fill in this page first), tr Printing bag 445 64 3992tw l '. (Ioc / 008 A7 B7 V. Description of the invention (γ) Active region and gate layer 204 are the same, when When the control gate is continuously formed, even if an error occurs during alignment, the area where the floating gate overlaps with the substrate will not change without parity problems. Please refer to Figure 4 and Figure 7 at the same time, of which Figure 7 It is the VH-W cross-sectional view in Figure 4. Due to the active area of the column; the width 234 of 220 (that is, the distance 234 between the two shallow trench isolation structures 102) has been formed before the control gate 230a is manufactured, and the subsequent production of the control gate 230a At this time, the distance 236 between the control gates 230a is less limited by the width 234 of the active column 220. Therefore, the distance 236 between the control gates 230a can be smaller than the distance 234 between the shallow trench isolation structures 202 without increasing the Forming a common source (or drain) barrier of the column active region 220 can increase the degree of accumulation. As can be seen from the above preferred embodiments of the present invention, the application of the present invention has the following advantages: 1. Before defining the active area and the isolation structure, first form a gate layer, and then define the isolation structure according to the position of the gate layer. Since the active area is defined by using the gate layer as a mask, the active area defined by the active area is consistent with the gate layer, so it has a self-alignment function, which can avoid the conventional problem of misalignment. 2. The distance between the control gate layers can be smaller than the distance between the isolation structures, which can increase the accumulation of the components without reducing the resistance of the common source (or drain) formed in the active area of the column. 3. Since the active area is quite consistent with the gate layer, when the control gate layer is misaligned, the area where the control gate layer and the floating gate layer overlap remains unchanged. Therefore, the coupling ratio will not be different due to inaccurate control of the sluice as in the conventional method, so the parity problem can be avoided. 12 This paper size is in accordance with China Goods Standard (CNS) A4 specification (2 丨 0X297 male 4) III nnn-.- '1 / nnn (Please read the notes on the back before filling this page) Printed by the Industrial and Consumer Cooperatives 445641 Continental, A7, B7 V. Invention Description ((() Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention, anyone skilled in this art Without departing from the spirit and scope of the present invention, various modifications and retouching can be made. Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application. (Please read the precautions on the back before reading) (Fill in this page) Printed by the staff of the Central Standardization Bureau of the Ministry of Economic Affairs, Consumers' Cooperatives, this paper is sized for China National Standards (CNS) A4 (210X297 mm)