442840 6027twf.doc/008 AT B7 -- 五 經濟部智慧財產局員工消費合作社印製 發明說明（丨） 本發明是有關於一種高頻承載器測試晶片’且特別 是有關於一種用於高頻承載器之基板型電性測試晶片° 半導體積體電路晶片通常不單獨存在’而爱透過輸 出入系統與其他晶片電路交互連接。半導體晶片及內部電 路非常複雜，需要構裝體(package)來保護及攜帶，因此電 子構裝的主要功能包括：（1)提供電流路徑以驅動晶片上的 電路；（2)分佈晶片進出之訊號；（3)將電路産生的熱能發 散至外界：（4)在具破壞性的環境中保護晶片。由於半導體 元件的積集度逐漸提高，多功能高容量高處理速度卻面積 極小的產品相形增加，相對地，構裝技術的發展也朝向高 密度、高腳位、高頻率及高效能的半導體構裝發展。而現 今提供半導體元件構裝之承載器種類更是琳瑯滿目，包括 導線架型承載器（Ieadframe)、硬式基板型承載器（riglcj substrate)、軟式基板型承載器（flex substrate)，晶圓級構 裝承載器（wafer level package)，陶瓷基板承載器卜咖^^ substrate)等，可以形成各式各樣的構裝結構。由於積體電 路元件之處理速度要求逐漸提高，以個人電腦而言，中央 處理單元（CPU)的處理速度已進入十億赫茲(GHz)的時代 而對於通訊產品更是有諸多高頻半導體元件。因此， 對於構裝承載器（carrier)在電性上表現要求也會相對$ 高，尤其是在高頻操作時的效能，更是承載器品莺的嬖^ 重點。 -、荽求 傳統上對於承載器的電性檢測，不論是導線架刑 軟式基板型或硬式基板型等，都是藉由一短路測試〇 t纸張尺度適用中國國家標準（CNS>A4規格（21〇 X 297公望） (請先閱讀背面之注意事項再填寫本頁) -裝-------1 訂--------- 442840 A7 經濟部智慧財產局員工消費合作社印製 6027twf.doc 扇8 B7 五、發明說明（7/ ) 及一開路測試（open)，以萃取承載器本身的電性參數，比 如承載器所提供訊號路徑的電阻(R)、電感（L)、電容値(C)。 然而，這樣的測試對於未來高頻操作時，並無法確保其效 能及良率。舉例來說，藉由上述測試方法，並無法獲知高 頻操作時，承載器訊號路徑的干擾現象，訊號損失、訊號 衰減等表現。因此，現今對於高頻承載器通常還需做進一 步檢測，模擬晶片經過貼附（die attaching)、打導線（wue bonding)、封裝（encapsulating)後，整個回路在高頻操作的 電性特性。 因此本發明的目的之一就是在提供一種基板型電性 測試晶片，提供承載器進行高頻檢測。 本發明的另一目的就是提供一種非矽或砷化鎵的測 試晶片，可以大幅降低測試晶片成本，並可以提高測試晶 片產量及製造速度，同時便於變更測試晶片之設計。 爲達成本發明之上述和其他目的，提出一種基板型 電性測試晶片，係由至少一層圖案化線路層及至少一絕緣 芯層，交替疊合形成，亦即二相鄰圖案化線路層之間必有 一絕緣芯層使之隔離。圖案化線路層間彼此電性連接，而 圖案化線路層其中之一位於基板型電性測試晶片表面，且 具有多個接點，每一接點適於分別與欲測試承載器之線路 電性連接。基板型電性測試晶片與承載器經過封裝後，可 進行高頻電性測試。 依照本發明的一較佳實施例，其中絕緣芯層之材質 包括玻璃環氧基樹脂、雙順丁烯二酸醯亞胺及環氧樹脂 4 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 442840 6027t\vf,doc/008 五、發明說明（务） 等，因此可以大幅降低測試晶片之製造成本。而圖案化 線路層係將一銅箱經過定義而形成’因此十分便於變更 測試晶片的線路設計。由於本發明之測試晶片係採用基 板的形式，所以利於量產’且具有較快之生產速度。 爲讓本發明之上述和其他目的、特徵、和優點能更 明顯易懂，下文特舉一較佳實施例’並配合所附圖式’作 詳細說明如下： 圖式之簡單說明： 第1圖及第2圖分別繪示依照本發明一較佳實施例 的一種基板型電性測試晶片，應用於承載器電性測試的俯 視圖。 第3圖則繪示本發明基板型電性測試晶片，應用於 承載器電性測試的剖面圖。 第4圖繪示本發明另一較佳實施例，一種基板型 電性測試晶片剖面結構圖。 第5圖及第6圖繪示利用本發明基板型電性測試 晶片進行承載器電性測試的結果。 圖式之標示說明： 100、200、300 :基板型電性測試晶片 102、204 :絕緣基板 104 :圖案化線路層 106、118、124 :導電跡線 108、202 :接點 110、114、116、120、122、126、128 :承載器線 5 本纸張尺度適用令國國家標準（CNSM4蜆格（210 X 297公釐） ------Γ!--- -裝 -------訂--I--I---^ (請先閱讀背面之注鲁？事項再填寫本頁) 經濟部智慧財產局員工消f合作社印製 442840 A7 6027twf.doc/0 08 37 五、發明說明（α ) 路 112、216 :導線 210 :承載器（BGA基板） 212 :晶片座 214、306 :黏著材料 21 8 ·金手指 220 :封裝材料 222、304 :圖案化線路層 224、302 :絕緣芯層 226 ' 308 :貫孔 228 :銲球墊 400、402、500、502 :電性特性曲線 404 :諧振點 504 :時域區域 實施例 欲對高頻承載器做進一步電性檢測，較佳是將一測 試晶片貼附於承載器、經打導線、封裝後，將承載器上的 線路形成一訊號回路，再模擬高頻操作，以取得承載器的 頻率響應及高頻電性特性。習知的測試晶片皆是以矽（Si) 或砷化鎵(GaAs)爲基底，透過半導體製程而形成測試電路 於基底上。然而此種測試晶片製造價格昂貴，而且耗時； 若要更新測試電路還需修改光罩等，十分消耗成本及工 時。 本發明提出一種非矽或砷化鎵爲基底的電性測試晶 6 ------r-----' ------訂—*------|綠 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） 442840 6027twf.doc/008 五、發明說明（f) 片。請同時參照第1、2、3圖，其中第1圖及第2圖分別 繪示依照本發明一較佳實施例的一種基板型電性測試晶 片，應用於承載器電性測試的俯視圖，而第3圖則繪示本 發明基板型電性測試晶片，應用於承載器電性測試的剖面 圖。 請先參照第1圖，本發明中基板型電性測試晶片100 是建構於一絕緣基板102上，絕緣基板102之材質包括玻 璃環氧基樹脂（FR-4 ' FR-5)、雙順丁烯二酸醯亞胺 (Bismaleimide-Triazine，BT)或者環氧樹脂（ep0Xy)等。而 經濟部智慧財產局具工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 絕緣基板1 〇2表面具有一圖案化線路層1 〇4，包括一些 導電跡線l〇6(conductive trace)及一些接點1〇8(包括導電 跡線106之末端亦形成接點）。圖案化線路層1〇4之形成 可以藉由絕緣基板102表面配置一銅箔層，然後經過定 義（微影蝕刻）而形成。導電跡線106與接點1〇8均會與 承載器的線路110電性連接，以形成訊號回路，以利後 續電性測試。其中，承載器可以是各種型態，比如導線 架 '硬式基板 '軟式基板，晶圓級構裝承載器，陶瓷基板 承載器等，所以對應的線路110可以是導線架中的導線， 硬式基板或軟式基板的跡線(trace)等。而導電跡線106可 以模擬實際晶片中的線路，而接點108模擬晶片中的焊墊 (bonding pad)。導電跡線106的末端與接點1〇8比如可以 利用打導線(wire bonding)的方式，分別透過導線Π2與承 載器的線路Π0連接，其中導線112材質包括金線、鋁線 等。當然亦可以透過其他方式形成導電跡線106與接點1〇8 7 本纸張又度適用中國國家標準（CNS)A4規格（210 X 297公釐） 442840 6()2 7tvvf.doc/0 0 8 經濟部智慧財產局員工消費合作社印製 五、發明說明（6 ) 和承載器的線路U0之間的電性連接，比如軟片自動接 合（tape automatic bonding, TAB)的方式，或覆晶（flip chip) 的方式，主要根據欲檢測之承載器未來的封裝方式決定。 以第1圖爲例，線路114、116透過與導電跡線106 的連接，可以與外部測試電路（未繪示）形成一回路，透 過輸入測試訊號，可進行頻率響應測試。以第2圖爲例， 同樣地，位於對角的線路120、122可以透過導電跡線 118，形成回路，而量測承載器中較遠離的線路間之頻率 響應。然而透過導電跡線124的連接，可以量測承載器 中相鄰二線路126、128的頻率響應。 請參照第3圖，爲了模擬實際構裝中線路的電性 表現，測試時亦會盡量模擬實際構裝結構。以硬式基板 承載器爲例，比如是球格陣列式構裝基板（BGA substrate)，基板型電性測試晶片200的絕緣基板204會 透過一黏著材料214固定於承載器210的晶片座212上。 而基板型電性測試晶片200上的接點202，經過打導線 製程’藉由導線216與承載器210線路末端的金手指 2 18(gold finger)電性連接，形成回路。然後透過封裝製 程（encapsulating process)，比如以灌模（molding)的方式， 用封裝材料220包覆基板型電性測試晶片200及接點2〇2 與金手指218連接的部分。其中封裝材料220比如是環 氧樹脂（epoxy)。以BGA基板210而言，其是由積層板 (laminate board)所構成，其包括多層圖案化線路層222 及絕緣芯層224交替疊合而成，而絕緣芯層224中還有 8 本紙張尺度適用中國國家標準（CNS)AO見格（210x 297公釐〉 <請先閱讀背面之注意事項再填寫本頁) 裝·--- 訂------- 綍 442840 6027twf.doc/0 08 A7 137 經濟部智慧財產局員工消費合作社印製 五、發明說明w ) 連接圖案化線路層222間的貫孔226(via)。BGA基板210 中的線路即是由圖案化線路層222及貫孔226所組成， 線路一端爲金手指218，另一端則爲銲球墊228(ball pad)。此時即可透過銲球墊228輸入測試訊號，量測BGA 基板210的頻率響應。 基板型電性測試晶片除了上述單層圖案化線路層 的結構外，亦可以形成如積層板的結構。請參照第4圖， 其繪示本發明另一較佳實施例，一種基板型電性測試晶 片剖面結構圖。基板型電性測試晶片300可以形成積層 板的形式，由多層圖案化線路層304及絕緣芯層302， 彼此交替疊合形成，亦即二相鄰圖案化線路層304間均 配置有一絕緣芯層302,且藉由貫孔308使圖案化線路 層304間形成電性連接。藉此結構，可以將各種測試線 路整合於同一基板型電性測試晶片300中，比如可以將 第1圖與第2圖中所示的圖案化測試線路整合。其中圖 案化線路層304的形成，可以銅箔藉由微影蝕刻的方式 製成；絕緣芯層3〇2之材質包括玻璃環氧基樹脂 '雙順 丁烯二酸醯亞胺或者環氧樹脂等。而圖案化線路層304 與絕緣芯層302間的疊合可以藉由壓合方式，以黏著材 料306加以黏合，當然亦可以積層方式形成。而貫孔308 係經由鑽孔，及塞孔製程形成。無論單層或多層的基板 型電性測試晶片，由於其製程較容易，所以便於變更線 路設計，可以因應各種承載器的電性測試。 當基板型測試晶片與承載器進行封裝後，所進行 9 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) —------訂·------I I 结』_442840 6027twf.doc / 008 AT B7-Description of invention printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Five Ministry of Economic Affairs (丨) The present invention relates to a high-frequency carrier test chip ', and more particularly to a high-frequency carrier test chip. The substrate-type electrical test wafer of the device ° Semiconductor integrated circuit wafers usually do not exist alone, but love to interact with other chip circuits through the input-output system. Semiconductor wafers and internal circuits are very complex and require a package to protect and carry. Therefore, the main functions of electronic assembly include: (1) providing a current path to drive the circuits on the wafer; (2) distributing the signals of the wafer in and out (3) Dissipate the thermal energy generated by the circuit to the outside world: (4) Protect the chip in a destructive environment. Due to the increasing accumulation of semiconductor components, the multi-functional, high-capacity, high-processing speeds have increased in proportion to the relatively small products. In contrast, the development of packaging technology has also moved towards high-density, high-pin, high-frequency, and high-performance semiconductor structures. Equipment development. Today, the types of carriers that provide semiconductor component structure are even more diverse, including lead frame type carriers (Ieadframe), rigid substrate type carriers (riglcj substrate), flexible substrate type carriers (flex substrate), wafer-level packaging A carrier (wafer level package), a ceramic substrate carrier (a substrate, etc.) can form a variety of structures. Due to the increasing processing speed requirements of integrated circuit components, the processing speed of the central processing unit (CPU) has entered the era of gigahertz (GHz) for personal computers, and there are many high-frequency semiconductor components for communication products. Therefore, the electrical performance requirements for constructing the carrier will be relatively high, especially the efficiency at high frequency operation, which is the focus of the carrier's product. -、 Purchase traditionally test the electrical properties of the carrier, whether it is a lead frame or a soft substrate type, etc., all are tested by a short-circuit test. The paper standard applies to the Chinese national standard (CNS > A4 specification ( 21〇X 297) (Please read the precautions on the back before filling out this page)-Install --------- 1 Order --------- 442840 A7 Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs Consumer Consumption Cooperative 6027twf.doc Fan 8 B7 V. Description of the invention (7 /) and an open test (open) to extract the electrical parameters of the carrier itself, such as the resistance (R) and inductance (L) of the signal path provided by the carrier , Capacitor 値 (C). However, such tests cannot guarantee its performance and yield for future high-frequency operation. For example, with the above test methods, it is not possible to know the signal path of the carrier during high-frequency operation. Interference phenomenon, signal loss, signal attenuation, etc. Therefore, at present, it is usually necessary to further test high-frequency carriers. After simulating the chip after die attaching, wire bonding, and encapsulating, The whole circuit is at high frequency Therefore, one of the objects of the present invention is to provide a substrate-type electrical test wafer and a carrier for high-frequency inspection. Another object of the present invention is to provide a test wafer other than silicon or gallium arsenide It can greatly reduce the cost of test wafers, increase the yield and manufacturing speed of test wafers, and facilitate the change of the design of test wafers. In order to achieve the above and other purposes of the invention, a substrate-type electrical test wafer is proposed, which is composed of at least one layer The patterned circuit layer and at least one insulating core layer are alternately stacked to form, that is, there must be an insulating core layer between two adjacent patterned circuit layers to isolate them. The patterned circuit layers are electrically connected to each other, and the patterned circuit layer is in which One is located on the surface of the substrate-type electrical test wafer and has multiple contacts, each of which is suitable for being electrically connected to the circuit of the carrier to be tested. After the substrate-type electrical test wafer and the carrier are packaged, Conduct high-frequency electrical test. According to a preferred embodiment of the present invention, the material of the insulating core layer includes a glass epoxy-based tree 2, bismaleic acid, imine and epoxy resin 4 (Please read the precautions on the back before filling out this page) This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) Wisdom of the Ministry of Economic Affairs Printed by the Consumer Affairs Cooperative of the Property Bureau 442840 6027t \ vf, doc / 008 V. Invention description (service), etc., which can significantly reduce the manufacturing cost of test wafers. The patterned circuit layer is formed by defining a copper box through the definition of 'So It is very convenient to change the circuit design of the test wafer. Since the test wafer of the present invention is in the form of a substrate, it is conducive to mass production and has a faster production speed. In order to make the above and other objects, features, and advantages of the present invention more Obviously easy to understand, the following is a detailed description of a preferred embodiment 'in conjunction with the accompanying drawings' as follows: A brief description of the drawings: Figure 1 and Figure 2 respectively show a preferred embodiment according to the present invention A top view of a substrate-type electrical test wafer applied to the electrical test of a carrier. Fig. 3 is a cross-sectional view showing the substrate-type electrical test wafer of the present invention applied to the electrical test of a carrier. FIG. 4 is a cross-sectional structure diagram of a substrate-type electrical test wafer according to another preferred embodiment of the present invention. Figures 5 and 6 show the results of the electrical test of the carrier using the substrate-type electrical test wafer of the present invention. Description of the drawing labels: 100, 200, 300: substrate-type electrical test wafers 102, 204: insulating substrates 104: patterned circuit layers 106, 118, 124: conductive traces 108, 202: contacts 110, 114, 116 , 120, 122, 126, 128: Carrier line 5 The paper size is applicable to the national standard of the country (CNSM4 grid (210 X 297 mm) ------ Γ! ----installed ---- --- Order--I--I --- ^ (Please read the note on the back? Matters before filling out this page) Printed by the staff of the Intellectual Property Bureau of the Ministry of Economic Affairs Cooperative 442840 A7 6027twf.doc / 0 08 37 5 Explanation of the invention (α) Roads 112 and 216: Conductor 210: Carrier (BGA substrate) 212: Wafer holder 214, 306: Adhesive material 21 8Gold finger 220: Packaging material 222, 304: Patterned circuit layers 224, 302 : Insulating core layer 226 '308: Through-hole 228: Solder ball pad 400, 402, 500, 502: Electrical characteristic curve 404: Resonance point 504: Time domain region Example For further electrical detection of high-frequency carriers, Preferably, a test chip is attached to the carrier, and after wiring and packaging, the circuit on the carrier is formed into a signal loop, and then a high-frequency operation is simulated to obtain The frequency response and high-frequency electrical characteristics of the carrier. Conventional test chips are based on silicon (Si) or gallium arsenide (GaAs), and test circuits are formed on the substrate through semiconductor processes. However, such test chips It is expensive and time-consuming to manufacture; it is necessary to modify the photomask to update the test circuit, which costs a lot of time and labor. The present invention proposes a non-silicon or gallium arsenide-based electrical test crystal 6 ----- -r ----- '------ Order — * ------ | Green (Please read the notes on the back before filling this page) This paper size applies to China National Standard (CNS) A4 (210 x 297 mm) 442840 6027twf.doc / 008 V. Description of the invention (f). Please refer to Figures 1, 2, and 3 at the same time. Among them, Figures 1 and 2 respectively show a preferred method according to the present invention. A substrate-type electrical test wafer of the embodiment is a top view applied to the electrical test of the carrier, and FIG. 3 shows a cross-sectional view of the substrate-type electrical test wafer of the present invention applied to the electrical test of the carrier. Referring to FIG. 1, a substrate-type electrical test wafer 100 in the present invention is constructed on an insulating substrate 102. The edge of the substrate material 102 comprises a glass epoxy resin (FR-4 'FR-5), maleic acid bis (PEI) (Bismaleimide-Triazine, BT) or epoxy (ep0Xy) and the like. Printed by the Consumer Goods Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page) The surface of the insulating substrate 10 has a patterned circuit layer 104, including some conductive traces 106 ( conductive trace) and some contacts 108 (including the ends of the conductive trace 106 also forming contacts). The patterned circuit layer 104 can be formed by disposing a copper foil layer on the surface of the insulating substrate 102 and then defining (lithographic etching). Both the conductive trace 106 and the contact 108 are electrically connected to the carrier's line 110 to form a signal loop for subsequent electrical testing. Among them, the carrier can be various types, such as a lead frame 'hard substrate' soft substrate, a wafer-level structured carrier, a ceramic substrate carrier, etc., so the corresponding line 110 can be a lead in a lead frame, a rigid substrate or Traces and the like of flexible substrates. The conductive trace 106 can simulate a circuit in an actual wafer, and the contact 108 simulates a bonding pad in the wafer. For example, the ends of the conductive traces 106 and the contacts 108 can be connected to the carrier lines Π0 through the wires Π2 by wire bonding. The materials of the wires 112 include gold wires and aluminum wires. Of course, it is also possible to form the conductive traces 106 and contacts 108 by other methods. This paper is again applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 442840 6 () 2 7tvvf.doc / 0 0 8 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (6) The electrical connection between the carrier and the line U0 of the carrier, such as tape automatic bonding (TAB), or flip chip. chip) is mainly determined by the future packaging method of the carrier to be tested. Taking the first figure as an example, the lines 114 and 116 can form a loop with an external test circuit (not shown) through the connection with the conductive trace 106. By inputting the test signal, a frequency response test can be performed. Taking the second figure as an example, similarly, the lines 120 and 122 located at the diagonal can pass through the conductive trace 118 to form a loop, and measure the frequency response between the farther lines in the carrier. However, through the connection of the conductive trace 124, the frequency response of two adjacent lines 126, 128 in the carrier can be measured. Please refer to Figure 3, in order to simulate the electrical performance of the line during actual construction, the actual construction structure will be simulated as much as possible during the test. Taking a rigid substrate carrier as an example, for example, a ball grid array type substrate (BGA substrate), the insulating substrate 204 of the substrate-type electrical test wafer 200 is fixed on the wafer base 212 of the carrier 210 through an adhesive material 214. The contact 202 on the substrate-type electrical test wafer 200 is electrically connected to a gold finger 2 18 at the end of the carrier 210 line through a wire-forming process to form a loop. Then, through an encapsulating process, for example, in a molding manner, the substrate-type electrical test chip 200 and the portion of the contact 202 connected with the gold finger 218 are covered with the encapsulating material 220. The encapsulating material 220 is, for example, epoxy. As for the BGA substrate 210, it is composed of a laminate board, which includes a plurality of layered patterned circuit layers 222 and an insulating core layer 224 alternately laminated, and there are 8 paper sizes in the insulating core layer 224 Applicable to Chinese National Standard (CNS) AO (210x 297 mm) < Please read the precautions on the back before filling out this page) Installation · --- Order --------- 442840 6027twf.doc / 0 08 A7 137 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention w) Connect the through holes 226 (via) between the patterned circuit layers 222. The circuit in the BGA substrate 210 is composed of a patterned circuit layer 222 and a through hole 226. One end of the circuit is a gold finger 218 and the other end is a ball pad 228. At this time, the test signal can be input through the solder ball pad 228 to measure the frequency response of the BGA substrate 210. In addition to the structure of the single-layer patterned circuit layer described above, the substrate-type electrical test wafer may also have a structure such as a laminated board. Please refer to FIG. 4, which illustrates a cross-sectional structure diagram of a substrate-type electrical test wafer according to another preferred embodiment of the present invention. The substrate-type electrical test wafer 300 may be in the form of a laminated board, which is composed of a plurality of patterned circuit layers 304 and an insulating core layer 302 alternately stacked on each other, that is, an insulating core layer is arranged between two adjacent patterned circuit layers 304. 302, and electrically connect the patterned circuit layers 304 through the through holes 308. With this structure, various test lines can be integrated into the same substrate-type electrical test chip 300, and for example, the patterned test lines shown in FIG. 1 and FIG. 2 can be integrated. The formation of the patterned circuit layer 304 can be made of copper foil by lithographic etching. The material of the insulating core layer 302 includes glass epoxy resin 'bis maleic acid sulfonium imine or epoxy resin. Wait. The overlap between the patterned circuit layer 304 and the insulating core layer 302 can be bonded by an adhesive material 306 by a lamination method, or it can be formed by a lamination method. The through hole 308 is formed by drilling and plugging process. Whether it is a single-layer or multi-layer substrate-type electrical test wafer, because its manufacturing process is relatively easy, it is easy to change the circuit design, and it can respond to the electrical test of various carriers. After the substrate-type test wafer and the carrier are packaged, the 9 paper sizes are applied to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page) --- ---- Order · -------- II Result 』_
修正日期90/4/26 4^28 4)2〇wf l.doc/002 第89107551號說明書修正頁 π 補无 五、發明說明（k)-- 的頻率響應測試項目，目前並無一定的標準規範，然而 測試是絕對必要的，因爲一般界定當承載器線路長度左 於十分之一訊號波長，即屬於高頻的構裝，此時許多高 頻的干擾及損失現象都會發生在構裝中。請參照第5圖 及第6圖，其繪示利用本發明基板型電性測試晶片進行 承載器電性測試的結果。請先參照第5圖，其中曲線400 表示基板型電性測試晶片在未封裝前線路的頻域穿透係 數；曲線402則表示基板型電性測試晶片經過封裝後， 所測得的頻域穿透係數。由圖中即可獲得承載器的頻域 特性曲線，且其諧振點約在於訊號頻率爲1.5GHz的頻 域。請參照第6圖，其中曲線500表示基板型電性測試 晶片經過封裝後，所測得時域反射係數曲線：曲線502 表示基板型電性測試晶片經過封裝後，所測得時域穿透 係數曲線。由圖可獲得承載器的時域特性曲線，並可知 在區域504承載器的上升時間（rising time)增加了 960ps。 此外，對於高頻承載器的高頻響應測試項目包括：穿透 損失（insertion loss)、反射損失（return loss)、隔離 (isolation)、親合（coupling)、傳遞延遲（propagation delay)、訊號衰減（signal degradation)、構裝中的電感/電 容電性參數（包括導線效應wire effect)等。 綜上所述，本發明由於提出一種基板型電性測試 晶片，取代以矽或砷化鎵爲基底的測試晶片’不但可以 大幅降低測試晶片的製造成本及工時，成爲承載器高頻. 電性測試的有利工具。同時由於基板型電性測試晶片的 <請先Μ讀背*之注意事項再填寫本頁) 經濟部智慧財產局負工消费合作社印製 訂---------線— ________________________ 本紙張尺度適用中國國家標準（CNS)A4規格（210x297公釐〉 442840 6027tvvf.doc/008 A7 B7 五、發明說明（q ) 製程較容易，利於測試晶片之量產，並利於變更晶片大 小，測試線路設計，可以提供更便利、更廣泛的承載器 電性測試應用。 雖然本發明已以一較佳實施例揭露如上，然其並非 用以限定本發明，任何熟習此技藝者，在不脫離本發明之 精神和範圍內，當可作些許之更動與潤飾，因此本發明之 保護範圍當視後附之申請專利範圍所界定者爲準。 (請先閱讀背面之注意事項再填寫本頁) • · I 丨丨丨！ —訂- -------"^_ 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國因家標準（CNS)A.·!規格（210 X 297公釐）Date of amendment 90/4/26 4 ^ 28 4) 2〇wf l.doc / 002 No. 89107551 Revised page π Supplement No. 5. Description of the invention (k)-Frequency response test items, there is currently no certain standard Standard, however, testing is absolutely necessary, because generally defined when the length of the carrier line is less than one tenth of the signal wavelength, which is a high-frequency structure, at this time many high-frequency interference and loss will occur in the structure . Please refer to FIG. 5 and FIG. 6, which show the results of the electrical test of the carrier using the substrate-type electrical test wafer of the present invention. Please refer to FIG. 5 first, where the curve 400 represents the frequency-domain penetration coefficient of the circuit of the substrate-type electrical test chip before being packaged; the curve 402 represents the measured frequency-region penetration of the substrate-type electrical test chip after packaging. Transmission coefficient. The frequency domain characteristic curve of the carrier can be obtained from the figure, and its resonance point lies in the frequency domain of the signal frequency of 1.5GHz. Please refer to Figure 6, where curve 500 represents the measured time-domain reflection coefficient curve after the substrate-type electrical test wafer is packaged: curve 502 represents the measured time-domain transmission coefficient after the substrate-type electrical test wafer is packaged curve. The time-domain characteristic curve of the carrier can be obtained from the figure, and it can be known that the rising time of the carrier in the region 504 is increased by 960ps. In addition, high-frequency response test items for high-frequency carriers include: insertion loss, return loss, isolation, coupling, propagation delay, signal attenuation (Signal degradation), electrical parameters of the inductor / capacitor in the structure (including wire effect), etc. In summary, the present invention, as proposed by a substrate-type electrical test chip, replaces the test wafer based on silicon or gallium arsenide 'not only can greatly reduce the manufacturing cost and man-hours of the test wafer, becoming a carrier high frequency. Electric A useful tool for sexual testing. At the same time, as the substrate type electrical test chip < Please read the precautions before reading this page before filling out this page) Printed by the Consumers ’Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs --------- line — ________________________ This paper Standards are applicable to China National Standard (CNS) A4 specifications (210x297 mm) 442840 6027tvvf.doc / 008 A7 B7 V. Description of the invention (q) The process is easier, which is conducive to the mass production of test wafers, and it is beneficial to change the size of the wafers and test circuit design Can provide a more convenient and extensive carrier electrical test application. Although the present invention has been disclosed above with a preferred embodiment, it is not intended to limit the present invention. Anyone skilled in this art will not depart from the present invention. Within the spirit and scope, some changes and retouching can be made, so the protection scope of the present invention shall be determined by the scope of the attached patent application. (Please read the precautions on the back before filling out this page) • · I丨 丨 丨! —Order- ------- " ^ _ Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, this paper is printed in accordance with China National Standards (CNS) A. ·! Specifications (210 X 297 mm) )