TW441060B - Multi-chip module - Google Patents

Abstract

A multi-chip module having better thermal performance, mainly comprises two substrates to load at least two chips, a lead frame and a molding body wrapping the substrate, chip and lead frame, wherein the back side of each chip is exposed out of the molding body to increase the thermal performance of the module. These two substrates are disposed on the upper and lower surfaces of the lead frame respectively. The chips are connected as flip-chip and are fixed to these two substrates. The lead frame comprises a plurality of conductive wires with the inner lead part, middle part and external lead part. The middle parts of plural conductive wires are electrically connected to two substrates with a plurality of bonding wires. The external lead parts of plural conductive wires extend externally from the molding body to electrically communicate with the outside world.

Description

4 410 6 0 Case No. 89〗 00fi 叩 月 月 Amendment V. Description of the Invention (2) The semiconductor device is mounted on a wafer 10 with a plurality of wafer pads 12 located in the central area of the upper surface of the upper wafer 10, An inner leg 21 of the upper lead frame 20 extends on the upper surface of the upper chip 10 and is fixed by adhesive tape 30. The inner leg 21 is electrically connected to the corresponding chip pad 12 by the wire 40 and the lower chip 50 has a plurality of wafer bonding pads 52 located in the central area of the upper surface of the lower wafer 50. The inner leg 61 of the lower lead frame 60 extends on the upper surface of the lower wafer 50 and is fixed and fixed by an adhesive tape 70. The inner leg 61 is guided by a wire. 80 is electrically connected to the corresponding wafer bonding pad 52, and the feet 62 of the lower lead frame 60 extend to the outside of the sealant and can be electrically connected to the external circuit. The inner leg 22 at the outer end of the upper lead frame 20 is in direct contact with the top surface of the inner leg 61 of the lower lead frame 60, so that the upper chip 1Q and the upper lead frame 2 () are electrically connected to the lower chip 50 and the lower lead frame 60. connection. —Insulation adhesive 10 and the inner leg 61 of the lower lead frame 60 Q i π are compared with US Patent No. 5,332,922, although the lack of US No. 5, 8. 4, 874 has greatly reduced the packaging of semiconductor devices: thick Π wire frame No need to bend multiple times to simplify sealing

(wire b_) 的 方 ’but because of its ties

p99-〇l5.ptc cannot effectively reduce package two and: the wire frame, so its stack No. 5,8,04,874 // seal /; In addition, the United States Patent No. It still requires at least two lead frames to use two lead frames, so there will be a problem of frequency noise due to the connection = encapsulated body, at least because of the common lack of the aforementioned packaging devices. The encapsulant surrounds' so the wafer behaves normally—because the wafer is completely out of the encapsulant. Since the heat generated by the sealant :: must be completely blocked by the heat dissipation of the wafer, the insulation characteristics make the semiconductor semiconductor chip in the cracked structure produce some ancient conditions, which will be in the habit. Touch ira delete-a 'may damage or damage the crystal

Another object of the present invention is to provide a multi-chip package structure, a lead frame, and more than two chips are packaged in a package, 44 彳 06〇 __ Case No. 89100693__ year and month g 5. Description of the invention (3) pieces. [Summary of the invention] The main purpose of the present invention is to provide a better loose package structure, which includes at least two wafers wrapped in-Fengsheng: sheep: ;;;; the back of a wafer is exposed to the sealing gel, borrow This improves the thermal performance of the package structure. A secondary object of the present invention is to provide a multi-chip package structure with better heat dissipation efficiency, which utilizes flip-chip technology to increase the packaging efficiency of the package structure. It only needs to be used to improve the comparative performance according to the present invention. A multi-chip package structure with good heat dissipation efficiency. Straight main Π = carrying at least two crystals [-lead frame is used to connect the crystal f to: the circle and a gel coat the substrate, and the wafer person: 'where The back is exposed on the sealant. ^, Don't fix it on the upper surface of the lead frame

= Don't electrically connect and fix the two substrates IT d. The pads on the wafer surface ⑷ " ⑷-shaped (so 1 der bump) are used for the spleen | Old & The lead frame contains the middle part A of the plurality of conductors of the plurality of lead-based lead frames. A: bonding wires ^ ru * ,; ki The bottom part of the outer conductor of the lead is from the sealing compound ^ on the two substrates of the 5 '. Plural strips.-The sealant covers the base: win = epitaxy: it is used to communicate with external electrical channels and lead frames.

'Cable number ___89100693____year month day_revision___ V. Description of the invention (4) A multi-chip package structure with better heat dissipation efficiency according to the present invention, since the back of each chip is exposed to the sealing gel, so The heat generated by the normal operation of each chip can be directly dissipated through its back surface, thereby increasing the heat dissipation efficiency of the package structure. In addition, in the first-level packaging order, the flip chip (f 1 ip chip) has a packaging efficiency of about 90% (calculated on a 10M square chip), and the wire bonding (wi rending) and coil τ automatic tickling ( Tape Automated Bonding (TAB) packaging efficiency (calculated on the same chip size) is only about 75% and 50%, respectively. Therefore, according to the present invention, the multi-wafer sealed structure with better heat dissipation efficiency is used because the wafer is mounted on the substrate by a flip-chip method, so its packaging efficiency can be greatly increased. In addition, according to the multi-chip package structure with better heat dissipation rate of the present invention, since it only requires a lead frame, there will be no high-frequency noise problem due to the increase in connection points, thereby improving the electricity of the package. Sexual effectiveness. In order to make the above and other objects, features, and advantages of the present invention more obvious, the following describes the preferred embodiments of the present invention in detail with reference to the accompanying drawings #g. [Explanation of the invention] The third figure is a multi-chip package structure 100 'according to one of the first preferred embodiments of the present invention, which mainly includes two substrates 110, 120, a pair of crystals 130, 140, a lead frame 150, and A piece of colloid 170. The two substrates 110 and 120 are respectively provided with a plurality of substrate pads 11 2 and 1 2 2. The front surfaces of the pair of wafers 130, 140 are respectively provided with a plurality of solder ball protrusions (not shown in the figure), and the back surfaces of the pair of wafers 130, 140 are exposed to the sealing compound 17. . The plurality of solder ball protrusions of the pair of wafers 1 3 0 and 1 4 0 are used to fix them to the substrate, respectively.

P99-015.ptc Page 7 4 41 0 6 0 Case No. 89100693 Rev. V. Description of the invention (5) 1 1 0, 1 2 0 and form an electrical connection. The lead frame 501 includes a plurality of lead wires 1 5 2 having an inner leg portion 15 2 a, a middle portion 15 2 b, and an outer leg portion 1 5 2 c. The substrate 1 is fixed to the lower surface of the inner leg portion 5 2 a with an adhesive layer 5 4, and the substrate 120 is fixed to the lower surface of the inner leg portion 1 52 a with an adhesive layer 155. The middle portion 1 52b of each of the wires 1 52 is connected to the corresponding substrate pad 2 and the substrate pads 1 2 2 by connecting wires such as gold wires 1 58, respectively. The sealing body 170 covers the two substrates 1 120, the wafers 130, 140 ', the lead frame 1 50, and a plurality of gold wires 1 5 8. Among them, the lead frame 1 50 is plural. The outer leg portions 1 5 2 c of the wires 1 5 2 extend outwardly from the sealing body 170 to be used for electrical communication with the outside world. Please refer to the third figure again. The substrate 11 〇, 120 is generally made of non-conductive material [for example, FR-4 glass epoxy (guss-e ρ ο X y) or polyimide]. to make. The lead frame 150 is preferably made of copper, iron, nickel or an alloy thereof. In addition, the plurality of wires 152 may be plated with a highly conductive material such as silver, copper, gold or palladium. The material of the sealing gel 1 70 is an insulating material. The preferred plastic compound is CEL-920 0XU plastic provided by Hitachi Chemical Company. Please refer to the third figure again. When the multi-chip package structure 100 is subjected to the sealing process, its thickness tolerance must be set to be small to prevent the chip 130 and 140 from being squeezed by the upper and lower molds. This results in a die crack. Therefore, the adhesive layer 1 54 and 1 5 5 are preferably made of an elastic material such as silicone rubber (si 丨 iC0ne rubber). The elastic material can be applied in a liquid form first, and then cured to form an elasticity. Floor. With this ’the adhesive layer 1 5 4 and 1 5 5 can increase the thickness tolerance between the substrate 1 10 and 120 to reduce the thickness of the package and the cavity (mold).

P99-015.ptc Page 8 〇 6 〇 Case No. 89100693_ year month day __ amendment_ 5. Description of the invention (6) Cavity ty) Stress generated by inconsistency β Therefore, the elastic layer can increase the package body 100 The allowable thickness reduces production costs. The plurality of solder ball protrusions of the wafer 130, 140 can be formed using the conventional ◦ 4 (Controlled Collapse Chip Connection) process. (A) A solder ball protrusion is formed on the die pad of the wafer. Metallurgical (under bump metailurgy (ϋΒΜ) ° (B) forms bump bumps on UBM. The substrates 1 10, 1 20 are provided with a plurality of solder balls (not shown) in the mounting area of the pair of wafers 130, 140, and are respectively electrically connected to corresponding ones. Substrate pads 1 1 2, 1 2 2. The plurality of solder ball protrusions of the wafers 130 and 140 are respectively aligned with the solder ball pads on the substrates 1 1 0,; 2 0, and then a reflow process such as infrared radiation reflow ( IR ref 1 ow). Therefore, the plurality of solder ball protrusions of the wafers 130 and 140 not only fix them to the substrates 110 and 120, respectively, but also provide a conductive and thermally conductive pathway. An underfill (u n d e r f Π 1) is preferably provided between the wafer and the substrate to seal the gap between the wafer and the substrate. This underfill can reduce the stress on the f solder ball connection (this is due to the inconsistent thermal expansion between the wafer and the substrate). The fourth diagram is a top view of a multi-chip package structure 100 according to one of the first preferred embodiments of the present invention, which includes a pair of wafers 130 and 140. The fifth figure is a top view of a multi-chip package structure 2000 according to one of the second preferred embodiments of the present invention. The multi-chip package structure 200 is the same as the third figure and the fourth except that the two chips 2 300, 2 40, and 2 3 2, 2 4 2 replace the chips 1 300, 1 40. The multi-chip sealing structure in the figure is 100. It can be understood that the substrate used in the multi-chip package structure 2000 includes electrical layouts which must be designed for the chips 2 3 0, 2 4 0, and 2 3 2, 2 4 2 used.

P99-〇15.ptc Page 9 6 6 -f 89100693

'Explanation of the invention (7) The multi-chip package structure according to the present invention is exposed to the encapsulant, so it is two positive every two days: the back of each-chip is connected through its back, which can promote the production of Yiyi ^ The heat can directly improve the heat dissipation effect of the package structure of the present invention; 'It is radiated from the wafer. Because of the chip package structure, since its wafer is a good day, according to the board of the present invention, it can greatly reduce its thickness and increase the basin. ;: The method is based on the multi-chip package structure according to the present invention due to the σ f efficiency. In addition, the lead frame can be avoided due to the increase of the connection points between the lead frames, thereby improving the electrical performance of the package. The gate frequency noise problem, because although the present invention has been disclosed in the aforementioned preferred embodiment, the present invention, anyone skilled in this art, does not depart from the present invention: the limit is within the range, when various changes and modifications can be made . For example, the fine arsenic and wafer packaging structures use one or two pairs of wafers as a multi-phase stacked wafer. Therefore, the scope of protection of the present invention is defined by the scope of mutual benefit. Turn in Bamboo Shoulder

4 41 0 6 0 _ Case No. 89100693 __Che Yue Ri Xiu __ — Brief Description of the Drawings [Illustration] Figure 1: Sectional view of "polycrystalline semiconductor package device" of US Patent No. 5, 332, 922 Figure 2: Sectional view of US Patent No. 5,804, 874 "stacked chip packaging device with a plurality of L0C type semiconductor wafers"; Figure 3: Sectional view of the first preferred embodiment of the present invention Figure 4: Top view of the first preferred embodiment of the present invention; and Figure 5: Top view of the second preferred embodiment of the present invention. [Figure No. 1 4 7 10 21 40 60 61 80 100 11 2 130 152 152c 158 Description] Lower crystal inner pin conductor Upper crystal inner pin conductor Lower inner pin conductor Polycrystalline substrate wafer wire outer pin gold wire piece wire frame piece Sealing pad 2 Upper chip 3 Inner pin 5 Tape 6 Tape 8 Lead wire 9 Resin package 12 Wafer pad 20 Upper lead frame 22 Outer inner leg 30 Tape 50 Lower chip 52 Wafer welding 62 Outer pin 70 Tape 90 Insulating adhesive Layer 110 Substrate 120 Substrate 122 Substrate front 140 Chip 150 Lead frame 152b Middle portion 152a Inner leg portion 154 Adhesive layer 155 Adhesive layer 170 Sealant 180 Adhesive layer

Part II

P99-015.ptc Page 11 4 41 C 6 〇 Case No. 89100693 Month / Date Amendment

P99-015.ptc Page 12 4 41 06 0 ___ £ #, 88123Ϊ56 V. Description of the invention (5) For the above purpose of the invention, the invention provides a kind of electrostatic discharge protection with embedded well area diodes. Circuit. This electrostatic discharge protection circuit with embedded well area diodes includes at least the following units: a well area located on the substrate; most transistors located in the well area, any of the drain systems being located adjacent to the source; adjacent to the well Most embedded wells located on opposite sides of the well area. The depth of any embedded well area is deeper than the depth of the drain and source electrodes. The protection ring is located on the substrate. This protection ring surrounds the well area and passes through the embedment. Type well area; most auxiliary impurity areas i or 'per-auxiliary impurity areas' of bit well areas enter into the well area, and any auxiliary impurity area is separated from the protection ring gate by additional isolation; Wire for light connection = and =: guard ring and source to a relatively low potential. In addition to this, the bottom: the connection A ring has the same conductivity type 'and the conductivity type of the source, drain, and embedded doped region is opposite to that of the substrate. $ 区 和 助 .b-4 Schematic description of the summary to make the above and other objectives, features, and advantages of the present invention easy to understand, order 44 spots 1 hard points can be more detailed as follows: Attached to the mouth Schematic, detailed phase The first picture is a schematic diagram of the relationship between the electrostatic discharge protection circuit and the integrated body pair; other parts of the circuit

2001. 03. 08. 009 Amendment 4 41 〇6 〇_ Case No. 88123156 V. Description of the invention (6) The second diagram A is a schematic cross-sectional diagram of a conventional metal-oxide-semiconductor protection circuit; Top view of the metal-oxide-semiconductor protection circuit structure; FIG. 3A is a cross-sectional view of the metal-oxide-semiconductor protection circuit structure proposed by a preferred embodiment of the present invention, and FIG. A top view of a metal-oxygen semi-electrostatic discharge protection circuit structure according to a preferred embodiment of the invention. Main symbols: 10 output and input terminals 11 ESD protection circuit 12 Internal buffer 13 Die 14 VDD 15 VSS 20 Substrate 21 Isolation 22 Well area 23 Source 24 Drain

Page 10 2001.03. 08.010

Page 11 2001.03. 08.011 06 ο January 1st Revised The schematic cross-section shown and the picture shows the electrostatic discharge 31 between the diodes in the well area along the BB ′ line in the third diagram B. In addition, this book has at least the following units: gate 35, well area 36, protection area 39, first wire 393,. Among them, the drain electrode 33, the source electrode 34, the doped region 39, and the first wire ---- plug number 88123156. Five 'invention description (8) Electrostatic discharge protection circuit. Reference is made to the third plan A as shown by the second β circle, where the third A is a cross-sectional view. It can be clearly seen that the embedded protection circuit is located at the substrate 30 and at the input / output terminal 32, the drain 33, the source 34, the ring 37, and the embedded well area 38 of the electrostatic discharge protection circuit described in the isolation embodiment. The two wires 3 9 6 and the relatively low potential 3 9 9, the gate 35, the embedded well area 38, the auxiliary 3 9 3 and the second wire 3 9 6 are often the majority. First, the well region 36 is located on the substrate 30 and the conductivity type of the well region 36 is the same as the conductivity type of the substrate 30. The conductivity type of the well region 36 may be a positive type (pos ^ ve eiectricity) or a negative type (negaUve eiectricity l ο and The electrode 3 3, the source 3 4 and the gate 3 5 together form a transistor located in the well region 36, and there are usually a plurality of transistor well regions 36. Here, the drain 33 and the source 34 are located in the well. The gate electrode 35 is located inside the region 36 and the gate electrode 35 is located on the surface of the well region 36. In addition, each of the drain electrodes 33 is between two adjacent source electrodes: and :, and the source electrode 34 The conductivity type of the electrode is similar to the conductivity type of the well region 36. The source electrode 34 includes at least a shallow junction surface, and the drain electrode 34 also has at least ^ 3 α surface. The thickness of the shallow junction surface is less than about 1000 angstroms.

Page 12 2001.03, 08.012 4 41 0 6 〇guang ~ pure 881 231 Fifi | Chase after the fifth day, the invention description (9) ^ --- _ u / Li * This embodiment has a pair of embedded wells 38 Here, the embedded well area 38 is adjacent to the well area 36 and on opposite sides of the well area. In addition, the conductivity type of the embedded well region 3 8 is opposite to that of the rubidium region 36, and the depth of any one thousand embedded well region 38 is deeper than the depth of any one of the drain 34 and any of the source 33. ^ The guard ring 37 is located on the substrate 30 and surrounds the well region 36, and the conductivity type of the guard ring 37 is opposite to that of the embedded ridge region 38. In addition, the guard ring 37 passes through the embedded area 38. In this embodiment, there are a pair of auxiliary impurity regions 39, and each of the auxiliary impurity regions 39 is located in an embedded well region 38. Here, each auxiliary doping area 39 and the well area 32 are separated by a guard ring 37, and each auxiliary doping area 39 and the guard ring 37 may be separated by an additional isolation 385. Incidentally, the conductivity type of the auxiliary doped region 39 is the same as that of the embedded well regions 38. Furthermore, the first wire 3 93 is used to couple the drain 33 and the auxiliary impurity region 39 to the output and input terminals, and the second wire 3 9 3 is used to consume the gates 35. 37 and the source 34 are relatively low to the potential a. It is obvious that because the gate 35 is grounded, it is impossible for these metal-oxide semiconductors to be turned on by changing the gate voltage. Further, "the relatively low potential point is located in the bottom 30", and the input / output terminal 32 includes at least a pad. ~ The diode-embedded electrostatic discharge protection

Page 13 Protect 20〇1-〇3.〇8.〇13 4 41 〇6 〇t Case No. 881 ^ 1 1 year 々 \ Amendment 5 Amendments to the invention (10) ^ --1¾] See the reaction mechanism of the circuit It can be summarized as follows: First, the function of these metal-oxide semiconductors in the well area 36 and the function of metal-oxide semiconductors in the conventional metal-oxide semiconductor environmental protection circuit-like 'parasitic dipole connection Transistors and parasitic diodes are formed and used to conduct current. In other words, the advantages and disadvantages of the conventional metal-oxide-semiconductor environmental protection discharge protection circuit will also appear in this part of the embodiment. In any case, 'because the first wire conducts the electric charges appearing at the input / output terminal 32 to each' at the same time, and the pole 33 and the auxiliary impurity region μ, therefore, through the intermediary of the rear-entry well region μ 'in the embedded well region 38 and the substrate There will also be a majority of incidental diodes between 30. The various parasitic and depleted regions have three substrates that are accompanied by large electrical charges; the polar body that is connected to an electrode body is located in the well electric field of the electric field, and the transistor is opposite. The heat generated by the second and the empty area is caused by the incident. Therefore, the electrostatic protection of the thermal storage is destroyed and the heat of the crystal grains in the second electrode is added. Most, therefore, the junction of the thermal circuit is parasitic to the damage carried by the dual carrier. The empty area is still empty. The strength is reduced outside the area 3 and 6. The substrate 30 is fully absorbed so that all the low points have not yet been opened without generating a large electric field. It is located in the well area 3 6 and is located on the substrate 3 0 in. Significant advantages: First, thereby reducing the production and the substrate 30 can be used without damaging the entire parasitic diode, and the charge will still be caused by the integrated circuit.

Page 14 2001, 03, 08.014 4 41 〇6 ο. Case No. 88 丨 2 Magic Anvil

Amendment V. Description of the invention (Π) Therefore, although the embedded well area is 3 g; s: + ^ Coincidentally, the ratio of the ice π anfeikai S is wider than any one of the source 34 or any of the drain 33. However, the size (area) of the well area 36 is still the same as that of the acquaintance Jin A Fenglei a @ = = f surrounded by the Baohuan ring 37. It is recognized that the area of Fengdian's electrostatic discharge protection circuit is in order to benefit the direct government and the electric discharge protection circuit is necessary for the integrated circuit, but the area of the integrated circuit of the electrostatic discharge protection circuit is very good, so the present invention This advantage is quite paid. " Product integration: 5 rf integrated circuit must balance the needs of electrostatic discharge protection and product market demand, so there are 4 people in this article >, with the well area, «彳 further includes a majority of ^ L The core of the core seeker and the pole 33 are located in the-well area. The electrical properties of the f-well area are the same as those of the embedded well area, = the depth is deeper than the depth of the ridge area 36. In other words, the majority of attachments are formed below the drain electrode 33 'such that the electric field is lost. ° Disadvantages of the shortcomings of the city's electrostatic discharge protection circuit 1 = increase ^ 'and poetry catch = 1 ^ 疋' From the previous discussion, it can be seen that the outermost source 34 can be located in the well area μ at the same time, take ν The outermost source 34 of w is directly adjacent to the Baoqi = formula, and the reaction mechanism here is clearly independent of the boundary structure between the well area 36 and the embedded area 38 of the present invention. — Too = The above is only a preferred embodiment of the present invention, and is not intended to limit the equivalent changes made in the spirit or to fall within the scope of the patent disclosed by the present invention. "Modifications shall be included in the following applications: Page 1 2001.03. 08.015

Claims (1)

^ --- One-Case No. 89100693 dated in ___ $ 、 ΐί # Patent scope 1-A multi-chip package structure with better heat dissipation efficiency, which includes: ^ The lead frame has an upper surface and one Surface, the lead frame includes a plurality of wires with inner leg portions, middle portions and outer leg portions; and / or a first substrate provided on the upper surface of the lead frame, the first substrate is provided with a plurality of first substrate pads -A first wafer, the front surface of which is provided with a plurality of first solder ball protrusions for fixing the first wafer to the first substrate and electrically connecting the first wafer to the first substrate;-a second substrate, provided On the lower surface of the lead frame, the second substrate is provided with a plurality of second substrate pads; a second wafer is provided with a plurality of second solder ball protrusions on the front surface for fixing the second wafer to the second substrate; A second substrate and electrically connecting the second chip to the first substrate, and a plurality of connecting wires' for electrically connecting the middle portion of the plurality of wires; Connected to the corresponding first substrate pad and the second substrate pad; and a gel covering the first substrate, the second substrate, the first wafer and the second wafer, a plurality of connecting wires and a lead frame, wherein the wires The outer legs of the plurality of wires of the frame extend outward from the sealing gel for electrical communication with the outside world, and the back of the first chip and the back of the second crystal moon are exposed to the sealing gel. 2. A multi-chip package structure with better heat dissipation efficiency according to item 1 of the scope of the patent application, which further includes a first _Zheng Zhan located between the first base plate and the upper surface of the lead frame and a second The win layer is disposed between the second substrate and the lead frame. P99-〇15.ptc No. 13 _ Case No. 89100693_ Year Month Amendment _ 6. Scope of patent application Between the lower surface. 3. The multi-chip package structure with better heat dissipation efficiency according to item 2 of the scope of patent application, wherein the first adhesive layer and the second adhesive layer are used to increase the thickness tolerance of the package. 4. The multi-chip package structure with better heat dissipation efficiency according to item 2 of the scope of patent application, wherein the first adhesive layer and the second adhesive layer are made of an elastic material. P99-015.ptc Page 14 6 4 1 The scope of the patent is to be reached, the electrostatic discharge protection circuit of the embedded well area diode, the conductance; Ϊ; :: T of a well area, the well area is conductive The type and the majority of the transistors in the well-opening area of the substrate, the majority and the majority of the plurality of transistors: two: on the Haijing area, and the plurality of drains of the plurality of transistors are adjacent to each other and are located in the well Area *, where each of the electrode systems is located in the type ϋ 1 ^ 'hara, and the conductivity systems of the drain and source electrodes are opposite to the conductivity type of the well area; and: 5: f-entry well area 'These embedded well areas are adjacent to the well area and the Ϊ area ::] ϊ Γ, where the conductivity types of these embedded well areas are η Γ opposite to the electrical type' and The depth of any one of the deep car X of the embedded well area is deeper than the depth of any of the drain electrode and any of the source electrode; these: ΗίϊΓ guard ring, the protection ring surrounds the well area and the pass area is opposite; " Here, the conductive type of the guard ring and the embedded well auxiliary spitting are in most of the auxiliary mixed areas of the embedded well areas. The doped region is located in the -mother ° doped region and the protection trout, in the "well"-the auxiliary 搀 (¾ ^ ^ 〇 Chen is separated by an additional isolation, these auxiliary doped ° conductive type system The same as the embedded well areas; 蛊 2 first wires' the first wires are used to couple the drain electrodes to a doped region to an input terminal; and to-: Ϊ f second wires, The second wires are used to couple the relatively low% of the gate poles. Here, the second wires are also coupled to the protection ring and the source of the patent scope on page 17 4 41 〇 06 〇 The potential is relatively low. 2. The protection circuit described in item 1 of the scope of patent application, wherein the conductivity type of the above well area includes at least a positive type. 3. The protection described in item 1 of the scope of patent application Circuit, where the conductivity type of the above well area includes at least a negative charge type. 4. The protection circuit described in item 1 of the scope of patent application, further includes any of the source systems located at the outermost edge of the well area and the embedding at the same time. In the well area 5. Guaranteed as described in item 4 of the scope of patent application Protection circuit, in which the above-mentioned source electrode located at the outermost edge is immediately adjacent to the protection ring. 6. The protection circuit according to item 1 of the scope of patent application, wherein the above-mentioned plurality of auxiliary impurity regions and the well area are protected by the The protection ring is separated. 7. The protection circuit described in item 1 of the scope of the patent application, wherein most of the sources mentioned above include at least a shallow junction surface. 8. The protection circuit described in item 7 of the scope of patent application, The thickness of the shallow joint surface is less than about 100 angstroms. Page 18 6. Scope of patent application 9. The protection circuit according to item 1 of the scope of patent application, wherein the plurality of drain electrodes mentioned above include at least a shallow junction surface. 10. The protection circuit according to item 9 of the scope of patent application, wherein the thickness of the shallow junction surface is less than about 100 angstroms. 11. The protection circuit described in item 1 of the scope of patent application, further comprising placing each of the drain electrodes in an incidental well area. 12. The protection circuit described in item 11 of the scope of patent application, wherein the conductivity type of the above-mentioned well area is the same as that of the embedded well areas 13. The protection circuit described in item 11 of the scope of patent application , The depth of any of the incidental wells is deeper than the depth of the well. 1 4. The protection circuit according to item 1 of the scope of patent application, wherein the relatively low point of the potential above is located in the substrate. 15. The protection circuit according to item 1 of the scope of patent application, wherein the above-mentioned input terminal contains at least fresh water. Page 19