TW439186B - A partially recessed shallow trench isolation method for fabricating borderless contacts - Google Patents

Abstract

An improved and new process for fabricating MOSFET's in shallow trench isolation (STI), with sub-quarter micron ground rules, includes a passivating trench liner of silicon nitride. The silicon nitride passivating liner is utilized in the formation of borderless or ""unframed"" electrical contacts, without reducing the poly to poly spacing. Borderless contacts are formed, wherein contact openings are etched in an interlevel dielectric (ILD) layer over both an active region (P-N junction) and an inactive trench isolation region. During the contact hole opening, a selective etch process is utilized which etches the ILD layer, while the protecting passivating silicon nitride liner remains intact protecting the P-N junction at the edge of trench region. Subsequent processing of conductive tungsten metal plugs are prevented from shorting by the passivating trench liner. This method of forming borderless contacts with a passivating trench liner in a partially recessed trench isolation scheme improves device reliability since it prevents electrically short circuiting of the P-N junction and lowers the overall diode leakage. In addition, the use of this invention's semi-recessed STI process scheme helps to reduce the aspect ratio of the trench, thereby aiding the filling of the trench. Therefore, with the process described herein, STI oxide seam formation is eliminated.

Description

4391 Β β 5. Description of the invention (i) [Background of the invention] (1) Background of the invention The general purpose of the present invention is to provide a new and improved method for forming integrated circuits, which uses and passivates nitrides. Part of the trench liner is a recessed shallow trench isolation (ST I) method to create borderless contact. In sub-micron technology, shallow trench isolation (ST I) has become the standard method for semiconductor device isolation and replaces other isolation methods, that is, the local silicon oxidation (LOCOS) method that requires a larger area. In a conventional shallow trench isolation process, trenches are formed in a semiconductor substrate between electrically active regions (ie, M 0 SF E T gate and source / drain), and the MOSFETs are electrically isolated from each other. The trench is filled with an insulating material such as silicon oxide to provide electrical isolation. The active device and resistor containing the transistor of the MOSFET are manufactured in a semiconductor substrate with a "active" region of shallow trench isolation (ST I) to isolate the area between the active devices. Since the transistor size is sub-micron The traditional contact structure used began to restrict the device performance in many aspects. First, if the contact hole is also the smallest and the problem of cleaning tiny contact holes is taken into consideration, it is difficult to reduce the contact resistivity. In addition, The area of the source / drain region cannot be reduced due to the conventional contacts formed, because the contact holes are aligned with these areas in separate mask steps, and a large extra M area must be used for error. In addition, The larger " extra M area also results in increased source / drain-substrate junction capacitance, which has a negative impact on device speed. Borderless contact or " borderless M contact will address many micro and sub-micron MOSFETs Contact problems, while relaxing the basic design of the device and the traditional "frame" contact processing problems

Page 7 5. Description of the invention (2). This borderless contact makes use of space and area on the source / drain regions, which will be explained in more detail. Borderless contact is part of advanced design and related to shallow trench isolation (S T I) processing. (2) 'Explanation of the know-how' By the traditional shallow trench isolation (ST I) processing, forming a borderless contact with the trench area is a difficult problem. The borderless contact or "borderless M contact" is a contact that is located on the active and isolation regions of a semiconductor device and is exposed. It is generally used to contact the diffusion region formed in the substrate. Forming isolation from traditional shallow trenches The problem of combined borderless contact involves etching the opening of the contact hole through the intermediate dielectric layer while avoiding etching of the dielectric material in the trench. Usually, the intermediate layer and the trench filling material are in the form of silicon oxide. Therefore, the trench The filling oxide can be etched and damaged by the etching of the contact hole. If the trench isolation material is etched back along the trench wall, the damage effect will occur, that is, leakage and short circuit at the edge of the P / N interface, especially When the area is filled with a conductive material. U.S. Patent No. 5,807,784 entitled "Device Isolaton Methods for a Semiconductor Device" approved on September 15, 1998 (Kim et al.) Describes a method for forming a device A method for isolating a layer on a semiconductor device includes a two-step method of forming a field oxide in shallow trench isolation (ST I). The first step includes isolating oxygen Field implant region of the trench bottom in the semiconductor substrate, and oxidation of the oxygen is implanted region to form a field oxide layer, the second step includes depositing an insulating material to further fill the trench.

The title approved on September 8, 1998 was " METHOD OF FILLING

Page 8 43 91 8 6 V. Description of the invention (3) US Patent No. 5, 80 7, 490 (Fiegl et al.) Of SHALLOW TRENCHES 11 describes an isolation method in silicon integrated circuit processing, which fills trenches to fill A marginal overfilling and deposition of a temporary polycrystalline layer with a thickness less than the depth of the trench. An oxide layer is used as a polishing barrier. The temporary layer outside the trench is polished, which uses a filling layer and a polishing barrier as a chemical mechanical polishing (CMP) polishing barrier. The polishing stop layer, the filling layer and the temporary polycrystalline silicon layer of the same thickness are removed by the CMP, and the surface is flattened. The remaining temporary layer is removed and the final polishing of the filling layer ends on the pad nitride. U.S. Patent No. 5,817,568 entitled "Method of Forming a Trench Isolation Region" approved on October 6, 1998 (Chao et al.) Illustrates the use of a complex trench formation technique to form individuals with different widths Method of trench depth. The method includes sequentially forming a buffer oxide layer and a polishing resist layer on a semiconductor substrate. Second, the buffer oxide layer, the polishing resist layer, and the semiconductor substrate are defined to form at least one narrow trench. Second, the buffer oxide layer, the polishing barrier layer, and the semiconductor substrate are defined again to form at least one wide trench. Secondly, a part of the oxide layer and a part of the polishing resist are removed to form a flat surface. Finally, the polishing barrier layer and the buffer oxide layer are removed. U.S. Patent No. 5,6 5 2,176 (Maniar et al.) Entitled " Method for Providing Trench Isolation and Borderless Contact " approved on July 29, 1997 (Maniar et al.) Describes a trench isolation method that uses A trench lining made of nitride. Another similar patent was approved on October 14, 1997 and entitled "Method for Providing

Page 9 4391 86 V. Description of the invention (4)

US Patent No. 5,677,231 to Trench Isolation " (Maniar et al.) Also describes a shallow trench isolation (ST I) and a borderless contact process that has an aluminum nitride pad under the ST I silicon oxide. During the formation of the contact window, the use of a selective etch chemistry for aluminum nitride ' The trench liner will protect the P-N junction at the corner of the trench. By protecting the junction, subsequent formation of conductive plugs will not cause the junction to be electrically shorted and maintain a low diode leakage current. U.S. Patent No. 5,268,330 entitled "Process for Improving Sheet Resistance of a Integrated Circuit Device Gate11" approved on December 7, 1993 (Givens et al.) Describes a process including shallow trench isolation (STI), And the contact on the P-N junction which can be used as a borderless contact. A purification layer is deposited on an integrated circuit device 'which is manufactured using a metal silicide method. An insulating layer is deposited. The insulating layer is planarized and further polished to expose a passivation layer on the interlayer. The portion of the passivation layer on the gate is removed. A trench on the interface is formed by removing the insulating layer and using the passivation layer as a remaining resist. Secondly, a part of the purification layer on the interface was removed. The gate can be further metallized, and windows and trenches on the gate can be filled. The contact on the interface is a borderless contact. The present invention relates to a novel method of using CMP to selectively remove a second material on a first material and form a flat surface of the first material (without the second material remaining). The method of the present invention requires less CMP processing time 'which has a lower cost than the conventional CMP method and forms a polished surface with excellent flatness.

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IIM 4 391 86:

Fifth > Description of the invention (5) Summary of the invention The generality a of the present invention is to provide a new and improved method for forming integrated circuits > which uses a part related to a protective nitride trench observation pad A recessed shallow trench isolation (STI) method to make a non-marginal contact. One of the more specific aspects of the present invention is to provide an improved t-marginal contact formation method during the fabrication of integrated circuits on a semiconductor substrate. The substrate is usually Monocrystalline silicon. The initial process included a pad oxide which was formed by donating a silicon dioxide layer. Secondly, the "hard mask 11 silicon nitride layer was deposited. A reverse mask process k was used for Shallow trench isolation (STI), shallow trench, hard mask nitride layer, and pad oxide are scribed. A shallow trench is etched and then deposited-thick oxide Silicon layer. The thick silicon oxide layer caused a slight tilt in the surface of the trench due to the trench filling process. The surface was flattened by chemical mechanical light (CMP) and a hard mask nitride layer was used to thicken the oxide layer. Polished to a flat surface. The hard mask nitride layer is used as a polishing stopper. In the «th embodiment of the present invention, the above and other @ 's are implemented by using a method of manufacturing a partially recessed shallow trench isolation (STI) structure. > As explained by the following method: 0 After the trench is flattened as described above, 5 a part of the silicon oxide is recovered by a dry etching process or a-wet etching process. The final result of this part of the reclamation step is The oxides in the ditch return to 1 / 2- 3/4 in the ditch. More details of some of the returns in this issue 3 can be found in " DESCRIPTION OF THE PREFERRED'S " The above and other g's in the second embodiment of the present invention are implemented by using a method for manufacturing a non-border contact, which includes nitrogen in a partially recessed trench. Page 11 43 91 8 6 V. Description of the invention (6) Siliconized passivation layer. The protective nitride liner is completed in the present invention by the following method. After the etch-back of the trench oxide described above, only a part of the recessed oxide remained in the shallow trench. In this step of the process, a key process in the present invention is to form a silicon nitride liner in the trench and on the hard mask nitride. The nitride liner is formed by a low-pressure chemical vapor deposition (L P C V D) method using an ammonia gas and a silane gas. A possible densification step can be performed at high temperatures in a nitric oxide atmosphere or in oxygen and nitrogen before the nitrogen compound. It should be noted that a trench liner composed of a silicon nitride layer will fill the trench area, but the trench is partially filled with oxide under the nitride layer. After the nitride liner is formed, a thick silicon oxide layer is deposited by a high-density plasma (HDP) system and is performed in this way to form a seamless ST I trench fill. Another advantage of this process is that the nitride layer will protect the silicon semiconductor from radiation damage caused by high-density plasma processes. After the deposition of thick high-density plasma (HDP) oxide, the surface was flattened by chemical mechanical polishing (CMP), and the back polishing was terminated by nitrogen consisting of a thin pad and a hard cover化 层。 The layer. After planarizing the surface by chemical mechanical polishing, the nitrided layer is removed by etching, except for a nitride liner which remains in the trench and is protected from etchback by an oxide. A shallow trench (ST I) oxide deposited by high-density plasma (HDP) etching will fill the top of the trench on the nitride liner. The nitride liner will remain in one-half of the trench. The original portion of the recessed oxide under the nitride liner remains at the bottom of the trench. In a third embodiment of the present invention, the above and other objects are achieved by

Page 12 43 91 8 6 V. Description of the invention (Ό It is implemented by the method of making a borderless or "borderless" contact with the substrate diffusion region, which uses a nitride liner that is self-aligned and serves as a passivation layer. Use The nitride liner is in a partially recessed oxide. The contact hole formation and alignment method has the advantages that will be explained. The key point is that the silicon nitride liner is self-aligned and serves as a diffusion region to isolate the edge from the shallow trench. Protects the passivation layer. A major advantage of the nitride liner is that it will form a borderless contact without reducing the polysilicon-to-polysilicon spacing (a major design advantage). In addition, the nitride liner protects the The trench isolation edge does not cause contact hole errors and is not affected by the self-aligned silicide formation process. The nitride liner electrically insulates the trench isolation edge and reduces field edge leakage current. As mentioned above, the nitride liner Protecting the silicon semiconductor from the radiation generated by the previous high-density plasma process. Another object of the present invention is to provide an improved trench filling formation. In the above-mentioned multiple-step ST I oxide filling process, the portion of the recessed oxide will assist in filling trenches with a high aspect ratio and help eliminate S T I oxide seams and holes. Traditionally used in the present invention to manufacture devices The processing steps are described below. Prior to forming tungsten contacts or plugs / pillars, most standard processes are performed (a) polycrystalline silicon deposition, doping, annealing, and scribing to form polycrystalline silicon gates (not shown in the figure), (B) tungsten silicide formation process, (c) undoped silicate glass (USG) formation process, (d) atmospheric pressure chemical vapor deposition of borophosphosilicate glass formation process (SACVD BPSG), (e) Plasma assisted tetraethyl orthosilicate oxide (PE TEOSK is not shown in the figure) to flatten the surface. All the standard processes for providing these layers include forming an intermediate

Page 13 4391 δ6 V. Description of the invention (8) Insulation layer (ILD). After the contact holes are defined and etched, they are then deposited by CVD tungsten. The tungsten plug / plunger is formed, and the misalignment of the contact hole is solved by the nitride of the present invention, which is protective and passivation. [Brief description of the drawings] The purpose and other advantages of the present invention will be described in the preferred embodiment with reference to the accompanying drawings, in which: The cross-sectional view of FIG. Shallow trench isolation for thick oxide blanket overlying deposition. The cross-sectional view of FIG. 2 illustrates the planarization method by surface CMP. The cross-sectional view of FIG. 3 illustrates a method according to an embodiment of the present invention, whereby a part of a recessed trench isolation is formed and a passivated trench liner is manufactured. The cross-sectional view of FIG. 4 illustrates a method according to an embodiment of the present invention, whereby a high-density plasma insulator is blanket-deposited to fill trenches without holes and fine slits. The cross-sectional view of FIG. 5 illustrates the planarization method of the surface CMP terminated by the nitride mask layer of the hard mask. The cross-sectional view of FIG. 6 illustrates a trench isolation formation method whereby the thick hard mask nitride layer is removed. Figure 7 is a cross-sectional view illustrating a method according to an embodiment of the present invention, whereby the source / drain of a MOSFET device is electrically contacted with a passivated nitride trench liner using a borderless or "borderless" M contact hole . Brief description of drawing number 2 substrate 4 pad oxide layer

Page 14 4 3 9186 V. Description of the invention (9) 6 Silicon nitride hard cover curtain layer 8 Shallow trench 1 0 Silicon oxide layer 1 2 Oxide layer 1 4 Dashed line 1 6 Oxide 1 8 Silicon nitride liner 1 9 dashed line 2 〇 silicon oxide layer 2 2 nitride pad 2 4 STI oxide 2 6 oxide 3 0 contact hole formation 3 1 contact hole misalignment 3 2 silicon nitride pad 3 3 source / drain region 3 4 Tungsten silicide 3 5 Arrow 3 6 STI oxide 3 8 Boron filled silicate glass 4 0 STI oxide layer 5 0 Crane plug / plunger [Description of preferred embodiments] The main embodiment of the present invention is Single-process using partially sunken trench isolation (STI) to create a new and improved method for making no-border contact. Referring to Figure 1, --- semiconductor substrate 2 is provided, which is usually --- single silicon Substrate. A pad oxide layer 4 is formed by growing a silicon dioxide layer by heat. A silicon nitride hard mask layer 6 is deposited. A shallow trench 8 is scribed, and the hard mask nitride layer and the pad oxide are scribed using a reverse mask process. A shallow trench is etched and a thick layer of oxidized sand 10 is deposited, which has a slight tilt on the surface caused by the trench filling process. The thick silicon oxide layer shown in Fig. 1 is deposited by CVD method under the following detailed process conditions. The target film thickness is about 5000-10,000 Angstroms. The deposition temperature is about 40 0-8 0 ° C. Reactive gases are silane, oxygen, ozone and dichlorosilane

Page 15 43 91 8 6 V. Description of the invention (ίο)

Referring to FIG. 2, the thick oxide layer 12 is shown in FIG. 2 and is almost the same as the hard mask 6 nitride layer (as back-polishing) and as shown in the figure. At this time, part of the silicon oxide etch-back step will make ^ Plate light stop layer) co-planar etching process begins. In the part of the etch-back step, the etching process or the oxide in the wet canal is etched back to about 14 lines. As shown. Etched under the following detailed process conditions. In the case of the selective chemical recovery process, the chamber pressure is about 5-50 mTQl> t, and the power is about 1000-20 00 watts. The engraving rate is about 0.00-60000 minutes' and the target removal amount is 5000-1000 Angstroms. The reaction gas contains: CF4, CHF3, SiF4 ,, C4, Fs, Ar, 02. For the wet etch process, the temperature of the ‘lean dry forging for electroless forging’ is about 80-200.

Released hydrofluoric acid (DHF) is used to remove about 2000-4000 Angstroms, and the target oxide remaining in the trench is about 1500-2500 Angstroms thick. Referring to FIG. 3, after part of the etch-back, only part of the recessed oxide 16 for ST I is left in place. At this stage of the process, a silicon nitride liner 18 is formed in the trench and on the hard mask nitride 6. The nitride liner 18 may be formed by low pressure chemical vapor deposition (LPCVD) using ammonia and silane gas (at about 400-800 ° C) or by plasma deposition process. The target film thickness is approximately 500-1000 Angstroms. Before the nitride liner, a densification step may be performed using nitric oxide, oxygen, and nitrogen. In addition, the following gases can be selected: N2, 〇2, N2〇, N02, NO. Referring to FIG. 4, after forming the nitride liner, a thick silicon oxide layer 20 is deposited by a high-density plasma (HDP) system and is shaped in this manner.

Page 16 43 91 8 6 V. Description of the invention (π) Filling into a seamless ST I trench. Another advantage of this process is that the nitride layer 18 will protect the silicon semiconductor 2 from radiation damage from high-density plasma. The seamless process conditions of the high-density plasma oxide layer in Figure 4 are as follows: PECVD reactor, the temperature is about 3 0-5 5 0 ° C, the reaction gas is SiH4,

Si H2C12, 02, 〇3, the target film thickness is about 15 0-3 500 Angstroms. Referring to FIG. 5, after the deposition of the post HDP halide 20, the surface is flattened by CMP and the back polishing is terminated in the nitride and the oxide layer, as shown by the dotted line 19. Referring to FIG. 6, after the surface is planarized by CMP, the nitrided layer is removed by etching except for the nitride liner 22 remaining in the trench. The residual S T I oxide 2 4 fills the top of the trench. The nitride pad 22 is approximately at the midpoint of the trench. The portion of the recessed oxide 26 in Fig. 6 is drawn at the bottom of the trench. The value of the nitrided layer (non-nitride liner 2 2) was removed in detail to select the maximum value condition: (a) Selective full-type surname engraving process 'It is an aqueous solution mixture of sulfuric acid and hydrogen peroxide' (B) Remove the entire gaseous hard mask, usually remove about 1 500-2 0 0 angstroms, (c) remove about 100-300 angstroms of oxide amount 'U) in The number of oxides remaining in the trench is about 2500 to 5000 Angstroms. Referring to FIG. 7, most advantages of the contact hole formation 30 are shown. The key point is that the self-aligned passivation nitride cutting pad 32 allows for borderless contact to the source / drain regions 33 and does not reduce the polycrystalline silicon to polycrystalline silicon spacing (not shown in the figure). It should be noted that 'the contact hole is misaligned 31 and the edge of the isolation trench is protected by a nitride pad. In addition, the nitride pad 32 will protect the field edge junctions from excessive metal silicide protection as shown by arrow 35 during the self-aligned silicide process. Passivation nitride

Page 17 ^ 43 91 3β V. Description of the invention (12) The trench isolation area protected by the pad 35 can also avoid the influence of the titanium silicide process and reduce the leakage current at the field edge junction. As mentioned above, the nitride pad will also prevent the silicon semiconductor from being damaged by the radiation of the HDP process. The contact hole formation process of FIG. 7t uses special processing conditions to selectively etch oxides without etching the protective nitrided layer. A plasma dry etching process is used to selectively remove the oxide and terminate on the nitride liner (32). The dry-etching temperature is about 80 ° -200 ° C. Referring to FIG. 7, the partially recessed ST I oxide 36 will help reduce the aspect ratio of ST I oxide filling and help eliminate ST I oxide gaps and holes. The top of the nitride pad is an ST I oxide layer 40. Referring again to Figure 7, before the mine contact or plug / plunger formation 30, most standard processes will be performed, such as the following process steps: (a) thin gate oxide formation (not shown in the figure), (B) polycrystalline silicon deposition, doping, annealing and scoring to form a polycrystalline silicon gate (not shown in the figure), (c) a polycrystalline silicon gate spacer process, and (d) an ion implantation and diffusion process to form a source Electrode / drain electrode 3 3, (e) tungsten silicide 3 4 formation process, (f) undoped silicate glass 3 6 formation process, deposit the film to a thickness of about 100 angstroms (g) subatmospheric pressure chemistry Vapor-deposited borophosphosilicate glass 3 8 formation process, the film is deposited to a thickness of about 4000 angstroms (h) plasma-assisted tetraethyl orthosilicate oxide (not shown in the figure) to make the surface flattened. All the standard processes for providing these layers include forming an intermediate insulating layer (I LD). After the contact holes are defined and etched, they are then deposited by CVD tungsten. A tungsten plug / plunger 50 is formed in the contact hole 30, as shown in FIG. Although the invention has been particularly disclosed and described with reference to its preferred embodiments,

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Claims (1)

43 918 6 VI. Scope of patent application 1 · A method for manufacturing a part of a recessed shallow trench isolation structure on a semiconductor substrate to prepare a passivated trench liner, the method includes the following steps: setting a semiconductor substrate, the semiconductor A trench is formed therein * A pad oxide layer is formed on the semiconductor surface; a silicon nitride hard mask layer is formed on the semiconductor surface T The trench is insulated with a thick layer Layer filling; flatten the insulator to obtain a trench isolation area that is almost in the same plane as the hard cover layer, and etch back the trench insulator to 1/2 or 3/4 of the trench; thus forming a partially recessed shallow trench The isolation is formed on a semiconductor to prepare a passivation trench liner. 2 The method according to item 1 of the patent application park, wherein the pad oxide is thermally grown to a thickness of 100-300 Angstroms. 3. The method according to item 1 of the scope of the patent application, wherein the hard mask layer is silicon nitride having a thickness of 100-300 angstroms, which is a stop layer of chemical mechanical polishing (CMP). 4. The method according to item 1 of the scope of patent application, wherein the step of filling the trench comprises depositing a thick insulator, which is tetraethyl orthosilicate to form a silicon oxide having a thickness of 5000 to 10,000 angstroms. 5. The method according to item 1 of the scope of patent application, wherein the step of planarizing the trench is CMP. Page 20 4391 86 6. Application for Patent Scope 6. The method described in item 1 of the scope of patent application, wherein the trench filled with silicon oxide is etched back using dry reactive ion etching (RIE) or wet etching process to A partially recessed oxide trench is formed. 7. A method for manufacturing a part of a recessed shallow trench isolation structure formed on a semiconductor substrate and forming a passivation trench liner, the method includes the following steps: setting a semiconductor substrate having a trench formed therein; A liner oxygen is provided with a hard cover to deposit the trench, and the trench is deposited to cover the remaining isolation, and the partition plane is thus shaped like an application layer, a curtain layer, and a thick insulation. In the area of the body, the contact edge layer is separated from the trench area by a flat flat channel to isolate the trench area of the insulation insulation passivation insulation liner. The trench isolation area that is flat from the insulator forms a protective blunt layer and the surrounding area. 7 Patented steps with a depositional margin bottom include engraving on the semiconductor surface; it is engraved on the semiconductor surface; edge layer filling; to obtain almost the same plane as the hard mask layer to 1/2 or 3 / of the trench 4 places; in the trench and at the top of the hard cover curtain layer for insulation and isolation; an insulating insulation material is filled to form a unit, to obtain almost the same as the hard cover curtain layer, Removing the hard mask layer; layer, which is interposed between the liner and the wall of the trench isolation barrier between the top layer of the insulator. The method described in item 1 forms a passivation trench, a silicon nitride layer with a thickness of 500-1000 angstroms. Θ Page 21 43 91 8 6 VI. Patent Application Range 09. The method described in item 7 of the patent application range, wherein after the passivation trench liner is formed, a high-density plasma (HDP) silicon oxide trench is filled. The system is used to fill trenches without holes or gaps. 10 · The method as described in item 7 of the scope of the patent application, wherein the step of filling the remaining portion of the trench includes the deposition of a thick insulating layer, which is tetraethyl orthosilicate to form a thickness of 1500-3500 Angstrom silicon oxide. 11. The method according to item 7 of the scope of the patent application, wherein after the passivation liner is formed with the thick HD P oxide, the step of finally planarizing the trench is CMP. 1 2 · A method for manufacturing a part of a recessed shallow trench isolation structure on a semiconductor substrate, wherein a passivation trench liner is used to make the MOSFET's borderless contact. The method includes the following steps: setting a semiconductor substrate, The semiconductor has a trench formed in which y is provided with a pad oxide layer, which is depicted on the semiconductor surface; a hard mask layer is provided, which is engraved on the semiconductor surface; and the trench is filled with a thick insulating layer ; Planarize the insulator to obtain a trench isolation area that is almost in the same plane as the hard cover layer; etch back the trench insulator to 1/2 or 3/4 of the trench; deposit a passivation insulating layer in the trench and hard The top of the cover layer is used to cover the wall surface of the cushion and the isolation insulator; the remaining trench is filled with an isolation insulation material to form a Page 22 43 91 B 6 pole / ί and poles form self-dielectric insulating holes in the source pads will be recessed or half-marginal or non-existing. No. 12 500-1000 No. 12 No. 12 plate formed chemical trench lining The method on the silver engraving step, in which there is no marginal contact, is flattened to obtain an area that is almost the same as that of the hard mask layer, and then the hard mask layer is removed; forming an intermediate electrode of the M 0 SF Ε and capacitor oxide Integrating, doping, annealing, and scoring to set the gate electrode 6. Patent application separation area, oxidize the surface of the trench isolation plane of the isolation insulator to isolate the polysilicon gate sinker; form the M 0 SFET The source deposits and selectively deposits and forms an intermediate scribe and etch contacts the passivation trench liner. Therefore, it is used in the manufacture of part of the passivation layer. The semiconductor substrate should form a silicon nitride passivation surface that is not subject to contact holes. A method for manufacturing a partially recessed shallow trench purification trench. The method includes setting a semiconductor substrate and the half of the diffusion region; aligning the silicide layer; Layer; / and the pole P-N interface diffusion area, and the corner area of the protection trench; the protective border in the recessed trench isolation contacts. The method described, wherein the passivation trench is made of silicon nitride. The method described above includes a step of abutting a P-N junction and the previous steps of the padding will protect the P-N influence. The trench isolation structure is formed on a semiconductor substrate. The trench liner is used to fabricate a MOSFET and includes the following steps: The conductor has a trench formed therein. Q Page 23 43 91 8 6 VI. The scope of the patent application is provided with a pad oxide layer, which is engraved on the semiconductor surface; a hard cover curtain layer, which is engraved on the semiconductor surface; the trench is thickly insulated Layer filling; planarizing the insulator to obtain a trench isolation area almost in the same plane as the hard mask layer; etch back the trench silicon dioxide insulator to 1/2 or 3/4 of the trench; deposit a nitride dream The purification layer is placed in the trench and the top of the nitrided hard cover layer to cover the wall of the gasket and the silicon dioxide insulator. The remaining trench is filled with a high-density plasma deposition of silicon oxide insulation material. Forming an isolation region; planarizing the silicon oxide isolation insulator by CMP to obtain a trench isolation region almost on the same plane as the silicon nitride hard mask layer, and then removing the nitride hard mask layer; 'oxidizing the silicon surface To form the thermal silicon dioxide of the MOSFET's gate and capacitor insulator; deposit, dope, anneal, and scribe polycrystalline silicon gates; set gate wall isolation; form the source of the MOSFET / Drain diffusion region; deposit and selectively form a self-aligned silicide layer; deposit and form an intermediate dielectric insulating layer; scribe and etch the contact hole in the source / drain P-N junction diffusion region; by CVD A conductive metal is deposited in contact with the contact hole; therefore, the silicon nitride passivation pad in a partially or semi-recessed silicon oxide trench isolation is used to make the source / drain connected to the MOSFET. Page 24 43 91 8 6 VI. Patent Scope Extremely borderless or borderless contact. 16. The method as described in item 15 of the scope of patent application, wherein the silicon nitride passivation pad will protect the silicon from radiation damage during subsequent process steps or after processing is completed. 17 The method as described in item 15 of the scope of patent application, wherein the process including the formation of passivated silicon nitride trench liners is used in complementary MOS (CMOS) transistors with p-type and ri-type MOSFET gate channels . Page 25