TW439130B - Method of manufacturing a gate structure for a semiconductor memory device with improved breakdown voltage and leakage rate - Google Patents

Abstract

The invention is a method of manufacturing a semiconductor memory device using a novel intergate dielectric stack. A key feature of the invention is the novel O/N/SiON/O structure, forming a silicon oxynitride layer on the silicon nitride layer. The method begins by forming a first insulating layer and a first conductive layer on a semiconductor substrate having one conductivity type. A second insulating layer is formed on the first conducting layer by sequentially stacking: a first silicon oxide layer; a silicon nitride layer; a silicon oxynitride layer; and a second silicon oxide layer. A second conductive layer is formed on the second insulating layer. The first insulating layer, the first conductive layer, the second insulating layer, and the second conductive layer are patterned to form a floating gate, an intergate dielectric, and a control gate. Finally, a source and drain are formed to complete the memory device.

Description

43 m C V. Invention " — Background of the Invention: 1. Technical Field of the Invention The present invention relates to a method for manufacturing a leisure structure of a semiconductor memory device. More specifically, the present invention relates to a method for improving electrical properties with a dielectric between ONO gates. 2 · 4 Eyes Relevant Technology Description In a traditional semiconductor memory device, a 100N0 dielectric film is used as an inter-electrode dielectric, which has a silicon oxide film / a nitride breakdown film / a silicon oxide film Composed of stacked structures. The ON0 structure has a very thin film, which provides excellent withstand voltage and hysteresis characteristics. However, semiconductor device manufacturers continue to increase effective device density while maintaining cost competitiveness. Since the ONO dielectric film becomes thinner, the pinholes of the nitride and poor electrical quality characteristics will cause a low breakdown voltage and leakage current that negatively affect the reliability of the memory device. Therefore, an inter-gate dielectric film for a semiconductor memory device, which can provide higher withstand voltage and hysteresis characteristics when the film thickness becomes thinner, is required. The closest and obviously more relevant technological developments in the patent literature can be gleaned from the following patents.

U.S. Patent No. 5,661,056 (Takeuchi) discloses nitrogen oxides formed on an oxide layer of -NO, and a NON dielectric stack. U.S. Patent No. 5,597,75 4 (Lou et al.), U.S. Patent No. 5,42 7,96 7 (Sad j ad i), and U.S. Patent No. 5,665,620 (Nguyen) for disclosure Method for forming ONO stack. US Patent No. 5,443,998 (Meyer) discloses a method for forming

Page 5 ο 5. Description of the invention (2) Gasification of ΝΟΟ stacking method. U.S. Patent No. 5,407,870 (Okada) discloses a nitrogen oxide / halide / nitrogen oxide stack. SUMMARY OF THE INVENTION: An object of the present invention is to provide improved electrical properties (especially withstand voltage and leakage current) over conventional MOS stacked gate-to-gate dielectric layers. Another object of the present invention is to provide a structure and a conventional 0 N 0 stacked gate-to-gate dielectric layer with a relatively large thickness, which has a higher electric resistance! And lower leakage current of improved semiconductor memory device gate method. Another object of the present invention is to reduce or eliminate the problem of pinholes formed in a nitride layer of a conventional ONO stacked dielectric layer. Another object of the present invention is to reduce structural stress (phase 0N0 stacked dielectric layers). 'In order to achieve the above-mentioned gate, it includes: ion, and has a semiconducting and non-electrode region; the source compound; the dielectric located between the channels, which is composed of silicon nitride, oxynitride dielectric The upper one controls the gate method of the present invention. On this side, a floating gate silicon electrode is provided above a body substrate electrode and a drain oxide on the silicon and oxygen gates to provide a conductive type of opposite conductive region. A method for forming a type of semiconductor substrate on a type of semiconductor substrate that is electrically isolated from each other by a channel region above a channel region of oxygen-floating gate electrode; a continuous oxide stone above the gate electrode; and The first insulating layer (1 2) of a semiconductor memory device is manufactured between the gate electrodes and

Page 6 43 913 0 V. Description of the invention (3) A semiconductor substrate (10) of the conductivity type. A first conductive layer (14) is formed on the first insulating layer (1 2). A second insulating layer is formed on the first conductive layer (14). Its stacking sequence is: a first silicon oxide layer (16); a silicon nitride layer (18);-a silicon oxynitride layer (20); and a second silicon oxide layer (22). A second conductive layer (24, 26, and 28) is formed on the second insulating layer (16, 18, 20, and 2 2). The first insulating layer (12) is characterized to form a channel oxide. The first conductive layer (1 4) is depicted to form a floating gate electrode. The second insulating layer (16, 18, 20, and 22) is engraved to form an inter-electrode dielectric. The second conductive layer (24, 26, and 28) is scribed to form a control gate. pole. Impurity ions are implanted on both sides of the semiconductor substrate (1 0) adjacent to the floating gate electrode (丨 4) to form source and drain regions (30) and (3 2) 'so that it has The conductivity type is opposite to the conductivity type of the semiconductor substrate. A wall surface insulating film is formed on the sides of the floating gate electrode (4) and the control gate electrode (24, 26, and 28). Description of the preferred embodiment: To achieve the purpose of the present invention, the method for forming a gate of a semiconductor memory device having an improved inter-gate dielectric will be described in detail. The sequence of manufacturing steps of a semiconductor memory device gate having an improved inter-gate dielectric is shown in the i-th figure. It should be noted that the scheme is greatly simplified. This method first provides a semiconductor substrate process, as is well known in the art. The semiconductor substrate preference has been partially processed, such as isolation and well formation as is well known in the art. As shown in Figure 1, a first insulating layer 12 is formed on an active region. The first insulating layer 12 is preferably an oxide layer (channel oxide).

4 3 91 3 0 V. Description of the invention (4) It can be formed using a wet process in a water vapor atmosphere or a dry process in an oxygen atmosphere. Preferably, the first insulating layer 12 is in a temperature range between 8 50 ° C and 105 0 ° C, and a pressure range between 7 1 0 Torr and 8 1 0 Torr in a dry process. The time range is between 10 minutes and 60 minutes, and is grown to a thickness range between 90 angstroms and 120 angstroms. As also shown in FIG. 1, a first conductive layer (such as a polycrystalline dream) 14 is formed on the first insulating layer 12. The first conductive layer 14 can be formed using a chemical vapor deposition (CVD) process that pyrolyzes silanes at a temperature of 5 7 5 ° C to 650 ° C and a pressure of 2 5 Pa to 130 Pa. . Secondly, the first conductive layer 14 is preferably doped by implanting phosphorus ions therein. Secondly, as shown in FIG. 1, a first silicon dioxide layer 16 is formed on the first conductive layer 14. The first silicon dioxide layer 16 can be formed using a chemical vapor deposition process, which is performed by oxidizing silane with oxygen at a temperature of 40 (TC to 4 5 (TC at 'atmospheric pressure or low pressure'). ; Decompose TEOS at a low temperature at a temperature of 650 ° C to 750 ° C; at a temperature of 850 ° C to 900 °. (: Temperature At low pressure, silicon dichloride is reacted with nitrogen dioxide; or it is preferred to oxidize polycrystalline silicon with oxygen at a temperature between 8 5 ye and 95 0 ° C under atmospheric pressure. A layer of stone dioxide layer is preferably formed in a thickness range between 30 angstroms and 100 angstroms. Secondly, as shown in FIG. 1, a silicon nitride layer 18 is formed on the first silicon oxide layer 1 6 above. The silicon nitride layer] 8 can be formed using a chemical vapor deposition process, which is carried out under atmospheric pressure and in a temperature range between 70 ° and g °. Reaction; or preference by depressurization range between 25Pa to 100pa and temperature between 70 (Γ (: to 80 (rc) ΙΓΓΊΙΗ

5. Description of the invention (5) Scope 'The reaction of digas silane with ammonia gas. The silicon nitride layer 18 is preferably formed in a thickness range of 50 to 150 angstroms. In a main step, as shown in FIG. 2, a thin silicon oxynitride layer 20 is formed on the top of the silicon oxynitride layer 18. Processed in a nitrogen-containing gas such as NO or N20. This processing can be done by the silicon nitride layer 18 in the furnace body or, preferably, by rapid heat treatment (RTP). Preferentially, the N 20 gas has a flow rate range between 1000 seem and 1,000 sccm, a temperature range between 90 ° C. and 10 ° C., and a pressure range between 10 kPa and 100 ^ pa. 'Flow time between 20 seconds and 180 seconds. The nitrided 20 preference is formed to a thickness range between about 5 angstroms and 30 angstroms. F times' as shown in Figure 1' use as In the aforementioned chemical vapor deposition process or oxidation process, a second layer is prepared above the Shixi layer 20. The second cut layer 22 is formed in a thickness range between 50 Å and 50 Å. The silicon oxide layer 22 is preferred to be It is formed as 20 angstroms to a layer of the first inter-gate dielectric layer as shown in Fig. 1. The conductive layers 24, 26, 28 are formed on a tungsten silicide layer 26 and a complex BI: The first—the polycrystalline silicon sublayer 24, the polycrystalline silicon sublayer 24, and the polycrystalline silicon covering the scotch sublayer 28. This first pass was formed by using chemical vapor deposition at 57 $ 28 The pressure of 130Pa will be used to dissolve the syringane. = To the temperature of 65, at 25Pa to the process or prefer a thermal evaporation process (such as + tungsten tungsten sublayer 26 can use a sputtering last, such as 1 shown in the figure, which is well-known in the art). The first insulation layer Ϊ2, Dai uses optical micro, as well known in the art, 18, 20, 22 and the second conductive screen. 〇The conductive layer 14 and the second insulating layer 16 are 24′26, 2 8 are carved and formed into a

t 4391 3 Ο_ 5. Description of the invention (6) Channel oxide, a floating gate, a dielectric between gates, and a control gate. Thereby, a source 30 and a drain 32 are formed to complete the memory device. Advantages: The present invention provides many advantages over conventional techniques. While the advantages of traditional ONO stacking (including manufacturing capabilities) are maintained, the present invention can oxidize dangling bonds by using oxygen decomposed by N20 and NO gas, thereby reducing structural stress and eliminating pinholes. The present invention has been proven to increase the withstand voltage and reduce the leakage current, thereby providing superior performance and making it easy to reduce the thickness. The device is manufactured using the present invention (0 / N / Si ON / 0), using a conventional ON0 process and using two additional processes. This effective thickness is determined using a high-frequency capacitor voltage (HFCV) test known in the art. The breakdown voltage (Vbd) is determined by using a boost test to measure the voltage when the current reaches 1.0 microampere. The breakdown electric field (EJ is determined by V b Xu with this effective thickness. The test results are shown in Figure 3. Although the present invention has been specifically shown and described with reference to its preferred embodiment, it should be Those skilled in the art understand that various changes in form and detail can be made without departing from the spirit and scope of the present invention. 0 Brief description: 10 Semiconductor substrate 12 First insulating layer 14 First conductive Floor

Page 10 V. Description of the invention ⑺ 1 6 First silicon dioxide layer 1 8 Silicon nitride layer 2 0 Silicon oxynitride layer 2 2 First silicon dioxide layer 2 4 Second conductive layer 2 6 Second conductive layer 2 8th, • Conductive layer 3 0 Source 3 2 Drain 1_ View of the schematic diagram The first figure is a cross-sectional view illustrating the present invention. Fig. 2 is a cross-sectional view illustrating the main steps of the nitrogen oxide formation of the present invention. FIG. 3 illustrates experimental data of the present invention compared with a conventional ONO dielectric layer.

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Claims (1)

Scope of Patent Application1. A method for manufacturing a semiconductor memory device, comprising the steps of: a) forming a first insulating layer on a semiconductor substrate having a conductivity type; b) forming a first A conductive layer on the first insulating layer; c) forming a second insulating layer, which are sequentially stacked: (I) a first silicon dioxide layer; (Π) —a layer of nitrided nitride; (m) —layer A silicon oxynitride layer; and (IV) —a second silicon dioxide layer; on the first conductive layer; d) forming a second conductive layer on the second insulating layer, and e) depicting the first insulation Layer, the first conductive layer, the second insulating layer and the second conductive layer to form a floating gate, a dielectric layer between the gates, and a control gate. 2. The method according to item 1 of the scope of patent application, wherein the silicon oxynitride layer is formed by rapid heat treatment of the nitrided layer, which is in a nitrogen-containing gas at 900 ° C to 110 ° A temperature range between 0 ° C and a pressure range between 10 kPa and 100 kPa, and a time between 20 seconds and 180 seconds; wherein the silicon oxynitride layer has a thickness between 5 angstroms and 30 angstroms. 3. The method according to item 1 of the patent application range, wherein the silicon oxynitride layer is formed by processing the silicon nitride layer in a N 20 gas. 4. The method according to item 1 of the patent application range, wherein the silicon oxynitride layer is formed by processing the silicon nitride layer in a NO gas. Page 13 43 913 0 6. Application scope 5 · A method for manufacturing a semiconductor memory device, comprising the steps of: a) forming a first insulating layer on a semiconductor substrate having a conductivity type B) forming a first conductive layer on the first insulating layer; c) forming a first silicon dioxide sublayer on the first conductive layer; d) forming a silicon nitride sublayer on the first two On the silicon oxide sublayer; e) annealing the silicon nitride sublayer in a gas containing oxygen and nitrogen; f) forming a second silicon dioxide sublayer on the annealed silicon nitride sublayer; g) Forming a second conductive layer on the second silicon dioxide sublayer; h) the first insulating layer, the first conductive layer, the first silicon dioxide sublayer, and the annealed silicon nitride sublayer; Layer, the second silicon dioxide sublayer, and the second conductive layer to form a floating gate, an inter-gate dielectric layer, and a control gate; and i) forming a source and a gate electrode. 6. The method according to item 5 of the scope of patent application, wherein the annealed silicon oxynitride secondary layer is formed by rapid heat treatment of the silicon nitride layer, which is in a gas containing nitrogen and oxygen at 9 The temperature range from 0 ° C to 110 ° C, the pressure range from 10kPa to 10OkPa, and the time from 20 seconds to 180 seconds. 7. The method according to item 6 of the patent application scope, wherein the annealed silicon nitride sublayer is formed by processing the silicon nitride layer in N20 gas. Page 14 4 3 9 彳 3 〇 6. Application for patent scope 8 * As the method for applying for patent scope No. 6, wherein the annealed silicon nitride sublayer is processed by treating the silicon nitride layer in NO gas. Be formed. 9-A method for manufacturing a semiconductor memory device, comprising the steps of: a) forming a first insulating layer on a semiconductor substrate having a conductivity type; b) forming a first conductive layer; An insulating layer; c) forming a first oxydioxide secondary layer on the first conductive layer; d) forming a nitrided sublayer on the first dioxide secondary layer; e) by The silicon nitride layer is rapidly heated to form a silicon oxynitride sublayer, which is performed in a gas containing nitrogen and oxygen at a temperature range of 90 ° C to 1100 ° C and a pressure range of 10kPa to 100kPa. Time between 20 seconds and 180 seconds; f) forming a second silicon dioxide sublayer on the silicon oxynitride sublayer; g) forming a second conductive layer on the second silicon dioxide sublayer H) the first insulating layer, the first conductive layer, the first silicon dioxide sublayer, the annealed silicon nitride sublayer, the second silicon dioxide sublayer, and the second A conductive layer to form a floating gate, a dielectric layer between the gates, and a control gate; and Into a source and a drain. I 0 The method according to item 9 of the patent application range, wherein the silicon oxynitride sublayer is formed to a thickness ranging from 5 angstroms to 30 angstroms. II. The method of claim 9 in which the annealed silicon nitride secondary layer is formed by processing the silicon nitride layer in N 20 gas Page 15