TW439127B - Method for manufacturing semiconductor self-aligned dual-doped gate - Google Patents

Abstract

There is provided a method for manufacturing semiconductor self-aligned dual-doped gate, which is suitable for a substrate having a source/drain region, a first region and a second region. The method comprises: sequentially forming a gate insulating layer, a first conductive layer, a first insulating layer doped with second impurity ions, and a second insulating layer without being doped with impurity ions; defining and removing the second insulating layer without being doped with impurity ions and the first insulating layer doped with second impurity ions of the first region; implanting first impurity ions on a first conductive layer of the first region wherein the first impurity ions cannot enter the second region due to the block of the second insulating layer without being doped with impurity ions; performing a thermal driving procedure to remove the second insulating layer and the first insulating layer of the second region, and defining the first insulating layer doped with second impurity ions of the first region and second region for forming a gate of the first region and a gate of the second region, respectively, thereby completing the method of the present invention.

Description

5. Description of the invention (1) The present invention relates to a method for manufacturing an integrated circuit, and more particularly to a method for manufacturing a semiconductor self-aligned double-doped gate. Complementary metal-oxide-semiconductor (CM0S) process is one of the most important semiconductor integrated circuit technologies. 'Memory and logic products are used as the basis for the development of MoS (Metal-Oxide-Semiconductor) transistor elements. The idler electrode is used as the control electrode, that is, the output characteristic of the transistor is controlled by the voltage signal of the gate electrode. Traditionally, compound crystals containing high-concentration n-type impurity ions (such as phosphorus or bell) are used as the gate material. The initial development of the Mos transistor was based on metal (such as Ming) as the gate material ’, which is the origin of the Mos name. After the self-aligned process of ion implantation (ion impiantation) was invented ’, due to the subsequent high-temperature annealing process, the interface characteristics of the polycrystalline silicon and the oxide layer are good, and it can withstand high-temperature manufacturing.

"This is an advantage that cannot be achieved by metals". Polycrystalline silicon therefore replaces metal as the main closed-electrode material D. In general CMOS applications, n + complex silicon serves as the gate of both n_ and channel M0S. The so-called single poly scheme has the main advantage of easy processing, but the absolute value of the starting voltage (Vth) of the ^ station will be large (>! V). From the point of view of circuit design, if you want to meet the requirements of high speed and low power loss, the Vth of p- and n-M0s must be positive-negative and not too large, so the P-M0S element is usually used before the gate is formed. The channel region is subjected to a doping process (such as boron ion implantation) to reduce the absolute value of Vth. This p_M0s structure is called a buried channel M0S, while the n-M0S structure is called a surface channel M0S, which mainly reflects the relative oxygen of channei.

V. Description of the invention (2) The location of the oxide / Si substrate interface, this CMOs method has therefore become the industry standard technology. However, the bottleneck began to be encountered after the 0 35 m process. The main problem was the short channel effects of the p-MOS transistor. Because the carrier channel in the latent channel is far away from the oxide interface, the gate Poor controllability ', so compared with the surface channel element, the short channel effect is much more serious. To 0. 2 5 // m transistor production, its related effects' such as Vth drop (roll-off) and source-induced barrier lowering (drain-induced barrier lowering) caused an increase in leakage current and other phenomena, are quite equivalent Difficult to control 'so structural changes must be made to address this issue. The CM ,. OS structure formed by the dual poly silicon scheme (dual pol y scheme) is different from the early single poly scheme in that poly-Si is used as the gate of p-MOS, so Components that can make area channels' are, however, more complicated in procedure. Since both P- and n-MOS are area channels, the controllability of the short-channel effect can be improved. At present, this double-multiplexed silicon method seems to have become the mainstream of the gate technology of 0.2 5 ~ 0, 18 μm. There are also publications in the literature that this method can be successfully applied to the development of 0.08 CMOS, showing its potential. Traditional single polycrystalline silicon CMOS circuits, many manufacturers prefer to use in situ doping chemical vapor deposition (CVD) n + poly Si thin films, because it can save the time of implantation and annealing cost. However, this method is not feasible when using the double polysilicon method. In order to improve the aforementioned problems, conventional techniques are to deposit an undoped polycrystalline silicon thin film, complete the lithographic etching of the gate electrode, and then perform P- and η-type elements, respectively.

D: \ CSpatent \ 88006. Ptd Page 5 4391 27 V. Description of the invention (3) The implantation doping and activation of the element, the detailed steps are as follows: As shown in Figure 1A, 'the first is to p-type silicon substrate 1〇 〇 Implement a thermal oxidation process, such as LOCOS, to form a field insulation layer (not shown) and isolate the active area by the field insulation layer. For example, in the first region 180 and the second region 190 in FIG. 1A, t, the first region 180 is PMOS, and the second region 190 is MMOS. Then, the inter-electrode insulation layer 110 is generated on the surfaces of the first region 180 and the second region 19 by erbium oxidation, and then a polycrystalline silicon conductive layer 12 is deposited. Please refer to FIG. 1B and apply a photoresist 122. First, a photolithography process is performed with a photomask to define the photoresist 122, and then the photoresist 122 in the second region 190 is removed by an etching process, and the photoresist 12 in the first region 180 is retained. In the implantation process, boron ions are implanted in the polycrystalline silicon conductive layer 120 of the second region 190, and thereafter, the boron ion-doped polycrystalline silicon conductive layer 120 is represented by the boron ion doped polycrystalline guide 120b. 10w Please refer to Figure 1C, remove the photoresist 122, then apply a layer of photoresist 124, and then perform a photolithography process with another photomask to define the photoresist. After that, the photoresist in the first area 180 is removed by an etching process. 124, reserve the second zone 19 ^ resistance 124 ,. Phosphate ions were implanted in the first region of the polycrystalline spar of layer 18 in the first region = 12G in the implantation process. From then on, the polycrystalline hard conductive layer doped with erbium ions ... is represented by an ion-exchanged polycrystalline silicon conductive layer 120a. 2 As shown in the figure, the photoresist is removed first, and then the thermal drive-in process is performed to drive the disk ions in the composite W conductive layer 120a and the boron ions in the silicon conductive layer 120b to a proper depth. Figure 1E, “Etching a photolithography process and etching process with a photomask” forms the doped ion core in H8G, and in the second area II 1 ^ 1 page 6 D: \ CSpatent \ 88006. ptd ^ 39127 V. Description of the invention (4)! The doped boron ion gate 12b is formed in 90 °. Refer to Figure F. 'Next, perform the ion doping steps of the conventional semiconductor technology and form the gate sidewalls 50, and complete an N-type metal-oxide semiconductor with source / drain 105 and gate structure ( NMOs) transistor 1 and p-type metal-oxide-semiconductor (PMOS) transistor 170. — According to the above steps, the conventional technology must use three photomasks to complete the manufacture of the double-doped gate structure, and the manufacturing process is more complicated. The present invention is doped with a second type impurity ion (such as boron ion), a silicon glass layer and a nitride layer, and then the first region is doped with a second type impurity ion (such as boron ionomer), and the glass layer and silicon nitride are removed. Insulating layer, when the first type is planted in the first area (the curtain is like a gasified stone, the insulating layer can be used as the ion shielding mask in the second area to protect the polycrystalline silicon conductive layer in the second area from being implanted. The doped first type impurity ions (such as boron ions) of the silica glass layer are used as the decoration implantation source: and then the impurity ions (such as boron ions) are diffused and thermally processed in the polycrystalline silicon conductive layer by the thermal process It becomes a P-type gate. In the same region, the other type of the polycrystalline silicon conductive layer in the first region can be simultaneously driven into the appropriate depth to become a Π-type gate. Phosphorus drives the second-type impurity ions into the polycrystalline silicon conductive layer, which saves the use of a photomask in a standard way. Therefore, the present invention simplifies the steps of the conventional technique, which not only shortens the production cycle but also conforms to the semi-operative process. The need to reduce costs. Mass production urgently needs the present invention which lies in the self-aligned double doped gate Made, the semiconductor substrate having a first region and a second region, the 'forming a gate insulating layer applied to a surface of' in 'accomplishing a first conductive layer on the gate insulating region table Eph Table ,,

• 439] 27 V. Description of the invention (5) layer, the first lightning guide; marginal layer, on the doped surface to form a doped second impurity ions, first impurity ions, first impurity ions, first impurity ion surface Forming a non-doped second-type dopant f 'defines the non-doped second ion insulating layer and the doped ion second insulating layer insulating layer, and removes the non-doped second conductive layer located in the first region = Doping the second type of impurity ion first insulating layer, implanting it in the first region, and performing a first type of impurity ion implantation procedure-the first conductive layer, the conductive layer, forming a doped first type impurity ion Block, so that the second region of Xi Di's do not have implanted dopant ions, the second insulating layer resists the ions, the first insulating ions cannot implant into the doped second type hetero ions, the second insulating layer Λ ', and the second The process of doping the second-type impurity layer in the region and the second-type impurity ions diffuse into the first conductive the first-type impurity ion and the non-doping of the first conductive layer The process of driving the impurity ions t into an appropriate depth to remove the insulating layer in the second region, exposing The first Γ insulating layer and the doped second type impurity ions of the first and second regions are doped with the doped first type impurity ions and the first conductive layer region is doped with the first !! second type impurity ions The first conductive layer defines the first and second type impurity ions. The doped two regions of the first and second ion regions are protected respectively: a conductive layer and a gate insulating layer, and the first and second doped regions are doped. The second type region is doped with the first type impurity ion interrogator and the second region. ', Is an ion gate, and completes the self-aligned double-doped gates of the present invention in order to make the above and other objects, features, and advantages of the present invention clearer ... , And with the accompanying drawings, the detailed description is as follows:

V. Description of the invention (6) Brief description of the diagrams Figures 1 A to 1F show the main steps of the conventional technique "manufacturing method of a double-doped gate". Figures 2A to 2E represent the main steps of an embodiment of the "method for manufacturing a self-aligned double-doped gate" according to the present invention. Symbol description 100, 2 0 0 ~ substrate; 105, 205 ~ source / inverted region; 180, 190, 280, 290 ~ active region; 120, 120a, 12 0b, 220, 220a, 220b ~ conductive layer; 110, 210 2 30, 240, 110 ', 210' ~ insulation layer; 120a ', 120b', 2 20 a ', 220b, ~ gate; 1 2 2, 1 2 4 ~ photoresistor; 150, 2 50 ~ gate Side wall objects; 16 0, 1 7 0, 2 6 0, 2 7 0 ~ transistor. Examples Refer to Figure 2A, which shows the initial steps of the present invention. In the figure, the substrate 200 is a semiconductor material, such as silicon and germanium, and the formation method is

D: \ CSpatent \ 88006. Ptd Page 9 V. Description of the invention (7) There is silicon on the crystal or insulation layer. For the convenience of explanation, a P-type silicon substrate with P-type well area and N-type well area is used here. As an example. The initial step is shown in Figure 2A. First, the P-type silicon substrate 200 is subjected to a thermal curing process, such as a field oxidation method to form a field insulation layer (not shown), and the field insulation layer is used to isolate the active area. As shown in FIG. 2A, the first area 280 and the second area 290, the first area 280 is, for example, a P-type well area, and the second area 290 is, for example, an N-type well area. Then, a gate insulating layer 21 0 is generated on the surfaces of the first region 280 and the second region 290 by a thermal oxidation process. The gate insulating layer 21 0 may be a gate oxide layer having a thickness of 30 to 150 angstroms. . Secondly, a first conductive layer 22 is deposited on the surface of the gate insulating layer 210. The first conductive layer 220 may be a polycrystalline stone having a thickness of 1000 to 300 angstroms by a low pressure chemical vapor deposition method (LPCVD). In order to reduce its resistance value, arsenic ions or phosphorus ions can be implanted by diffusion or ion implantation methods of conventional semiconductor processes, or by means of simultaneous doping to form a doped conductive layer. Next, a first insulating layer 230 doped with second-type impurity ions is deposited on the surface of the first conductive layer 220. The second insulating layer 230 doped with second-type impurity ions may be formed by a conventional chemical vapor deposition method (CVD). ), Atmospheric pressure chemical vapor deposition (APCVD), sub-normal pressure chemical vapor deposition (SAPCVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), or high density Electrolytic chemical vapor deposition (HDPCVD) with appropriate amount of materials such as Tetra Methyl Borate to deposit a boron-containing ion (p-type impurity ion abundance) with a thickness of loooo ~ 500 angstroms Layer of silica glass. A non-doped second ion insulating layer 240 is then deposited on the surface of the second type doped impurity ion first insulating layer 230. This non-doped second ion insulating layer 240 may be low voltage

D: \ CSpatent \ 88006. Ptd Page 10 43 91 27 V. Description of the invention (8) Learn about the vapor deposition method (LP r ^ i layer or non-doped material to cut through the glass U5 heart 35GG angstrom of gaseous fossils, please refer to Figure 2B, the photolithography process of y_feng ^ photomask, the step •, doping the second-type impurity ion diion / second insulation layer 240 and imitation co-error „οοη brother insulation layer 23 0 ′ The non-doped second ion insulating layer 24 0 and the second doped impurity ^. And an insulating layer 23 () are removed by an etching step, and the surface of the first conductive layer 220 is exposed. It is an anisotropic etching process. Then, the implantation procedure of the first-mass ion (for example, phosphorus ion) is performed. The ion implantation energy is about 5 ~ 50KeV, and the implantation dose is about 10 × 1016. ns / cm2 to form a first conductive layer 220a doped with a first type impurity ion by the first conductive layer 220 'implanted in the first region 280. The second region 29 is a second insulating layer due to the presence or absence of dopant ions. With the blocking of 24 0, the first type impurity ions cannot be implanted into the first insulating layer 23 () doped with the second type impurity ions. In this step, the non-doped ion The insulating layer 240 replaces a photomask, which can block the first type of impurity from implanting into the first insulating layer 23 doped with the second type of impurity ions. Therefore, a mask can be saved in Keling, which can shorten the production cycle and reduce the cost. Then, a thermal drive-in process is performed, and the second region 290 is doped with the second type impurity ions (for example, boron ions) from the first insulating layer to diffuse into the first conductive layer 22 (). Process, and drive the first type impurity ions (for example, phosphorus ions) in the first conductive layer 22 0 in the first region 2 80 to an appropriate depth. The self-aligned method is used to drive the second type impurity ions by heat. The procedure is the most important feature of the present invention. After this step, the first conductive layer 220 doped with the first type impurity ions is doped with the first type impurity ions.

D: \ CSpatent \ 88006. Ptd Page 11 4 3 91 2 7 V. Description of the invention (9) The conductive layer 22〇a is shown, and the second type impurity is doped 220 ~ to dope the second type impurity, The first conductive layer is represented by 吒. Doping the impurity pattern, then * 'remove the insulating layer 240 of the second region 290 and doping the second-type impurity ion—the second-type impurity ion—the conductive layer by an etching step ”This etching step may be anisotropic An etch step is performed. Please refer to the 2D picture 'Define the impurity in the first region—28 ° with a lithographic process = electrical = 22Γ—doped second type f in the second region 29 ° is carved on the second conductive layer 220b, and then the etching step is used in The first region 28o and the first region 290 form a p of the first region 28o doped with two closed electrodes 22aa of the first type impurity ions and the second region 29o doped p with second type impurity ions. -Type T-pole 220b. This etching step may be performed by an anisotropic etching step, and the self-aligned double-doped gate electrode of the present invention is completed. Please refer to FIG. 2E, and then 'combined with the conventional ion doping step and the formation of the interrogation sidewall 250' to complete an N-type metal-oxide-semiconductor (NM0s) with a source / drain 20 and gate structure ) Transistor 26 and P-type metal-oxide-semiconductor (pM0s) transistor 27 with source / drain 205 and gate structure. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouches without departing from the scope of the present invention. Therefore, the present invention The guarantee scope shall be subject to the definition of the scope of the attached patent application.

Claims (1)

43 Case No. Amendment 1 VI. Scope of patent application _ &i; ar tr- ί ^ ._… 1. A method of manufacturing self-aligned dual-mining adopts the following steps: 'The method of hybrid closed pole, the manufacturing method includes ^ Provide a semiconductor substrate having 苐 ~ regions in the first region and two and second regions; layers; " surface formation of the second region-gate insulation on the open electrode insulation debris formed on the first-conductive it surface-first A conductive layer; Marginal layer; surface formation-doped second type impurity in the above doped second non-doped material age 2 ~ impurity ions first continuation s * negative ion # insulation layer formed a surface, meaning no impurities ： The first insulation layer of impurity ions and the upper and + -red 4Δ brother ~ insulation session. Doping of the fans mentioned in the second ... dopant ion II removes the above-mentioned ionic insulation layer, the above-mentioned doping Type 2 impurity-Implementation-Type-impurity: :: surface of the-conductive layer, · 円-conductive layer? Only directly into the first region of a conductive layer, the first doping of the first type impurity ions should be doped; capture: make the -type impurity ions 4 :: the second simultaneous impurity ion-insulating layer; into the second The above-mentioned doped second-type axis #, s-edge layer, the second impurity impurity electric layer of the s-edge layer, the procedure of the mass ion expansion into the first conductive ion, the conductive layer = the above Procedure for doping the first-type impurity; the conductive layer ...- type impurity ions are properly implanted (9). Remove the above flute _ "man and the (1). (2). (3). (4). (5) (6). ⑴ · (8). Untitled Page 13: A correction supplementary 20 卯 10.19.013 4391 27: Amendment. Case No. 881 of the sixth, the scope of the patent application pushes the second type impurity ion No. -An insulating layer that exposes the doped first-type impurity ion first conductive layer and a region of the doped second-type impurity ion first conductive layer; and ^ the second region (10). The doped first-type impurity ion layer in the second region, the doped second-type impurity ion 2 layer in the second region, and the gate insulating layer are located in the first region and above. The electricity is formed separately-the first region is doped with the first type impurity ions, and the free region is doped with the second type impurity ions. The self-aligned double-doped gate of the present invention is completed. 疋 Self-alignment 2. 3. :: Please f The method of manufacturing a self-aligned double-doped gate described in item 1 of the above-mentioned range, wherein the semiconductor substrate formed is a silicon substrate. In other words, the first-type impurity ion and the second-type heteroboron, phosphorus, or ping ion. The g ion is 4.5. Electrode method wherein the first-type impurity ion is n_-type or p_-type ion. 6. = The method for manufacturing a self-aligned double-doped free-electrode described in item 1 of the patent application scope s wherein the second-type impurity ion It is an η-type or p-type ion. ^ The self-aligned double-doped closed-electrode formation method described in item No. of the scope of patent application, wherein the above-mentioned first conductive layer is formed of polycrystalline silicon Manufacturing self-aligned double-doped gates as described in item 1 of the scope of the patent application _________________ The method of page 14 wherein the thickness of the first conductive layer is 1000 to 3000 angstroms. 2000.10.19.014 4 3 91 27 mWu «8113981 Amendment 6. Scope of patent application The above-mentioned doped second-type impurity ion first insulating layer formed in the method '纟 has a thickness of 1000 to 5000 angstroms. 9. The method for manufacturing a self-aligned double-doped gate according to item 1 of the scope of the patent application, wherein the above-mentioned second insulating layer is formed of silicon nitride or non-doped dream glass. I 0. The method for manufacturing a self-aligned double-doped dysprosium electrode as described in item 1 of the scope of the patent application, wherein the thickness of the non-doped second ion insulating layer is 1500 to 3500 angstroms. II The method for manufacturing a self-aligned double-doped gate according to item 1 of the scope of the patent application, wherein the ion implantation energy for implanting the first type of impurity ions is 5 ~ 50KeV, and the implantation dose is 1015 ~ 1016 inns / cm2. '12. The method for manufacturing a self-aligned double-doped gate as described in item 1 of the scope of the patent application, wherein step (8) causes the drive-in procedure performed in the first region and the diffusion performed in the second region. The program is a hot-drive process. Method j wherein the thermal drive-in process is performed for 10 seconds to 30 minutes. 14. A method for manufacturing a semiconductor white-aligned double-doped gate includes the following steps: (1) * Provided-* 第 »-* Half of the second and second regions (2) On the surface of the first and second regions > (3) Deposit a first (4) on the surface of the gate insulating layer * Deposit on the surface of the above-conductive layer- ~ Doped first insulating layer > 13. Gate self-aligned double-doped gate insulating impurity ions manufactured as described in item i of the patent application _ untitled page 15 2000.10.19.015 (6). (8). (9)., ^ Mwm -Ψ-…, dopant ion second insulation-insulating layer j doped second type impurity ion second insulation wire and the above-mentioned doped second type: ί: κ impurity: heterodyne second-conductive surface; ion first-insulating layer The first type doped with the first ion-conducting implanted electrical layer 'forms a doped first-region so that the first type is doped with the doped second type impurity ion, the first insulation layer is blocked, and a second is implemented. The type diffusion enters the doping process of the dopant, and at the same time, the procedure of the first conductive layer of the second insulating layer of impurity ions and the procedure of the first conductivity of the first type of impurity ions to an appropriate depth are performed. The first type of impurities do not include non-doped plasma and ions: the edge layer; the second type of impurities in the first region; the first type of layers: the first type of layers; the second step is removed by an etching step. Region of the undoped ion insulation layer and the doped second impurity ion first insulation layer, The doped first-type impurity ions of the first region are first conductive. The doped second-type impurity ions of the first region are first conductive and (10). The doping of the first region is defined by a lithography process. The first conductive layer of the hetero-type hetero hetero, the first conductive layer of the doped second hetero hetero in the second region, and the gate insulating layer, and then a step of depositing a layer of 罾 and 'on the edge of the edge in the etching step ] The first: a region [the second second entry dopant expands the above-mentioned second ionized layer and layer; Untitled page 16 2000.10.19.016 ήα it > tiyj ρ 1-^ _Case No. 88113981_ year, month and day _. Scope of patent application The above first region and the above second region respectively form a first region and a doped first -Type impurity ion gate and second region doped with second-type impurity ion gate to complete the self-aligned double-doped gate of the present invention. 15. Manufacture semiconductor self-alignment as described in item 14 of the scope of patent application The method of double doping the gate, wherein the first type impurity ions and the second type impurity ions are deletion, scale or fragment ions. 16. The method for manufacturing a semiconductor self-aligned double-doped gate according to item 14 of the scope of patent application, wherein the first-type impurity ion is an n-type or a p-type ion. 17. The method for manufacturing a semiconductor self-aligned double-doped gate according to item 14 of the scope of patent application, wherein the second-type impurity ion is an η-type or a ρ-type ion. 18. The method for manufacturing a semiconductor self-aligned dual-doped gate according to item 14 of the scope of patent application, wherein the first conductive layer formed above is composed of polycrystalline silicon. 19. The method for manufacturing a semiconductor self-aligned double-doped gate according to item 14 of the scope of patent application, wherein the thickness of the first conductive layer is 1000 to 3000 angstroms. 20. The method for manufacturing a semiconductor self-aligned double-doped gate according to item 14 of the scope of the patent application, wherein the thickness of the first insulating layer doped with the second-type impurity ion is 1 0 0 0 to 5 0 0 0 Angstroms. 21. The method for manufacturing a semiconductor self-aligned double-doped gate according to item 14 of the scope of patent application, wherein the above-mentioned second insulating layer is formed of silicon nitride or non-doped silicate glass . 2 2. Manufacturing semiconductor self-aligned double doping as described in item 14 of the scope of patent application D: \ CSpatent \ 88113981. Ptc p. 17 2001.02. 22.017 Case No. 88H3981 Supplementary 6. Scope of patent application The method of the hybrid gate, wherein the thickness of the second doped ion-free insulating layer is 15000 to 3500 angstroms. 2 3. The method for manufacturing a semiconductor self-aligned double-doped gate according to item 14 of the scope of the patent application, wherein the ion implantation energy for implanting the first type of impurity ions is 5 ~ 50KeV, and the implantation dose is 1015 ~ 1016 ions / cm2 〇24. The method for manufacturing a semiconductor self-aligned double-doped gate as described in item 14 of the scope of patent application, wherein the thermal drive-in process is implemented at 80 ~ 11 0 (TC Perform at a temperature of 10 seconds to 30 minutes. D: \ CSpatent \ 88113981.ptc Page 18 2000.10.19.018