TW436982B - Method for filling up a defect gap in a semiconductor structure - Google Patents

Abstract

A method for filling up a defect gap in a semiconductor structure is provided by which defect products due to a greater calibration error shift generated in the process can be remedied. The method of the present invention comprises using a low pressure chemical vapor deposition to form a dielectric material filled into the gap, and then etching back the filling layer to maintain the surface smooth. The filling layer is deposited in a thickness of about 300 angstrom, which can fill up a gap with a width below 600 angstrom. By the present invention, the shift tolerance of a contact window can increase by 600 angstrom.

Description

Λ369 82

... The present invention relates to a method for filling a gap in a semiconductor structure. · ′ In particular, it is related to the filling of the 5-2 background of the invention. ❻In the reduction of :: the size of the guide = the design is gradually or spaced ′ Μ must take into account the circuit :: size, current process technology ′ 纟 make a suitable size of half :: characteristics. However, defects in the process often occur, such as when the mask is aligned, some development variables and so on. However, these defects may be harmed by photoresist. How to reduce or remedy defects is often a serious focus. In the case of horse manufacturing technology, the production of memory is used as an example. The volume of the cell (^ 丨 ^ is getting smaller and smaller, and the difficulty of aligning the contact window with the lower-level wire is relatively higher. It even exceeds the alignment machine. Requirements for mass production level specifications. The reason for misalignment is mainly the phenomenon of mask alignment error shift. The so-called calibration error shift is the etching position defined by the mask pattern and the actual bottom. There is an error in the preset contact position on the material. This error will cause the deviation of the expected position after etching, and may form a hole that should not exist in the manufacturing process. Take the manufacturing of a capacitor (caPacitor) as an example. A picture shows a normal

• 4369 82 V. Description of the invention (2) Part of the capacitor's junction electrode 10 is covered with two adjacent gate electrodes. The technique is to cover the landing pole with a contact with the landing pad 30, and open a 40 or landing. The error deviation of pad 30 will reach the gate at 20! A gap exists between 0, so that the conductor 50 also fills this to form a word line (word structure. Gate 10 first deposits a landing 塾 30 on a layer of dielectric with a gap, and the structure appears. .For its electrical layer 40 ', and in order to determine the contact channel from the dielectric layer 40 to the landing 后, there is a possibility that any of the lithography can leave the aforementioned contact channel, so that (hole)' As shown in the second figure, the contact channel is filled into the guide gap channel, and the line and the bit line (bi-shaped substrate on the substrate are isolated and traditionally separated. They are connected in a continuous process. But as in When the procedure occurs, there will be a landing pad 30 displayed. There are bodies 50 and the shape can be turned on (t line), each gate is 20. When the photolithography and tapeworm engraved the land pad 30 and the gated capacitor touch window, and then made the dielectric layer mask to calibrate the etched dielectric layer and dielectric layer 40. When the channel is formed into a capacitor, the pole and the capacitor The short-circuit phenomenon of Ϊ ΐ Today, the accuracy of lithography technology has not caught up with the stage of process demand, and it is possible to change the size of the semiconductor process in response to the reduction in the size of the semiconductor process! Potential; The resulting bad mouth is the goal pursued by the present invention. 5-3 Purpose and summary of the invention: Page 5 436982 V. Description of the invention (3) The small gap in the guide structure occurs. This is to compensate for the short inter-body alignment method of the present invention. The process machine is aimed at having two first multi-layers located on the same layer, and a crystalline silicon body mainly extends from the channel. Throughout the example, the chemical gas On the silicon layer. Afterwards, such as the electrode below the capacitor), the first polycrystalline silicon and the first will naturally disappear. The shortcomings of the road, the filling order can increase the accuracy is not to be filled on the substrate and (such as outside the gate electrical layer, located in the main contact channel insulation dielectric gap) is the filling layer of the deposition method 'if at this time, Due to the gap two polycrystalline stone structure, the edges are covered with polycrystalline debris, and the second poly-dielectric layer is filled with polycrystalline sand, and the covering of the layer is removed into the third by dielectric conduction first. The alignment tolerance of the fine window, the channel. This gap channel is the smoothness of the side wall of the silicon layer in the implementation system using a low pressure than the second polycrystalline channel. The present invention provides sufficient contact during the calibration error biasing process. (Top and side), one or two need to have a dielectric layer, and along the main layer to reach the first with a dielectric filling to fill it and then etch back the channel to fill the gap. The channel has been unable to contact the structure. Except that there is an insulating dielectric layer (such as a land channel and a gap crystal layer. And the second polycrystal. The filling method is covered uniformly. Covering it in order to contact the polycrystalline chip layer (electrical filling, short circuit trouble 5-4 Brief Description of the formula: a first display portion FIG basic structure of a capacitor cross-sectional view corresponding to FIG second;

4369 82 V. Description of the invention (4) The second figure shows a sectional view of the structure of the capacitor formed due to the calibration error shift; the third to ninth figures show a method of making a capacitor and filling its flaws according to the embodiment of the present invention. Method, according to the cross-sectional structure diagram shown in its manufacturing process. Representative symbols of the main parts: 10 gate 2 0 insulation layer 30 landing pad 40 dielectric layer 5 0 lower electrode layer 11 gate 21 insulation layer 2 2 spacer 31 landing pad 3 5 first photoresist 41 dielectric layer 4 5 Second photoresist 51 Lower electrode layer 55 Third photoresist

Page 7 436982 V. Description of the invention (5) 60 0 Filling layer 5-5 Detailed description of the invention: The content of the present invention can be disclosed through the following embodiments and related illustrations. The embodiment of the present invention proposes a method for filling a gap in a capacitor structure. The third to seventh figures depict the formation process of the gap and its filling steps, and the eighth and ninth circles show that the capacitor's conductor fills this gap. By contact with the underlying structure. From the second figure, it can be seen that two open electrodes 11 are located on a substrate, and the top and side walls of the gate 1 1 are covered with a dielectric layer. This dielectric layer forms a top insulating layer 21 on the gate 11 respectively. And sidewall of the gap wall 22. In general, the structure of the gate electrode 11 includes polycrystalline silicon, and the dielectric material constituting the insulating layer 21 and the spacer 22 can be made of gaseous or emulsified stone. To form Lu Su ^ 31, first, a polycrystalline silicon layer 31 is deposited on the gate π, and then the first photoresist 35 ′ is covered on the polycrystalline silicon layer 31 by lithography technology, and then the first photoresist 35 is used as a mask. The mask is etched to remove the polycrystalline silicon layer 31, which is not protected by photoresist, and the structure of the land pad 3 is exposed. Even after the completion of the landing pad 31, the ::: Ϊ on the landing pad 31 and the gate u is covered as shown in the fourth figure to strengthen the insulation between the conductors. ❿ In order to make the electric body V in the subsequent process contact with Lu Yi 31, cover the second photoresistor 45, and use the photolithography technique to suspend the 19th resist 4 5 to define a contact window (

436982 V. Description of the invention (6) The position of the contact window) further etches a contact channel onto the landing ridge. However, in the lithography process, in view of the limitation of the precision of the photomask alignment machine, the production of photoresist often shifts. The offset degree of the addition of the first photoresistor 35 and the second photoresistor 45 is within a range of 50 to 60 nm, which is tolerable by current processes. If the offset window is exceeded and the contact window cannot be properly aligned, there is still room for allowing the rice carving to proceed after the contact track on the surface of the landing pad is touched out during the etching process of the dielectric layer 41. It invades the dielectric layer 41 downward and possibly penetrates the insulating layer 21 to reach the gate electrode 1; 1, as shown in the fifth embodiment. At this time, a gap having the same channel is formed between the dielectric layer 41 and the land plate 31. If this gap is left untreated, it is very likely that the gate is turned on after the conductor is filled in the subsequent process, causing a short circuit between the two conductors. This example uses uniformity under low pressure, which can be filled in the gap of more chemical vapor in the back contact. The width of the window is 60G. The method of engraving is shown in the figure. Continued etch-back process is selective. The deposition method is used, and the film is shifted at 600 Angstroms + Ya, RIE) In order to maintain the vapor deposition process, the filling process is compared with the filling process. Therefore, it is as if the deposition tolerance is below the thickness of the filling process. 3 Filling layer 6 〇 Land pad and back fill this gap, and the method (LPCVD). The material that is not easy to have holes is preferred to the material of the electrical layer 41. The sixth figure shows that the electrical layer 41 and the landing are about 300 angstroms with a gap. After this filling, the etch-back (to the landing pad 3 1 burst capacitor contact filling method due to this sinking, makes fine silicon nitride, there is a difference between the filling layer 60 0 pad 31 this thickness way, can for example react The reason for the small gap of the channel's smooth product method is that the low-voltage and the above-mentioned film can increase the contact ion such as the seventh

Page 9 43 6 9 8 2 V. Description of the invention (7) Finally, 'as shown in the eighth figure, a conductor layer is laid on the dielectric layer 4 丨, the landing pad 3 丨 and the filling layer 60' This conductor layer is usually It is polycrystalline silicon, which is the electrode layer 51 under the capacitor. Then, the traditional photolithographic etching method is used to form the structure of the lower electrode with the third photoresist 55 as a mask, as shown in the ninth embodiment. At this time, because there is a barrier of the filling layer 60, the lower electrode 51 cannot be in contact with the gate electrode i, of course, there will be no short circuit. The addition of the filling layer increases the alignment tolerance of the contact window and the lower layer conductor in the capacitor manufacturing process mentioned above to remedy and reduce the occurrence of defective products, and further improves the yield of the product. Although the embodiment of this syouming book takes the first polycrystalline silicon layer 11, the second polycrystalline silicon layer 3}, and the third polycrystalline silicon layer 51 as examples, for the conductors of the second layer or more The error offset problem between layers can also be solved by the present invention. The above is only a preferred embodiment of the present invention, and #-丄 〇 is not intended to serve as a scope for the patent application of the present invention; any other equivalent changes or modifications made without departing from the spirit and scope of the present invention , Should be included in the patent scope below. kiss

Claims (1)

436982 VI. Scope of patent application 1. A semiconductor structure on a semiconductor substrate, at least: a plurality of separate first polycrystalline silicon, the first polycrystalline silicon is located on the substrate, each of the first polycrystalline silicon The surface and side walls of the crystalline silicon are covered with a first dielectric layer> a second polycrystalline silicon, the second polycrystalline silicon is located on the substrate and fills the gap between two adjacent first polycrystalline silicons Space, and covering part of the upper surface of the adjacent first dielectric layer; a second dielectric layer, the second dielectric layer being located on the first dielectric layer and part of the second polycrystalline silicon, There is a channel between the second dielectric layer and the second polycrystalline silicon. The channel occupies part of the first dielectric layer not covered by the second dielectric layer and the second polycrystalline silicon. A portion of the polycrystalline silicon structure is exposed; a third dielectric layer, the third dielectric layer is located on a part of the sidewall of the second dielectric layer and covers the channel uniformly; and a third polycrystalline silicon, the A third polycrystalline silicon is located on the third dielectric layer and the second polycrystalline silicon and covers part of the first polycrystalline silicon. The dielectric layer. 2. The structure of item 1 in the scope of patent application, wherein the second polycrystalline silicon and the third polycrystalline silicon are both formed by self-aligned contact (SAC). 3. The structure according to item 1 of the scope of patent application, wherein the above-mentioned second dielectric layer includes an oxide. Page 11 436982 6. Scope of patent application 4. For the structure of item 1 of the scope of patent application, the width of the above channel is about 0 to 600 Angstroms. 5. For the structure of the first scope of the patent application, wherein the third dielectric layer is deposited by low pressure chemical vapor deposition (LPCVD), the deposition thickness is about 300 angstroms, and then the reactive ion etching method is used. (RIE) Etching is completed. 6. The structure as claimed in claim 5 wherein the third dielectric layer comprises a nitride. 7. A method for manufacturing a semiconductor, comprising at least: providing a semiconductor substrate having at least two separated first polycrystalline stones; covering a first dielectric layer on a surface of the first polycrystalline silicon; and A sidewall; forming a second polycrystalline silicon layer on the first dielectric layer and the substrate; forming a first photoresist layer on the second polycrystalline silicon layer to define a second polycrystalline silicon Using the first photoresist layer as a mask, etching a part of the second polycrystalline silicon layer, so that the second polycrystalline silicon is located on the substrate, and filling a space between two adjacent first polycrystalline silicon, And covering a part of the upper surface of the adjacent first dielectric layer; forming a second dielectric layer on the first dielectric layer and the second polycrystalline silicon Page 12 436982 6. The scope of the patent application forms a second photoresist layer on the second dielectric layer to define a contact window; the second photoresist layer is used as a mask, and a part of the second dielectric is etched. An electrical layer, so that a contact channel is formed on the second polysilicon, and there is another gap channel between the second dielectric layer and the second polycrystalline silicon; forming a third dielectric layer, the third A dielectric layer is located on the second dielectric layer and the second polycrystalline silicon, and evenly covers the interstitial channel; the third dielectric layer is etched back to the second polycrystalline dream; and a third poly is formed. A crystalline silicon layer is formed on the second dielectric layer, the third dielectric layer, and the first polycrystalline silicon to form a third photoresist layer on the third polycrystalline silicon layer to define a third polycrystalline silicon layer. Crystalline silicon; and using the photoresist layer as a mask, etching a portion of the third polycrystalline silicon layer to cover the second polycrystalline silicon, the third dielectric layer, and a portion of the second dielectric layer. 8. The method according to item 7 of the patent application scope, wherein the third polycrystalline silicon is formed by self-aligned contact (SAC). 9. The method as claimed in claim 7 wherein the second dielectric layer includes an oxide. 10. The method according to item 7 of the scope of patent application, wherein the width of the above-mentioned channel is about 0 to 600 angstroms. Page 13 6. Scope of Patent Application 19. For the method of item 13 of the scope of patent application, the width of the above-mentioned channel is about 0 to 600 Angstroms. 20. The method according to item 13 of the patent application scope, wherein the above-mentioned filling layer comprises silicon nitride. Page 16 Λ369 82 VI. Patent application scope Π. For the method of patent application scope item 7, wherein the third dielectric layer is deposited by low-pressure chemical vapor deposition (LPC VD), the deposition thickness is about 3 0 0 Angstroms, and then etched back by reactive ion etching (RIE). 12. The method of claim 11 in which the above-mentioned third dielectric layer comprises a nitride. The brake pads the windows and the ground should touch to make the layers separate, and there is a meaning layer to separate the meaning: two., Fixed body, fixed with a small wall. The gate is used to cover the gap to the gap. There are few uses, divide the 塾, to the land with the upper part of the bottom, the upper layer of the base layer is engraved adjacent to the bottom side of the layer method, the body #phase, the electric square base, and the guide, the layer and the cover. The gate is covered, the gate is blocked, the gate is blocked at the bottom, and the layer is based on the resistive layer, and the photoresistor interlayer of the resistive body layer, the photoconductive top body, and the photoelectrode are two and a half. Guide the first gate; fill in the first pole, one on the second side, one for the gate to form the surface, and the shape of the layer to form a stratified shape, with 13 poles; Page 14 436982 VI. Patent application scope Etching back the filling layer until the landing pad is exposed; forming a lower electrode layer on the dielectric layer, the filling layer and the landing pad; forming a third photoresist layer on the On the lower electrode layer, it is used to define that the lower electrode j uses the photoresist layer as a mask, and a part of the lower electrode layer is etched so as to be in contact with the landing pad. 14. The method of claim 13 in which the above-mentioned dielectric layer contains silicon dioxide. 15. The method according to item 13 of the patent application range, wherein the above-mentioned insulation layer includes one of the following: silicon dioxide, silicon nitride. 16. The method according to item 13 of the scope of patent application, wherein the above-mentioned spacer comprises one of the following: silicon dioxide, silicon nitride. 17. The method according to item 13 of the patent application range, wherein the lower electrode layer is formed by a self-aligned contact (SAC). 18. For the method of claim 13 in the scope of patent application, wherein the above-mentioned filling layer is deposited by a low pressure chemical vapor deposition (PCVD) method, the deposition thickness is about 300 angstroms, and then the reactive ion etching method (R IE) is used. Etching is complete. Page 15