TW436867B - Method for decreasing reverse narrow width effect in shallow trench isolation - Google Patents

Abstract

A method for forming a semiconductor isolation device is disclosed, in which at least a first conductive type substrate having a patterned silicon nitride layer thereon is provided. Thereafter, performing a second conductive type ion implantation with a tilted angle to form a doped region in the substrate. The substrate is an isotropically etched by using the silicon nitride layer as a mask to form a trench and to form a dielectric layer in the trench.

Description

436867 V. Description of the invention (1) 5-1 Field of the invention: The present invention relates to a method for forming a semiconductor isolation element, in particular to a method for reducing the effect of reverse narrowing width in shallow trench isolation. 5-2 Background of the Invention: As semiconductor devices continue to shrink in size, isolation devices have also changed from field oxide (FOX; Field Oxidation) regions formed by LOCOS (Local Oxidation of Silicon) to shallow trench isolation ( STI; shallow trench isolation). However, the problem of reverse narrow width effect, which does not occur in the field oxygen region, now occurs with shallow trench isolation. For the structure of a shallow trench isolation element, when the channel width is reduced, the threshold voltage of the element is reduced due to the inverse narrowing width effect. The inverse narrowing width effect is the lack of depletion charge on the side of the substrate caused by the electric field at the gate edge in the corner of the shallow trench isolation. As the channel width decreases, the ratio of the parasitic charge on the sidewall to the total lack of charge increases, and the drop in the starting voltage increases. For the application of the memory cell (ce 1 1) element, in order to compensate for the decrease in the initial voltage caused by the inverse narrowing width effect when the channel width is reduced, the channel dopant concentration should be increased. For example, in a Gigabit dynamic random access memory (DRAM; dynamic random access memory), the isolation interval is less than 0.4 micrometers, and the substrate doping concentration should be

4368 6 7 V. Description of the invention (2) Reaching 10 丨 Vin3 to get a starting voltage of nearly 1.0 volt. At the same time, when the reverse connection between the storage node and the substrate leaks, the dopant concentration of the substrate increases as it increases. Next, the generation of the inverse narrow-width effect and its effect in the memory are described by using Figure 2. As shown in the first figure, it is a schematic structural diagram of a conventional isolation element. On a substrate 100, a field oxygen region 12 is formed by a conventional area oxidation (Locos; Local Oxidation of Silicon) method. On both sides of the field oxygen region 1 20 are two semiconductor elements in the integrated circuit, such as a metal oxide semiconductor field effect transistor (^ 105? £ 1 '; 11 ^ 1 & 1-〇} ^ (^-semiconductor field effect transistor In order to improve the isolation between components, a general process will form a channel barrier layer 11 0 ′ under the field oxygen region i 2 〇, also known as the field implant (fie 1 dimp 1 ant) region. In the N channel In metal oxide semiconductors, the implanted dopant is usually a boron. The dopant in the field implanted region 110 is subjected to a subsequent heating process or tempering. A portion will diffuse to both sides of the field oxygen region 1 20, such as corner 1 11 in the second figure. The dopants diffused to both sides of the field oxygen region 1 2 0 will produce a general metal oxide semiconductor transistor. The narrow width effect is shown in the third figure. The third figure is the relationship between the starting voltage and the channel length. It can be seen from the figure that when the channel length decreases, the starting voltage is relatively low. increase.

4368 6 7 ——_________ V. Description of the Invention (3) Today's isolation components, as shown in the fourth figure, mostly use shallow trenches ft {hal 雕 (STI; Shal low trench isolation) 122 to replace traditional fields Oxygen zone. Similarly, in order to increase the isolation capability, a channel stop layer 112 is formed under the shallow trench isolation 122. However, 'due to the geometry of the shallow trench isolation 1 2 2, the inclusions in the channel barrier layer 丨 2 are not easily diffused to the corner 1 of the active area during subsequent tempering, and the concentration of the corners in the active area becomes lighter , As shown in the fifth figure, the reverse narr width effect (reverse narr0w width effect) can be seen from the drawing that when the channel length is reduced, the starting voltage is also relatively reduced. When the size of the body circuit element is reduced, the threshold voltage is reduced, so that the transistor is lost: the function of the gate and the gate m are reversed, and the narrow width effect is reversed. The action of the previous ion implantation to increase the concentration in the pull region increases the starting voltage in the active region. As two = so *, it is a traditional dynamic random access memory side structure = is formed in: ^ isolation 122 in a substrate 100, and field implantation = is formed under shallow trench isolation 122. The ion implantation area ιΐ4 is formed on the substrate ιο〇 clothing surface, which is used to increase the starting voltage of the 7G pieces of snow and sun limbs. A thin oxide layer 120, a tungsten oxide layer U2, and a oxynitride layer 142 are sequentially formed on the substrate surface 100 ', and a lower electrode node 134 forming a capacitor is formed by the upper mouse. The faint layer 144 generates leakage current at the storage node because the ion implantation region 114 enhances the active area.

Page 6 436867 V. Description of the invention (4) -3 Purpose and summary of the invention In the above inventor's view, many disadvantages caused by the traditional method of forming a shallow trench isolation element are described. The present invention mainly provides a method for forming a shallow trench. In the method of isolation, the corner concentration around the trench isolation can be increased to compensate for the charge emptying effect to reduce the reverse narrow width effect without increasing the substrate concentration. For the unit cell transistor, the initial starting voltage M can be kept high, and the substrate wave length can be kept low to reduce the problem of increased junction leakage current of the storage node. The isolation process includes providing a layer of nitride to form a shallow trench on the photoresist layer to isolate the critical ion implant layer of the present invention to form a shallow trench isolation in the non-drain of the mask. The present invention provides a method of width effect. The electrical substrate forms a separate pattern on the dream layer and a silicon layer. An implantation area is made at an angle of removal. In order to form a trench and fill it with the purpose described above, the 'lower inversion narrow' has a first silicon-conducting layer and a shallow trench isolation pattern defined in nitriding is transferred to the nitride bond step to tilt Into and isotropically etch the substrate dielectric layer in the substrate shape, as well as in the device. A method for forming a shallow trench. The method of the present invention also deposits a photoresist layer on the substrate. Next, after the photoresist layer on the photoresist layer, a second conductive layer is formed, and then a silicon nitride channel is formed. Finally, the silicon oxide layer is formed in the trench to form a 5-4 diagram to briefly explain 436867. V. Description of the invention (5) The above objects and advantages of the present invention will be described in detail with the following examples and diagrams, where: The first figure shows the structure of a field emulsion isolation region formed by a regional oxidation method using conventional techniques, where a channel barrier layer is formed under the field oxygen region. The second figure shows the use of conventional techniques to mix the channel barrier layer after tempering. Schematic diagram of debris gathering to the corner of the active area; the third figure is the relationship between the starting voltage of the narrow width effect and the channel length (the fourth figure is the intent of the traditional technique when forming shallow trench isolation) There is a channel barrier layer under the shallow trench isolation. The fifth figure is the relationship between the starting voltage of the inverse narrow width effect and the channel length. The sixth figure is the use of traditional techniques to form a dynamic random access record ~ Zhao Jing cell Fig. 7A through Fig. 7F are structural diagrams of each step when a trench isolation element is formed in accordance with the technology disclosed in the present invention; and

436867 V. Description of the invention (6) The eighth figure is a schematic diagram of the structure when a dynamic random access memory cell is formed according to the technology disclosed in the present invention. Main symbols: 10 substrate 12 ion implantation area 20 silicon oxide layer 30 polycrystalline silicon layer 32 metal silicide layer 34 storage node 40 silicon nitride layer 42 silicon oxynitride layer 44 silicon nitride layer 50 photoresist layer 60 ion Implant 100 substrate 110 channel barrier 111 corner area 114 corner area 120 field oxygen area 122 shallow trench isolation 130 polycrystalline silicon layer 132 metal oxide 134 storage node

4368 6 7 V. Description of the invention (7) 142 Silicon oxynitride layer 144 Silicon nitride layer 5-5 Detailed description of the invention: The semiconductor element of the present invention can be applied to a wider range, and can be made of different semiconductor materials. Because the current major semiconductor component is fabricated on a silicon substrate ', the following description will discuss embodiments of the present invention using silicon as a substrate on a semiconductor component, and the most common application is on a silicon substrate. However, the present invention can also be applied to substrates of other materials, such as gallium arsenide and germanium. Therefore, the application of the present invention is not limited to components made of broken semiconductor materials' but includes components made of other semiconductor materials. Furthermore, the embodiment shown in the present invention is a semiconductor device, but the illustration of the present invention is not intended to limit the scope of the present invention. Even the example of the example is the use of an insulated gate control structure, but there should be such a recognition that the insulated poles can be replaced with other structures. In this way, this is not intended to limit the semiconductor split of the present invention to the illustrated structure. These devices include the use and application of the preferred embodiment of the present invention shown below. Furthermore, different parts of the semiconductor device are not drawn according to the ruler. Some scales have been exaggerated compared to other related scales to provide clarity

4368 6 7 V. Description of invention description (8) and understanding of the invention. Since the description of the preferred embodiment of the semiconductor device of the present invention includes a specific P-type region and an N-type region, it should be clearly understood that the conductivity of different regions in the semiconductor element is interchangeable. Enhancement mode and lackion mode can be interchanged in the same way. Furthermore, although the embodiment drawn here is shown in two dimensions with width and depth at different stages, it should be clearly understood that the displayed area is only the three-dimensional unit cell (ce 1 1) of the wafer. In this case, the wafer may contain a plurality of unit cells β arranged in a three-dimensional space. In contrast, when the actual component is manufactured, the area shown is three-dimensional in length, width, and height. The present invention mainly finds a method for forming an isolation element, in which the concentration of shallow trench isolation corners is increased to compensate for the lack of charge here, and ^ reduces the effect of inverse narrow width without increasing the substrate concentration. In this way, a higher starting voltage and a lower substrate concentration can be used to eliminate the problem of increased storage and leakage current. "A good example of an isolating element that has the effect of reducing the visibility of people. The example is a household furnace. The former technology is not available, and it is implemented in this way." Baixian, k provides a substrate and defines an active area. A silicon nitride layer and a photoresist layer are sequentially formed on the substrate, and the pattern of the trench isolation area is transferred to the photoresist layer and the nitrogen hafnium layer = trench trench resistance. Layer is removed. Then, the key step of the present invention is to 'make light ^ monthly

4368 6 7 V. Description of the invention (9) Ion implantation. After that, the silicon nitride layer is used as the inverse. Then, the same as the traditional manufacturing process, the process described above to form the trench according to 2 = material will be closed the first half of the Γ component. According to the technique disclosed in the present invention, the steps of forming the I-slot isolation element based on the structure shown in FIG. 7F are shown in FIG. 7A, as shown in FIG. 7A, a substrate ln and a photoresist layer 50. The nitrogen-cutting layer 40 is mainly == chemical hair layer 4. Mask, ^ with traditional chemical vapor deposition: = = = = 疋 The purpose is to transfer the pattern of the isolation element to the nitride breakdown layer 40. In the example, the thickness of the nitrogen-cut layer 40 is about 18 U = the thickness is about 5 000 to 9,000 Angstroms. The first layer is the barrier layer two; the lithography technology transfers the pattern to light and then Γ: Γ the second pattern is a shallow trench isolated UI wood drink. As shown in Figure 7C, the photoresist is used as a photoresistor. Reactlve iGn uses a 2 way to remove the photoresist layer 5 ο. Is it a traditional tilt? Key steps, as shown in Figure 70 It is shown that ion implantation 60 at-= degree forms a separation on the substrate 10, and the conductivity of the implanted ions is the same as that of the substrate ^ silicon substrate, and the right p is thin &

The ions implanted in the court can be BF2 or β. If it is N, the second one is 436867. V. Description of the invention (ίο) silicon substrate, the ions implanted here can be p or As. In this embodiment, the angle of inclination is about 7 to 45 degrees. The energy of the implanted ions is about 5 to 30 kilo-electron volts, and the concentration of the implanted ions is about 0.001 to 2x3. Since the ion implantation 60 is inclined at an angle, the ion concentration at the corner of the substrate 10 'under the silicon nitride layer 40 is increased; that is, the element in the active region has a higher initial voltage. After 'is the same as the conventional shallow trench isolation process. As shown in FIG. 7E, the silicon nitride layer 40 is used as a mask, and a portion of the substrate 10 is etched by traditional anisotropical ly to form a trench β. The etching method may be a reactive method. Ion etching (r I Ε). As shown in FIG. 7F, the step of performing linear oxidation forms an oxide layer 20 in the trench. The formation method is to put the whole wafer into a furnace tube, and the heating temperature is about 80 to 120 ° C, and the time is about 10 to 60 minutes. In this embodiment, the thickness of the oxide layer 20 is about 100 to 300 angstroms. The eighth figure is a schematic diagram of the structure when a dynamic random access memory cell is formed according to the technology disclosed in the present invention. As shown in the eighth figure, a silicon oxide layer 22 is first formed by conventional chemical vapor deposition in the formed trench, and then the nitrided silicon layer 40 used as a mask is removed. Removal can be by immersing the wafer in a phosphoric acid bath. Next, a polycrystalline silicon layer 30, a metal silicide layer 32 ', a silicon oxynitride layer 42, and a nitride nitride layer 44' are sequentially formed thereon. The silicon oxynitride layer 42 is used as an anti-reflection layer (an ti-

P. 13 s 436867 states (11) '' ref lect10n). After that, it is etched—part of the polycrystalline silicon layer 30, the metal silicide layer 32, the silicon oxynitride layer 42 and the silicon nitride layer ”, and the substrate to form the storage node 34. In this embodiment, because The concentration of the substrate is not increased, and no joint leakage current of the storage node will be generated. According to the above description, the present invention finds a method to form an isolation element, which can not only increase the concentration of the shallow trench isolation corners to Compensate for charge voids and discharges to reduce the effect of reversed load width without increasing the substrate concentration. For the cell transistor, the initial voltage can be kept high, and the substrate thickness can be kept low to reduce the junction leakage of the storage node. The problem of current increase. — The above description is only a preferred embodiment of the present invention, and is not intended to be limited to the scope of the patent application of the present invention; all other equivalent changes made without departing from the god of f disclosed in the present invention Or modification 'should be included in the scope of the patent application described below.

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Claims (1)

4368 6 7 VI. Scope of patent application 1. A method for forming a semiconductor isolation element, the method at least comprises: providing a substrate having a third conductivity, and having a pattern-transferred silicon nitride on the substrate Layer; performing an ion implantation with a second conductivity at an oblique angle and forming an implanted region in the substrate; using the silicon nitride layer as a mask to anisotropically etch the substrate 'to form A trench; and forming a dielectric layer in the trench. 2 _ The method according to item 1 of the patent application range, wherein the above-mentioned inclined angle is about 7 to 45 degrees. Item 3, if the scope of patent application i includes silicon oxide. 4. The method of claim 1 in the scope of the patent application, wherein the method for forming the patterned silicon nitride layer at least includes: depositing a silicon nitride layer on the substrate; and forming a silicon nitride layer on the silicon nitride layer. A photoresist layer; defining a shallow trench isolation pattern on the far photoresist layer; and transferring the shallow trench isolation pattern on the photoresist layer to the nitrogen-cut layer; removing the photoresist layer. Page 15: 436867 VI. Application for Patent Scope 5. The method of the scope of application for patent No. 4 wherein the method for transferring a pattern to the silicon nitride layer at least includes etching the silicon nitride with the photoresist layer as a mask Floor. 6. According to the method of claim 1 in the scope of patent application, the trench is further filled with a silicon oxide layer to form a shallow trench isolation element. 7. A method of forming a shallow trench isolation element, the method at least comprising: providing a substrate having a first conductivity, and having a pattern-transferred silicon nitride layer on the substrate; tilting at an angle Performing an ion implantation with a second conductivity, and forming an implantation region in the substrate; using the silicon nitride layer as a mask to anisotropically etch the substrate to form a trench; in the trench A dielectric layer is formed therein; and a silicon oxide layer is filled in the trench to form a shallow trench isolation element. 8. The method of claim 7 in the scope of patent application, wherein the above-mentioned inclined angle is about 7 to 45 degrees. 9. The method according to item 7 of the patent application, wherein the dielectric layer includes at least an oxide dream. 10. The method of claim 7 in the scope of patent application, wherein the above-mentioned pattern transfer is formed Page 16 4368 6 7 6. The method for applying a patented silicon nitride layer at least includes: depositing a nitrided hair layer on the substrate; forming a photoresist layer on the nitrided dream layer; A shallow trench isolation pattern is defined on the photoresist layer; the shallow trench isolation pattern on the photoresist layer is transferred to the silicon nitride layer; and the photoresist layer is removed. 11. The method of claim 10, wherein the method for transferring a pattern to the silicon nitride layer at least includes etching the nitrided oxide layer with the photoresist layer as a mask. A method for reducing the reverse narrow width effect in the process of forming a shallow trench isolation, the method at least comprises: providing a substrate having a first conductivity; depositing a nitrided layer on the concrete substrate; Forming a photoresist layer on the silicon nitride layer; defining a shallow trench isolation pattern on the photoresist layer: transferring the shallow trench isolation pattern on the photoresist layer to the nitride; The photoresist layer; conductive ion implantation, tilted at an angle to form an implanted area with a sub-substrate on the side substrate, trench: "the silicon nitride layer is a mask to etch the substrate anisotropically, To form Page 17; 436867 6. Scope of patent application A dielectric layer is formed in the trench; and a silicon oxide layer is filled in the trench to form a shallow trench isolation element. 13. The method of claim 12 in the scope of patent application, wherein the above-mentioned inclined angle is about 7 to 45 degrees. 14. The method according to item 12 of the patent application scope, wherein the dielectric layer mentioned above contains at least stone oxide. 15. The method of claim 12 in the scope of patent application, wherein the method for transferring a case to the silicon nitride layer at least includes etching the nitrided oxide layer with the photoresist layer as a mask. Page 18