4367 0 4 A7 B7 五、發明說明（/) 發明背景： 技術領域： (請先閲讀背面之注意事項再填寫本頁) 本發明是一種有關在傳輸裝置與接收裝置間，利用單一 傳輸線可同時有多位元數位資料傳輸的系統與電路。特別是 關於在單一傳輸媒介上利用電流模式的多位元傳送與接收 裝置。 相關技藝說明： 傳統上，資料匯流排(Data Bus)經常被使用在兩個或多 個訊號平行傳遞的需求上。而傳遞的距離可能是：1公釐到 20公釐的半導體晶片中的鋁金屬線上；1公尺長的印刷電路 板上的銅箔線路；或甚至數公尺長的電氣傳輸線。通常資料 匯流排需要兩條線路來傳遞不同的訊號以改善傳遞速度。 經濟部智慧財產居員工消費合作社印製 資料匯流排的重要參數或有價値的特徵包括：資料傳輸 的頻寬(每秒每條線可傳遞的位元數）；電源消耗量(特別是指 對資料匯流排的電容充放電時所消耗的交流電源量)；以及， 相對於傳輸距離的長度，每一位元所佔的晶片面積。有相當 多的技術文章討論到在0.35微米的半導體製程技術中，對於 主宰晶片效能的因素中，資料匯流排的傳輸速度比互補金氧 半導體(CMOS)元件閘速度(Gate speed)更重要。 原因是晶片的物理尺寸加大而鋁金屬線的線寬變窄，對 傳輸線的速度有相當大的影響，即傳輸線的長度增加而寬度 減少使得總電阻値增加。另一方面，傳輸線間的距離越窄更 使得傳輸線的電容値增加。 由於電阻値、電容値的增加，導致影響時間延遲的電阻 本紙張尺度適用中國國家標準（CNS)A4規格（2】0 X 297公釐) 4367 0 4 五、發明說明（夕） -電容延遲（Resistive-Capacitance Delay)參數變大，而降低傳 輸速度。在一些技術文獻中提示了不同的資料匯流排結構可 以有較小的電壓變化而且有較少的電阻-電容延遲。 一種已知減少線路延遲的技術是利用電流模式而非電 壓模式來傳遞資料，在這種方法中，資料匯流排上的電壓在 訊號傳遞時不會有劇烈的變化，但電流是被調變的。因爲電 壓沒有改變，所以電阻-電容延遲在傳輸時變不是影響傳輸 時間的因素。此時，影響資料匯流排傳輸速度的是傳輸媒介 物質本身的光延遲(light delay)速度’這種延遲遠較電阻-電容 延遲來的小 ΰ Mode Techniques for High Speed VLSI Circuits with Application to Current Sense Amplifier for CMOS SRAM's" Seevinck et al., IEEE journal of Solid State Circuits，Vol. 26, No. 4 April 1991，pp. 525-535 這篇文章4367 0 4 A7 B7 V. Description of the invention (/) Background of the invention: Technical field: (Please read the notes on the back before filling out this page) The present invention relates to the use of a single transmission line between a transmitting device and a receiving device. Multi-bit digital data transmission system and circuit. In particular, it relates to a multi-bit transmitting and receiving apparatus using a current mode on a single transmission medium. Relevant technical description: Traditionally, data buses are often used for the requirement of two or more signals being transmitted in parallel. The transmission distance may be: aluminum metal wires in semiconductor wafers of 1 mm to 20 mm; copper foil lines on printed circuit boards of 1 meter long; or even electrical transmission lines of several meters long. The data bus usually needs two lines to transmit different signals to improve the transmission speed. Important parameters or valuable characteristics of the printed data buses of the Intellectual Property Department's consumer cooperatives in the Ministry of Economic Affairs include: the bandwidth of data transmission (the number of bits that can be transmitted per line per second); the power consumption (especially the The amount of AC power consumed when the capacitor of the data bus is charged and discharged); and, relative to the length of the transmission distance, the chip area occupied by each bit. There are quite a few technical articles discussing that in the 0.35 micron semiconductor process technology, the data bus's transmission speed is more important than the complementary metal-oxide-semiconductor (CMOS) device gate speed in terms of dominating chip performance. The reason is that the physical size of the wafer is increased and the line width of the aluminum metal line is narrowed, which has a considerable impact on the speed of the transmission line, that is, the increase in the length of the transmission line and the decrease in the width make the total resistance 値 increase. On the other hand, the narrower the distance between the transmission lines, the more the capacitance 値 of the transmission lines increases. Due to the increase of resistance 値 and capacitance 导致, the resistance that affects the time delay. This paper size applies the Chinese National Standard (CNS) A4 specification (2) 0 X 297 mm. 4367 0 4 5. Description of the invention (Even)-Capacitive delay ( Resistive-Capacitance Delay) parameter becomes larger, which reduces the transmission speed. It is suggested in some technical literatures that different data bus structures can have smaller voltage changes and less resistance-capacitance delays. A known technique for reducing line delay is to use current mode instead of voltage mode to transfer data. In this method, the voltage on the data bus does not change drastically during signal transmission, but the current is modulated. . Because the voltage does not change, the change in resistance-capacitance delay during transmission is not a factor that affects the transmission time. At this time, what affects the data bus transmission speed is the light delay speed of the material of the transmission medium. This delay is much smaller than the resistance-capacitance delay. Mode Techniques for High Speed VLSI Circuits with Application to Current Sense Amplifier for CMOS SRAM's " Seevinck et al., IEEE journal of Solid State Circuits, Vol. 26, No. 4 April 1991, pp. 525-535 This article
經濟部智慧財產局員工消費合作社印M —:-------->t--------訂· <諳先閱讀背面之注意事項再填寫本頁) 中，提出一種電流傳遞延遲的簡化模型。一個利用此種簡化 模型的應用實例則在下列文章中被提出，”A 1.6Gb/s Data Rate 1Gb Synchronous DRAM with Hierarchical Square Shaped Memory Block and Distributed Bank Architecture" Nitta et al., Proceedings of the International Solid State Circuits Conference，SP23.5, p302, 1996。 在1’ 1 Gb/s Current-Mode Bidirectional I/O Buffer”，Sim et al., Symposium on VLSI Circuit Digest of Technical Papers, IEEE, 1997,的文章中，揭露了一種雙向電流傳輸模式的驅 動及接收裝置。這種電路裝置是具有低電源消耗的雙向緩充 器。應用減少傳輸線上的電壓變化及降低緩充器的節點阻 3 本紙張尺度適用中國國家標準（CNS) A4規格（210 X 297公笼） 4 3 6704 五 經濟部智慧財產局員工消費合作社印製 B7 發明說明（/) 抗，以獲取高頻寬。在輸入及輸出電路上使用電流模式電路 來傳遞數位資料。 在美國專利 U.S.Patent 5,355,391 (Hororwitz et al.)說明 書中，揭露了一種高速的資料匯流排系統。在該資料匯流排 系統中，主控裝置(MASTER DEVICE)位於傳輸系統的中央 交點上，其餘從屬控制裝置(SLAVE DEVICE)則置於各傳輸 線的另一端上。互補金氧半導體(CMOS)電流模式驅動器及 接收器被應用在此系統中，使得傳輸線上有較小的電壓波 動。 在美國專利 U.S.Patent 4,481，625 (Roberts et al.)說明書 中，掲露了一種應用於非常大的電腦系統中的各個功能單元 間的高速資料傳輸的資料匯流排裝置。在該些功能單元間的 傳輸模式是利用電流模式，以克服通過一些主動裝置時因傳 輸線阻抗的問題而造成的信號不連續問題。這樣的作法可以 防止高速傳輸時信號傳遞轉向(tum-around)的問題發生。 在美國專利 U.S.Patent 5,45〇,026 (Morano)說明書中， 揭露了一種差動電流模式資料匯流排驅動器，該驅動器連接 輸入數位信號到通常被偏壓到某一邏輯狀態之資料匯流 排，該資料匯流排驅動器將藉由在傳輸導線一端連接一電流 供應裝置，而另一端連接電流吸收裝置來達成對相反邏輯信 號的反應。資料匯流排的電位會調整成另一種準位以表示相 反的邐輯狀態。如果輸入信號是正常偏壓的邏輯狀態’驅動 器將不連接電流供應裝置與電流吸收裝置，而將這兩者相互 連接，於是資料匯流排的電位仍維持第一次偏壓準位。 (請先蘭讀背面之注意事項再填寫本K > ---- 訂*-------- 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） 4367 0 4 A7 __ B7___ 五、發明說明（#) 在美國專利 U.S.Patent 5,254,883 (Hororwitz et al.)說明 書中，揭露了一種電流模式驅動器，以傳輸數位信號到資料 匯流排。該電流模式驅動器具有電晶體電路來控制資料匯流 排上的電流以及一個可變動準位電路以調整資料匯流排上 的電流準位。使用者也因此可以調整資料匯流排上的電流準 位。 使用多信號準位(multiple signal levels)的方式代表數位 資料的觀念是早已被揭露的技藝。在前述西蒙等(Sim et aL) 的文章中有一利用多信號準位的方式同時傳輸兩個數位資 料位元的裝置。 在文獻”A 3.3V 128Mb Multilevel NAND Flash Memory for Mass Storage Application”，Jung et al. Proceedings International Solid States Circuit Conference, 1996, paper TIP2.1，這篇文章中描述一種快閃記憶體使用四個分離的電 壓準位以表示存於記憶體單元的兩個位元的資料。周邊的電 路會將數位資料分成適當的電壓準位而存入記憶体單元。另 一方面，周邊電路感測記憶體單元上的電位而將其資料讀 出。 經濟部智慧財產局員工消費合作社印製 ---：----------' S--------訂， (請先閱讀背面之it意事項再填寫本頁) 在文獻”A 98mm 3.3V 64Mb Flash Memory with FN-NOR Type 4 Level Cell" , Ohkawa et al. Proceedings International Solid States Circuit Conference, 1996, paper TIP2.3,這篇文章中討論一種64Mb快閃記憶体，該快閃記憶 体單元使用4種電壓準位來儲存兩位元的數位資料。Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs M —: -------- > t -------- Order < 谙 Read the precautions on the back before filling in this page) A simplified model of current transfer delay. An application example using this simplified model is proposed in the following article, "A 1.6Gb / s Data Rate 1Gb Synchronous DRAM with Hierarchical Square Shaped Memory Block and Distributed Bank Architecture " Nitta et al., Proceedings of the International Solid State Circuits Conference, SP23.5, p302, 1996. In 1 '1 Gb / s Current-Mode Bidirectional I / O Buffer ", Sim et al., Symposium on VLSI Circuit Digest of Technical Papers, IEEE, 1997, A driving and receiving device of a bidirectional current transmission mode is disclosed. This circuit arrangement is a two-way slow charger with low power consumption. Application to reduce the voltage change on the transmission line and reduce the node resistance of the slow charger 3 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 male cage) 4 3 6704 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs DESCRIPTION OF THE INVENTION (/) to obtain high frequency bandwidth. Current mode circuits are used on the input and output circuits to transfer digital data. A high-speed data bus system is disclosed in U.S. Patent 5,355,391 (Hororwitz et al.) Specification. In this data bus system, the master control device (MASTER DEVICE) is located at the central intersection of the transmission system, and the remaining slave control devices (SLAVE DEVICE) are placed at the other end of each transmission line. Complementary metal-oxide-semiconductor (CMOS) current-mode drivers and receivers are used in this system, resulting in less voltage fluctuations on the transmission line. In U.S. Patent 4,481,625 (Roberts et al.) Specification, a data bus device for high-speed data transmission between various functional units in a very large computer system is disclosed. The transmission mode between these functional units is to use the current mode to overcome the signal discontinuity caused by the transmission line impedance problem when passing through some active devices. This method can prevent the problem of signal transmission tum-around during high-speed transmission. In US Patent 5,45,026 (Morano) specification, a differential current mode data bus driver is disclosed. The driver connects input digital signals to a data bus that is normally biased to a certain logic state. The data bus driver will respond to the opposite logic signal by connecting a current supply device at one end of the transmission wire and a current sink device at the other end. The potential of the data bus will be adjusted to another level to indicate the opposite editing status. If the input signal is a logic state of normal bias, the driver will not connect the current supply device and the current sink device, but will connect the two with each other, so the potential of the data bus will maintain the first bias level. (Please read the notes on the reverse side before filling out this K > ---- Order * -------- This paper size applies to China National Standard (CNS) A4 (210 x 297 mm) 4367 0 4 A7 __ B7___ V. Description of the invention (#) In the specification of US Patent 5,254,883 (Hororwitz et al.), A current mode driver is disclosed to transmit digital signals to the data bus. The current mode driver has a transistor circuit To control the current on the data bus and a variable level circuit to adjust the current level on the data bus. The user can also adjust the current level on the data bus. Using multiple signal levels The concept of) means representing digital data is a technology that has already been revealed. In the aforementioned article by Simon et al (Sim et aL), there is a device that uses multiple signal levels to simultaneously transmit two digital data bits. In the document "A 3.3V 128Mb Multilevel NAND Flash Memory for Mass Storage Application ", Jung et al. Proceedings International Solid States Circuit Conference, 1996, paper TIP2.1, this article The article describes a flash memory that uses four separate voltage levels to represent the two bits of data stored in the memory cell. The surrounding circuit divides the digital data into the appropriate voltage level and stores it in the memory cell. On the other hand, the peripheral circuit senses the potential on the memory unit and reads its data. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs ---: ---------- 'S-- ------ Order, (Please read the notice on the back before filling this page) In the literature "A 98mm 3.3V 64Mb Flash Memory with FN-NOR Type 4 Level Cell ", Ohkawa et al. Proceedings International Solid States Circuit Conference, 1996, paper TIP2.3, this article discusses a 64Mb flash memory that uses four voltage levels to store two-bit digital data.
在文獻A 3·4Μ byte/Sec. Programming 3-Level NAND _____5____ 本紙張尺度適用中國國家標準（CNS)A4規格（21〇χ 297公釐） 4 3 6"7 0 4 A7 B7 五、發明說明（i )In Document A 3 · 4M byte / Sec. Programming 3-Level NAND _____5____ This paper size applies the Chinese National Standard (CNS) A4 specification (21〇χ 297 mm) 4 3 6 " 7 0 4 A7 B7 V. Description of the invention ( i)
Flash Memory Saving 40 % Die Size Per Bit" , Tanaka et al. Symposium of VLSI Circuits, Digest of Technical Papers,1997, pp 65-66,這篇文章中提及使用三種臨限(threshold)電壓準位 來對應於數位資料〇、1及2，因此可以在一對記憶體單元上 儲存三位元的數位資料。 發明槪述： 本發明的主要目的是提供一種數位通訊系統，該系統可 以在單一傳輸媒介上輸送及接收多個位元的數位資料。 本發明的另一目的是提出一種使用單一電流模式代表 多位元數位資訊的傳輸方式，該方式可以在單一傳輸媒介上 傳輸多個位元的數位資料。 本發明的另一目的是提出一種可以在單一傳輸媒介上 接收多個位元數位資料的方式。 本發明的另一目的是提出一種在傳輸媒介上的多位元 電流模式驅動裝置，該多位元電流模式驅動裝置可以將多位 元的數位資料轉變成電流模式的電流訊號。 本發明的另一目的是提出一種在傳輸媒介上的多位元 電流模式接收裝置，該多位元電流模式接收裝置可以將電流 模式的單一電流訊號轉換成多位元的數位資料訊號。 爲了達成上述的各種目的及其他的許多優點，在此描述 一種電流模式的雙位元數據資料通訊系統。首先將兩位元的 數位資料轉換成電流模式訊號，該電流模式訊號包括一第一 正電流、一第一正電流、一第一負電流及一第二負電流。該 電流模式訊號將於一雙位元的電流模式資料匯流排上傳 ------------ - I - I (請先閱讀背面之注意事項再填寫本頁) 訂‘ 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 436704 ^_ 經濟部智慧財產局員工消費合作社印製 A7 E7 發明說明（t) 送。該電流模式的雙位元數據資料通訊系統更包括一接收裝 置與電流模式資料匯流排連接，以接收資料匯流排上的電流 訊號，並將該電流訊號轉換成兩位元的未修正數位資料。該 接收裝置的輸出端連接至一資料取出電路，該資料取出電路 可以將未修正的兩位元數位資料轉變爲正常的兩位元數位 訊號。 圖示的簡要說明： 圖一是用來說明本發明一種多位元電流模式資料匯流排的 傳送及接收架構方塊圖。 圖二是用來說明有關本發明一種多位元電流模式資料匯流 排的傳送裝置的實施例電路圖。 圖三是用來說明有關本發明一種多位元電流模式資料匯流 排的接收裝置的實施例電路圖。 圖四是用來說明如何將多位元資料的電流模式訊號由接收 裝置取出的示意圖及方程式。 圖五是本發明一種多位元電流模式資料匯流排在雙向傳輸 時的示意方塊圖。 圖六是有關本發明中代表多位元數位資料訊號的每一邏輯 準位的電流模式訊號圖。 發明的詳細說明： 請參考圖一，圖一是用來解釋本發明有關多位元電流模 式數位傳輸方式的一般架構。在這個例子中，有兩個位元 blTX及b2TX在多位元傳送裝置CMTX中被結合成電流訊 號。 ---1---.------!.--------訂· (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度通用中國國家標準（CNS)A4規格（210 x 297公釐） 436704 B7 五、發明說明（7 ) 圖二則是一個多位元傳送裝置的實施例電路圖。在圖二 的傳送裝置實施例電路圖中，N型金氧半導體(MOS)電晶體 Ml及P型電晶體M2的閘極連接至傳送裝置的第一位元資 料輸入端blTX，N型電晶體Ml的汲極連接至第一高電壓 源Vccl，而P型電晶體M2的汲極連接至第一低電壓源 Vss：l。N型電晶體Ml的源極及P型電晶體M2的源極一起 連接至傳送裝置的輸出端。由圖一中可以知道傳送裝置的輸 出端連接至電流模式資料匯流排CMB上。 N型電晶體M3及P型電晶體M6的閘極連接至傳送裝 置的第二位元資料輸入端b2TX。N型電晶體M3的汲極連 接至第一高電壓源Vccl，而P型電晶體M6的汲極連接至第 一低電壓源Vssl。 N型電晶體M4及P型電晶體M5的閘極連接至傳送裝 置的第一位元資料輸入端MTX。N型電晶體M3的源極連 接至N型電晶體M4的汲極。P型電晶體M6的源極連接至 P型電晶體M5的汲極。 N型電晶體M4的源極及P型電晶體M6的源極一起連 接至傳送裝置的輸出端。 在圖二中可以看出，電流模式訊號CMS是電流IV Π、 Γ2及Γ2等的和。在表一中顯示了電流模式訊號CMS與兩個 輸入資料位元的關係。Flash Memory Saving 40% Die Size Per Bit ", Tanaka et al. Symposium of VLSI Circuits, Digest of Technical Papers, 1997, pp 65-66, this article mentions the use of three threshold voltage levels to correspond Since the digital data is 0, 1, and 2, three-bit digital data can be stored on a pair of memory cells. Summary of the Invention: The main object of the present invention is to provide a digital communication system, which can transmit and receive multiple bits of digital data on a single transmission medium. Another object of the present invention is to propose a transmission method that uses a single current mode to represent multi-bit digital information, which can transmit multiple-bit digital data on a single transmission medium. Another object of the present invention is to propose a method that can receive multiple bit digital data on a single transmission medium. Another object of the present invention is to provide a multi-bit current-mode driving device on a transmission medium. The multi-bit current-mode driving device can convert multi-bit digital data into a current-mode current signal. Another object of the present invention is to provide a multi-bit current mode receiving device on a transmission medium. The multi-bit current mode receiving device can convert a single current signal in a current mode into a multi-bit digital data signal. In order to achieve the above-mentioned various objectives and many other advantages, a two-bit data communication system of current mode is described herein. First, the two-bit digital data is converted into a current mode signal. The current mode signal includes a first positive current, a first positive current, a first negative current, and a second negative current. The current mode signal will be uploaded to a two-bit current mode data bus -------------I-I (Please read the precautions on the back before filling this page) Order 'Ministry of Economy Printed on the paper of the Intellectual Property Bureau employee consumer cooperatives. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 436704 ^ _ A7 E7 printed by the Intellectual Property Bureau employee consumer cooperatives of the Ministry of Economic Affairs. The current-mode dual-bit data communication system further includes a receiving device connected to the current-mode data bus to receive the current signal on the data bus and convert the current signal into two-bit uncorrected digital data. The output end of the receiving device is connected to a data fetching circuit, which can transform the uncorrected two-bit digital data into a normal two-bit digital signal. Brief description of the figure: Figure 1 is a block diagram illustrating a transmission and reception architecture of a multi-bit current mode data bus of the present invention. FIG. 2 is a circuit diagram illustrating an embodiment of a transmission device for a multi-bit current mode data bus according to the present invention. FIG. 3 is a circuit diagram illustrating an embodiment of a receiving device for a multi-bit current mode data bus according to the present invention. Fig. 4 is a schematic diagram and an equation for explaining how to extract a current mode signal of multi-bit data from a receiving device. FIG. 5 is a schematic block diagram of a multi-bit current mode data bus according to the present invention during bidirectional transmission. FIG. 6 is a current mode signal diagram for each logic level representing a multi-bit digital data signal in the present invention. Detailed description of the invention: Please refer to FIG. 1. FIG. 1 is a diagram for explaining the general architecture of the multi-bit current mode digital transmission method of the present invention. In this example, two bits blTX and b2TX are combined into a current signal in the multi-bit transmission device CMTX. --- 1 ---.------! .-------- Order · (Please read the notes on the back before filling this page) The paper size is in accordance with the Chinese National Standard (CNS) A4 Specifications (210 x 297 mm) 436704 B7 V. Description of the invention (7) Figure 2 is a circuit diagram of an embodiment of a multi-bit transmission device. In the circuit diagram of the transmission device embodiment shown in FIG. 2, the gates of the N-type metal-oxide-semiconductor (MOS) transistor M1 and the P-type transistor M2 are connected to the first bit data input terminal blTX of the transmission device, and the N-type transistor M1 Is connected to the first high voltage source Vccl, and the drain of the P-type transistor M2 is connected to the first low voltage source Vss: l. The source of the N-type transistor M1 and the source of the P-type transistor M2 are connected to the output terminal of the transmission device together. It can be known from Figure 1 that the output terminal of the transmitting device is connected to the current mode data bus CMB. The gates of the N-type transistor M3 and the P-type transistor M6 are connected to the second bit data input terminal b2TX of the transmitting device. The drain of the N-type transistor M3 is connected to the first high-voltage source Vccl, and the drain of the P-type transistor M6 is connected to the first low-voltage source Vssl. The gates of the N-type transistor M4 and the P-type transistor M5 are connected to the first bit data input terminal MTX of the transmitting device. The source of the N-type transistor M3 is connected to the drain of the N-type transistor M4. The source of the P-type transistor M6 is connected to the drain of the P-type transistor M5. The source of the N-type transistor M4 and the source of the P-type transistor M6 are connected to the output terminal of the transmission device together. As can be seen in Figure 2, the current mode signal CMS is the sum of the currents IV Π, Γ2, Γ2 and so on. Table 1 shows the relationship between the current mode signal CMS and the two input data bits.
___S 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先間讀背面之注意事項再填寫本頁) 裳-------丨訂---- 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作杜印製 436704 A7 _B7 五、發明說明（ί ) 表 b2TX blTX Ι+ι Ι'ι 1+2 r2 CMS 0 0 0 1 0 1 I 1 + ϊ 2 〇 1 1 〇 0 0 I+1 1 0 0 1 0 0 Γι 1 1 1 0 1 0 I+i+I+2 電流GΠ、1+2及Γ2等的大小是由第一高電壓源與第 一低電壓源的電位差以及金氧半電晶體Ml、M2、M3、Μ4、 M5及M6的相對物理尺寸所決定。表二爲一實施例中金氧 半電晶體Μ卜M2、M3、M4、M5及M6等的通道的長度與 寬度的比例關係。 表二 電晶體 寬度 長度 Ml 10 0.5 M2 20 0.5 M3 20 0.5 M4 20 0.5 M5 40 0.5 M6 40 0.5 如果使用表二的電晶體通道的長寬比例關係，加上第一 高電壓源Vccl爲3.3V，第一低電壓源Vssl爲0V，那麼電 流1'、ΙΊ、1+2及1_2等的大小約各爲1毫安培(mA)。 請參考圖一，電流模式訊號CMS是透過電流模式資料 ------------< M.--------訂. (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公S ) 經濟部智慧財產局員工消費合作杜印製 -：< e 7 Ο 4 A7 ___B7__ 五、發明說明（^ ) 匯流排CMB傳送至電流模式接收裝置CMRX。另外，在電 流模式接收裝置CMRX中的第二低電壓源Vss2需連接至傳 送裝置CMTX的第一低電壓源Vssl。如此可以使得有一回 轉電流CMSR來配合電流模式信號CMS完成系統的回路。 在本發明的實施例之中，可以將電流模式傳送裝置與接 收裝置均置於同一個半導體晶片上或印刷電路板上。在此種 情況下，第一高電壓源Vcc丨與第二高電壓源Vcc2，實際上 可以是同一個電壓源。同樣的第一低電壓源VSSl與第二低電 壓源Vss2也可以是同一個電壓源，這樣就不需要回轉路徑 RTN。 現在，請參考圖六，在圖六中解釋了電流模式傳送裝置 CMTX如何產生電流模式訊號。在時間週期乃，要傳送的 雙位元資料blTX與b2TX是在第一邏輯準位(0)，而電流模 式訊號此時是處於電流準位A，這是圖二中電流Π與Γ2的 和。在時間週期Τ2，第一位元blTX是處於第二邏輯準位(1)， 第二位元b2TX則仍處於第一邏輯準位(0)，電流模式訊號此 時是處於電流準位B，這是圖二中的電流1'。 繼續參考圖六，在時間週期T3，要傳送的雙位元資料的 第一位元blTX是在第二邏輯準位(1)，第二位元b2TX是在 第一邏輯準位(1)，而電流模式訊號此時是處於電流準位C， 這是圖二中電流广與匕的和。 最後，在時間週期τ4，第一位元blTX是處於第一邏輯 準位(〇)，第二位元b2TX則處於第二邏輯準位⑴，電流模式 訊號CMS此時是處於電流準位D，這是圖二中的電流Π。 ------------- --------訂—I------^ 乂請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 436704 A7 __B7_______ 五、發明說明（〖°) 現在再參考圖一，電流模式資料匯流排CMB是用來傳 遞訊號的媒介，在半導體晶片上，其可以是鋁金屬線’在印 刷電路板上，其可能是印刷的線路’或者在兩個計算機功能 裝置間的傳輸電纜線。 電流模式訊號CMS被電流模式接收裝置CMRX所接 收，電流模式接收裝置CMRX包括電流接收器與邏輯訊號 取出電路，這些部份將在此做詳細說明。電流模式接收裝置 CMRX接收電流模式訊號CMS並將其轉換成代表原數位信 號b 1TX與b2TX的未修正訊號α與/3。表三顯示了未修正 訊號α、/3與原數位信號blTX、b2TX的對應關係。 表三 blTX b2TX a β 0 0 1 1 1 0 0 Vref 0 1 1 Vref 1 1 0 0 表三中的Vref的電壓準位大約是介於第一邏輯準位(0) 與第二邏輯準位⑴之間。 經濟部智慧財產局員工消費合作社印製 --------t I . 丨裝 ------—訂· (請先閱讀背面之注意事項再填寫本頁) 接著請參考圖三，對於電流模式接收裝置CMRX有更淸 楚的描述。電流模式資料匯流排CMB是連接於電流模式接 收裝匱CMRX的輸入端，該輸入端連接至差動放大器OP1 的反相輸入端(一）。該差動放大器OP1的非反相輸入端(+ ) 則連接於參考電壓源Vref。參考電壓源Vref的電壓準位大約 是介於第二高電壓源Vcc2與第二低電壓源Vss2之間，因此， --—- ___11___ 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 A7 B7__ 五、發明說明（（l ) 若以Vcc2等於3.3V，而乂吻等於0V ’則Vref的電壓準位 係介於3.3V〜0V之間者。 電流模式接收裝置的輸入端更連接至第一傳輸閘道 (transmission gate)Xl，該第一傳輸閘道XI由N型金氧半電 晶體M8與P型金氧半電晶體M7所組成，輸入端由N型金 氧半電晶體M8的汲極與P型金氧半電晶體M7的源極相連 接而成，輸出端則是N型金氧半電晶體M8的源極與P型金 氧半電晶體M7的汲極相連接而成，而N型金氧半電晶體 M8的閘極接至第二高電壓源Vcc2，另外P型金氧半電晶體 M7的閘極接至第二低電壓源Vss2 ’由於N型金氧半電晶體 M8與P型金氧半電晶體M7的閘極均被偏壓，故第一傳輸 閘道XI的作用與一電阻類似。第一傳輸閘道XI的輸出端 與差動放大器0P1的輸出端相連接，形成第一未修正訊號輸 出端α，即傳送的兩個位元數位訊號的第一位元未修正訊 電流模式接收裝置的輸入端更連接至第三傳輸閘道 (transmission gate)X3，該第三傳輸閘道Χ3由Ν型金氧半電 晶體Ml 1與P型金氧半電晶體M12所組成’輸入端由N型 金氧半電晶體Ml 1的汲極與P型金氧半電晶體M12的源極 相連接而成，輸出端則是N型金氧半電晶體Ml 1的源極與P 型金氧半電晶體M12的汲極相連接而成，而N型金氧半電 晶體Ml 1的閘極與P型金氧半電晶體M12的閘極均接至第 一未修正訊號輸出端α，由於N型金氧半電晶體Mil與P 型金氧半電晶體M12的閘極均被接至第一未修正訊號輸出 (請先閱讀背面之注意事項再填寫本頁) 裝----- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 436704 A7 __ R7__ 五、發明說明（丨’） 端α，故第三傳輸閘道X3的作用與一可變電阻類似，當第 一未修正訊號輸出端^處於第一邏輯準位(0)時，第三傳輸閘 道Χ3具有第一阻抗的特性，當第一未修正訊號輸出端α處 於第二邏輯準位(1)時’第三傳輸閘道Χ3具有第二阻抗的特 性。 第三傳輸閘道Χ3的輸出端接至差動放大器〇Ρ2的反相 輸入端(-）。差動放大器ΟΡ2的非反相輸入端(+)則接至參 考電壓源Vref。 第三傳輸閘道X3的輸出端更接至第二傳輸閘道X2的 輸入端，該第二傳輸閘道的輸入端是由N型金氧半電晶體 Ml0的汲極與P型金氧半電晶體M9的源極相連接而成。N 型金氧半電晶體M10的閘極連接至第二高電壓源Vcc2，而P 型金氧半電晶體M9的閘極連接至第二低電壓源Vss2。因爲 N型金氧半電晶體M10與P型金氧半電晶體M9的閘極均被 偏壓，故第二傳輸閘道X2的作用與一電阻類似。 第二傳輸閘道X2的輸出端是由N型金氧半電晶體M10 的源極與P型金氧半電晶體M9的汲極相連接而成，該輸出 端並接至差動放大器OP2的輸出端，形成第二未修正訊號輸 出端Θ，即傳送的兩個位元數位訊號的第二位元未修正訊 號。 在由第一傳輸閘道XI與差動放大器OP1組成的這部分 電路中’由於第一傳輸閘道XI始終處於導通狀態，所以差 動放大器〇P1的輸出端有一電阻性回授連接至差動放大器 OP1的反相輸入端，因此而形成負回授電路，該狀態的特性 ________ η____ 本紙張尺度適用中國國家標準（CNS)A4規格（2】0 X 297公f ) ' ------------- ^--------訂---------β (請先閱讀背面之注意事項再填寫本頁> 經濟部智慧財產局員工消費合作社印製 43 67 0 4 A7 ______B7_ 五、發明說明（丨>) 將使得差動放大器OP1的反相輸入端與非反相輸入端具有 等電位’即反相輸入端電位V(-)將保持與非反相輸入端電 位v( +湘等。舉例來說，如果反相輸入端電位V(一)大於非 反相輸入端電位v( + )，差動放大器OP1的輸出端電壓將往 負方向增加’此時流過第一傳輸閘道XI的電流，將使得反 相輸入端電位v(—)亦向下調整。在圖三的例子中，第一傳 輸閘道XI的作用會促使反相輸入端電位V(-)等於非反相 輸入端電位V( + )，也就是等於參考電壓源的電位Vref。差 動放大器OP2與第二傳輸閘道X2的關係也相同於對差動放 大器OP1與第一傳輸閘道XI的回授動作說明。 如果位於電流模式資料匯流排CMB上的電流爲零，則 在差動放大器on與第一傳輸閘道XI的電路中，根據上面 的討論，電流模式資料匯流排的電壓v(cmb)會等於參考電 源電壓Vref。事實上，在這個狀態時，沒有電流流經第一傳 輸閘道XI，所以跨在第一傳輸閘道XI兩端的電位差等於 零，因此差動放大器0P1輸出端的電壓ν(α)會等於電壓 V(CMB)，也等於參考電壓源電壓Vref。將這樣的偏壓力口到 第三傳輸閘道X3上，會使得第三傳輸閘道X3關閉，因此 差動放大器0P2及第二傳輸閘道X2與電流模式資料匯流排 CMB的連通被關閉，也因此使得差動放大器OP2的反相輸 入端電位v(-傳於非反相輸入端電位v(+)，也就是等於參 考電壓源的電位Vref，同時沒有電流流經第二傳輸閘道X2。 所以差動放大器OP2的輸出端電壓V(召)等於參考電壓源的 電位Vref，也就是說電壓V( α)等於電壓V( yS)等於電壓 I!----^------裝--------訂· (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 B? 五、發明說明（if) V(CMB)且大小爲參考電壓源的電位Vref。 如果圖二的電流傳送裝置送出一電流訊號到電流模式 資料匯流排CMB，結果將使得電流模式資料匯流排上的電 位V(CMB)產生改變。舉例來說，假設電流1'由第一高電壓 源流入電流模式資料匯流排CMB 〇電壓V(CMB)會驅向正 値，在此時，差動放大器的輸出電壓V(o〇會向負方向增力口 以補償電流模式資料匯流排上的電位V(CMB)的上升。金氧 半電晶體Ml及第一傳輸閘道XI的電晶體M7/M8的比例適 當調整可以使得由MTX變成邏輯準位(1)所導致的電流大約 等於差動放大器Opl的輸出電壓V( α)所導致流過第一傳輸 閘道XI的電流，而差動放大器Opl的輸出電壓V(a)會等 於第二低電壓源Vss2，且電流模式資料匯流排上的電位 V(CMB)會等於參考電壓源的電位Vref。由於差動放大器 Opl的輸出電壓V(a燴等於第二低電壓源Vss2，所以P型 金氧半電晶體M12會導通。不過所有來自傳送裝置的電流 都會被差動放大器〇P 1及第一傳輸閘道XI這部分的電路吸 收。差動放大器0p2的輸出電壓V(/5)仍然會維持在參考電 壓源電位Vref。上述情況的狀態就列在下面表四的第二列， jS=Vref。現在，假設圖二中的1+2也加入時，即b2TX 也成爲邏輯準位(1)。 因爲在上面的情況中，我們已先使差動放大器Opl的輸 出電壓ν(α)等於第二低電壓源Vss2，第一傳輸閘道XI流 著電流I+i，所以這部分的電路不會對1"2有反應，也稱爲其 已達到順從極限(compliant limit)，此時這部分的電路不會再 本紙張尺唐通用令國國家標準（CNS)A4規格（2i0 X 297公釐） ---------- !t--------訂· (請先閱讀背面之注意事項再填寫本頁) 436704 A7 五、發明說明（lT ) 吸收電流模式資料匯流排CMB上的電流I+2。由於P型金氧 半電晶體M12已導通，電流1+2因此會流至差動放大器0P2 及第二傳輸閘道X2這部分的電路，使這部分的電路動作。 相同於對1'的分析，差動放大器〇p2的輸出電壓V( /9)會向 負電位偏以補償電流1+2。同樣的，我們調整P型金氧半電晶 體M9及N型金氧半電晶體M10的尺寸，以使得電壓V( /3) 等於第二低電壓源Vss2。此時電流模式資料匯流排CMB上 的電流是(1'+ Γ2)，而電壓V( α)等於電壓V( /5)等於第二低 電壓源Vss2。此爲表四第三列的情況’ α=〇,沒=〇。現在’ 假設只有電流ΙΊ由電流模式資料匯流排CMB上流向第一低 電壓源Vssi。電壓V(CMB)會驅向負値’在此時’差動放大 器Opl的輸出電壓V(a)會向正方向增加’以補償電流模式 資料匯流排上的電位V(CMB)的下降。金氧半電晶體M2及 第一傳輸閘道XI的電晶體M7/M8的比例適當調整可以使得 由blTX變成邏輯準位(0)所導致的電流大約等於差動放大器 Opl的輸出電壓V( α)所導致流過第一傳輸閘道XI的電流， 而差動放大器〇pl的輸出電壓ν(α)會等於第二高電壓源 Vcc2，且電流模式資料匯流排上的電位V(CMB)會等於參考 電壓源的電位Vref。由於差動放大器Opl的輸出電壓V(a) 會等於第二高電壓源Vcc2，所以Ν型金氧半電晶體Mil會 導通。 不過，所有來自傳送裝置的電流都會被差動放大器〇pl 及第一傳輸闊道XI追部分的電路吸收，沒有電流會流過N 型金氧半電晶體M11。差動放大器0P2的輸出電壓v( /3)仍 本紙張尺度適用中國國家標準規格（210 X297公釐） 請先閱讀背面之泣意事項再填寫本頁) 裝--------訂--------- 經濟部智慧財產局員工消費合作社印製 4 3 67 0 4 A7 _ B7 五、發明說明（丨t) 然會維持在參考電壓源電位Vref。上述這種情況反應在表四 的第四列，a=l, ；S=Vref。 現在，假設圖二中的Γ2也加入時，即b2TX也成爲邏 輯準位(0)。因爲在上面的情況中，我們已先使差動放大器 Opl的輸出電壓V(a)等於第二高電壓源Vcc2，第一傳輸閘 道XI流著電流Π，所以這部分的電路不會對Γ2有反應，也 稱爲其已達到順從極限(complmnt limit)，此時這部分的電路 不會再吸收電流模式資料匯流排CMB上的電流Γ2。由於N 型金氧半電晶體Mil已導通，電流Γ2因此會流至差動放大 器Ορ2及第二傳輸閘道Χ2這部分的電路，使這部分的電路 動作。相同於對I、的分析，差動放大器〇ρ2的輸出電壓V( /3) 會向正電位偏以補償電流Γ2。同樣的，我們調整P型金氧半 電晶體Μ9及Ν型金氧半電晶體Μ10的尺寸，以使得電壓 V(yS)等於第二高電壓源Vcc2。此時電流模式資料匯流排 CMB上的電流是(Ι> Γ2)，而電壓V( α)等於電壓V( /3)等於 第二高電壓源Vcc2。此爲表四第一列的情況’《=1，/5=1。 表四列出了未修正資料訊號的位元準位相對於圖六中 的電流準位A、B、C及D的關係。 ----------' -裝--------訂- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作杜印製 表四 CMS a β Α(Γι+ r2) 1 1 Β(Ι+ι) 0 Vref C(IV ι+2) 0 0 D(I'i) 1 Vref 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 ^ 3 6 7 Ο 4 Α7 —--------Β7___ _ 五、發明說明（/；?) 電流接收裝置的輸出端α及/5連接至如圖四A、四B及 四C的修正電路或該修正電路的布林函數圖。如圖四A中’ 兩個位兀i資料的第~資料位兀blRX是弟一未修正資料位兀 α的反邏輯(logical NOT)，所以可用簡單的反相器(inverter) 來實施此部分修正電路。 至於決定第二未修正資料位元/5是否爲參考電壓源電 位的電路如圖四B所示。圖三電流接收裝置的第二未修正資 料位元/3被連接至反相緩衝電路U1的輸入端。反相緩衝電 路U1的動作是當輸入端電位大於其設定的臨限電位時，輸 出端的邏輯準位才會改變。在本實施例中’反相緩衝電路 U1的臨限電位需大於參考電壓源電位，即該反相器必需保 證在第二未修正資料位元Θ爲參考電壓源電位時不能改變 邏輯準位。但是，該反相器必需能從第二邏輯準位(1)轉變爲 第一邏輯準位(0)，當第二未修正資料位元/5爲第二邏輯準位 ⑴時。 第二未修正資料位元Θ亦連接至由U2及IB構成的緩 衝電路的輸入端。在本實施例中，這個由U2及U3構成的 緩衝電路被設計成有一低臨限電位，即當輸入端電位一大於 第一邏輯準位(〇)時，該緩衝電路的輸出電位立即由第一邏輯 準位(0)轉變爲第二邏輯準位(1)。這個設計是確保在輸入端電 位到達參考電壓源電位前’輸出端早已轉態爲第二邏輯準位 反及閘(NAND)U4和反相器(mVerter)U5組合成邏輯 AND的功能，其輸出端訊號稱爲/3 ΜΠ)，只有在第二未修正 裝--------訂---------- 請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297 ) 經濟部智慧財產局員工消費合作社印製 4367 04 A7 ____B7__ 五、發明說明（β ) 資料位元/3爲參考電壓源電位Vref時，/3 MID才會爲第二 邏輯準位(1)。 最後圖四C用來說明如何修正，以獲得第二資料位元 b2RX。第二資料位元b2RX是圖四C所描述的邏輯功能電 路的輸出結果。 很多的數學通訊系統都有一個基本要求，就是必須要能 在兩個功能單元(function unit)間利用同一個傳輸媒介來作雙 向的通訊。現在，請參考圖五，圖五用來描述一個多位元雙 向電流模式的數位通訊系統。 多位元雙向電流模式數位通訊系統，包括：傳送裝置 CMTXi、CMTX2及接收裝置CMRX!、CMRX2，它們分別連 接至電流模式資料匯流排的兩端。傳送裝置CMT&用來組 合兩資料位元M1TX及bl2TX，以形成電流模式訊號 CMS1。電流模式訊號CMS1被電流模式接收裝置CMRX2 接收後，該接收裝置CMRX2會處理此電流模式訊號CMS 1 而得出數位資料位元bl 1RX及bl2RX。 傳送裝匱CMTX2用來組合兩資料位元b21TX及 b22TX，以形成電流模式訊號CMS2 〇電流模式訊號CMS2 被電流模式接收裝置CMRXi接收後，該接收裝匱CMRX1 會處理此電流模式訊號CMS2而得出數位資料位元b21RX 及 b22RX。 在本實施例中，電流模式資料匯流排CMB在同一時間 只能是單一方向的傳輸信號，停止某一方向的傳輸後，才能 開始另一方向的傳送動作。例如，當電流模式的傳送裝置 ---------- *皿^,1------訂， {請先閱讀背面之注意事項再填寫本頁) - 10__ ^紙張尺度適闬中國國家標準（CNS)A4燒格（210 κ 297公釐) 436704 A7 _ B7 五、發明說明（（/) CMTXi傳送資料給接收裝置cmrx2時，傳送裝置cmtx2 與接收裝置CMRXi必須停止動作。同樣的，當電流模式的 傳送裝置CMTX2傳送資料給接收裝置CMKK時，傳送裝置 CMTXi與接收裝置CMRX2必須停止動作。這樣的通訊模式 一般稱爲單工傳輸(simplex transmission)。 圖二的電流模式傳送裝置，如果在兩個輸入端MTX與 b2TX的電位都介於金氧半電晶體(MOS)的臨限電壓與參考 電壓源電位Vref之間時，該電流模式傳送裝置將處於靜止狀 態。因此在雙向通訊的情況時，我們可以藉由使傳送裝置輸 入端電壓値爲參考電壓源電位，而令其停止動作。 圖三的電流模式接收裝置，在雙向通訊的情況時，也必 需能快速進入靜止狀態，這可以藉著在差動放大器Opl的反 相輸入端(-)與電流模式資料匯流排CMB間串接一金氧半 電晶體構成的傳輸閘道。由於電流模式資料匯流排上的電壓 準位接近於參考電壓源Vref，所以該傳輸閘道只需要一個電 晶體。由於N型金氧半電晶體有較尚的增益，故會被選用。 如果兩個接收端的傳輸閘道均不導通(OFF)時，圖五中的電 流模式資料匯流排CMB便會形成浮接狀態。電流模式資料 匯流排浮接的話，會有無法預期的工作模式，而且可能有過 高或過低的電路阻抗。如果兩個接收端的傳輸閘道均導通 (ON)時，圖五中的電流模式資料匯流排CMB上便會在不工 作時一直維持在接近參考電壓源的電位Vref。 電流模式傳送裝置CMTX^ CMTX2的結構如以上對 圖二的說明。電流模式接收裝置CMRX^ CMRX2的結構如 _^ ... _ — oc\ 本紙張足度適用中國國家標準（CNS>A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) k I n I I l 一&,， n n n I . 經濟部智慧財產扃員工消費合作社印製 A7 五、發明說明（广4 以上對圖三的c說明。 一種雙向資料匯流排具有每一方向一條傳輸線以及每 一傳輸線上兩位元資料，那麼便絕對可以做到同時雙向的資 料傳送，更不需要資料匯流排仲裁裝置及轉向設計。這樣的 雙向資料匯流排較傳統的單位元雙工(duplex)傳輸方式有更 好的工作效倉g 〇 以上實施例的說明可以較容易解釋本發明的動作原 理，對於如圖二、圖三、圖四的技術，可以被運用到更多位 元資料的傳送或接收裝置上。圖二、圖三以及圖四中的金氧 半電晶體元件，也可以由熟悉該項技術者以雙極接面(bipolar junction)電晶體加以取代。 本發明的原理與技術內容，已透過上述的說明與圖示而 可使一般熟習該類技術者加以理解與明瞭。任何熟習本發明 技術者，或可加以變化與修改，但仍不脫離本發明的精神與 申請專利範圍。 —丨---：------裝--------訂. (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公釐)___S This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (please read the precautions on the back before filling this page) Printed by the Intellectual Property Bureau's Consumer Cooperative Cooperative Printed by the Ministry of Economic Affairs' Intellectual Property Bureau's Consumer Cooperative Print 436704 A7 _B7 V. Description of Invention (ί) Table b2TX blTX Ι + ι Ι'ι 1 + 2 r2 CMS 0 0 0 1 0 1 I 1 + ϊ 2 〇1 1 〇0 0 I + 1 1 0 0 1 0 0 Γι 1 1 1 0 1 0 I + i + I + 2 The magnitudes of the currents GΠ, 1 + 2 and Γ2 are determined by the first high voltage The potential difference between the source and the first low-voltage source is determined by the relative physical sizes of the metal-oxide semiconductor transistors M1, M2, M3, M4, M5, and M6. Table 2 shows the ratio of the length and width of the channels of the metal-oxide-semiconductor crystals M2, M3, M4, M5, and M6 in one embodiment. Table 2 Transistor width and length Ml 10 0.5 M2 20 0.5 M3 20 0.5 M4 20 0.5 M5 40 0.5 M6 40 0.5 If the length-width ratio of the transistor channel in Table 2 is used, plus the first high voltage source Vccl is 3.3V, The first low voltage source Vssl is 0V, so the magnitudes of the currents 1 ′, 1Ί, 1 + 2, 1_2, and so on are each about 1 milliampere (mA). Please refer to Figure 1. The current mode signal CMS is based on the current mode data ------------ < M .-------- Order. (Please read the precautions on the back before filling (This page) This paper size is in accordance with China National Standard (CNS) A4 (210 x 297 male S). Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs for consumer cooperation. Du:-<e 7 Ο 4 A7 ___B7__ 5. Description of the invention (^) The bus CMB is transmitted to the current mode receiving device CMRX. In addition, the second low voltage source Vss2 in the current mode receiving device CMRX needs to be connected to the first low voltage source Vssl of the transmitting device CMTX. In this way, a loop current CMSR can be matched with the current mode signal CMS to complete the system loop. In the embodiment of the present invention, both the current mode transmitting device and the receiving device may be placed on the same semiconductor wafer or printed circuit board. In this case, the first high voltage source Vcc 丨 and the second high voltage source Vcc2 may actually be the same voltage source. The same first low-voltage source VSS1 and the second low-voltage source Vss2 may also be the same voltage source, so that the turning path RTN is not required. Now, please refer to FIG. 6, which explains how the current mode transmitting device CMTX generates a current mode signal. In the time period, the double-bit data blTX and b2TX to be transmitted are at the first logic level (0), and the current mode signal is at the current level A at this time. This is the sum of the current Π and Γ2 in Figure 2. . At time period T2, the first bit blTX is at the second logic level (1), the second bit b2TX is still at the first logic level (0), and the current mode signal is at the current level B at this time. This is the current 1 'in Figure 2. With continued reference to FIG. 6, at time period T3, the first bit blTX of the double-bit data to be transmitted is at the second logical level (1), and the second bit b2TX is at the first logical level (1). The current mode signal is now at the current level C, which is the sum of the current and dagger in Figure 2. Finally, at time period τ4, the first bit blTX is at the first logic level (0), the second bit b2TX is at the second logic level ⑴, and the current mode signal CMS is now at the current level D, This is the current Π in Figure 2. ------------- -------- Order—I ------ ^ 乂 Please read the notes on the back before filling this page) This paper size is applicable to China Standard (CNS) A4 specification (210 X 297 mm) 436704 A7 __B7_______ 5. Description of the invention (〖°) Now referring to Figure 1, the current mode data bus CMB is a medium used to transmit signals. On a semiconductor chip, its It can be an aluminum metal wire 'on a printed circuit board, which may be a printed circuit' or a transmission cable line between two computer function devices. The current mode signal CMS is received by the current mode receiving device CMRX. The current mode receiving device CMRX includes a current receiver and a logic signal take-out circuit. These sections will be described in detail here. Current mode receiving device CMRX receives the current mode signal CMS and converts it into uncorrected signals α and / 3 representing the original digital signals b 1TX and b2TX. Table 3 shows the correspondence between the uncorrected signals α and / 3 and the original digital signals blTX and b2TX. Table 3 blTX b2TX a β 0 0 1 1 1 0 0 Vref 0 1 1 Vref 1 1 0 0 The voltage level of Vref in Table 3 is approximately between the first logic level (0) and the second logic level ⑴ between. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs -------- t I. 丨 Installation ------------ Order (Please read the precautions on the back before filling this page) Then please refer to Figure III There is a better description of the current mode receiving device CMRX. The current mode data bus CMB is connected to the input terminal of the current mode receiver CMRX. This input terminal is connected to the inverting input terminal (1) of the differential amplifier OP1. The non-inverting input terminal (+) of the differential amplifier OP1 is connected to a reference voltage source Vref. The voltage level of the reference voltage source Vref is approximately between the second high voltage source Vcc2 and the second low voltage source Vss2. Therefore, ----- ___11___ This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7__ 5. Description of the invention ((l) If Vcc2 equals 3.3V and the kiss equals 0V ', then the voltage level of Vref is between 3.3V ~ 0V The input terminal of the current-mode receiving device is further connected to a first transmission gate X1. The first transmission gate XI is composed of an N-type metal-oxide-semiconductor M8 and a P-type metal-oxide-semiconductor M7. The input end is formed by connecting the drain of the N-type metal-oxide-semiconductor M8 and the source of the P-type metal-oxide-semiconductor M7, and the output terminal is the source of the N-type metal-oxide-semiconductor M8 and The drain of the P-type metal-oxide-semiconductor M7 is connected, and the gate of the N-type metal-oxide-semiconductor M8 is connected to the second high-voltage source Vcc2, and the gate of the P-type metal-oxide-semiconductor M7 is connected To the second low-voltage source Vss2 'Because the gates of the N-type MOSFET and M7 are biased Therefore, the function of the first transmission gateway XI is similar to that of a resistor. The output of the first transmission gateway XI is connected to the output of the differential amplifier OP1 to form the first uncorrected signal output α, that is, the two bits transmitted. The input of the first bit uncorrected signal current mode receiving device of the digit signal is further connected to a third transmission gate X3, which is composed of an N-type metal-oxide semiconductor transistor Ml 1 and The input terminal of the P-type metal-oxide-semiconductor M12 is formed by connecting the drain of the N-type metal-oxide-semiconductor M11 to the source of the P-type metal-oxide-semiconductor M12, and the output terminal is N-type gold The source of the oxygen semi-transistor Ml 1 is connected to the drain of the P-type metal-oxide semi-transistor M12, and the gate of the N-type metal-oxide-semiconductor Ml 1 is connected to the gate of the P-type metal-oxide semi-transistor M12. The poles are connected to the first uncorrected signal output terminal α, because the gates of the N-type metal-oxide semiconductor transistor Mil and the P-type metal-oxide semiconductor transistor M12 are connected to the first uncorrected signal output (please read the back Please fill in this page for the matters needing attention) Loading ----- This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 436704 A7 __ R7__ 5. Description of the invention (丨 ') terminal α, so the role of the third transmission gateway X3 is similar to a variable resistor, when the first uncorrected signal output terminal ^ When at the first logic level (0), the third transmission channel X3 has the characteristic of the first impedance. When the first uncorrected signal output terminal α is at the second logic level (1), the third transmission channel X3 Has a second impedance characteristic. The output terminal of the third transmission gateway X3 is connected to the inverting input terminal (-) of the differential amplifier OP2. The non-inverting input (+) of the differential amplifier OP2 is connected to the reference voltage source Vref. The output terminal of the third transmission gateway X3 is further connected to the input terminal of the second transmission gateway X2. The input terminal of the second transmission gateway is the drain of the N-type metal-oxide semiconductor transistor M10 and the P-type metal-oxide semiconductor. The source of transistor M9 is connected. The gate of the N-type metal-oxide-semiconductor M10 is connected to the second high-voltage source Vcc2, and the gate of the P-type metal-oxide-semiconductor M9 is connected to the second low-voltage source Vss2. Since the gates of the N-type metal-oxide semiconductor M10 and the P-type metal-oxide semiconductor M9 are both biased, the role of the second transmission gateway X2 is similar to that of a resistor. The output terminal of the second transmission gateway X2 is formed by connecting the source of the N-type metal-oxide semiconductor transistor M10 and the drain of the P-type metal-oxide semiconductor transistor M9. The output terminal is connected to the differential amplifier OP2 in parallel. The output terminal forms the second uncorrected signal output terminal Θ, that is, the second uncorrected signal of the transmitted two-bit digital signal. In this part of the circuit consisting of the first transmission gateway XI and the differential amplifier OP1 'Since the first transmission gateway XI is always on, the output of the differential amplifier 〇P1 has a resistive feedback connection to the differential The inverting input terminal of the amplifier OP1 thus forms a negative feedback circuit. The characteristics of this state ________ η ____ This paper size applies to the Chinese National Standard (CNS) A4 specification (2) 0 X 297 male f) '----- -------- ^ -------- Order --------- β (Please read the notes on the back before filling out this page > Employee Consumer Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs Printed 43 67 0 4 A7 ______B7_ 5. Description of the invention (丨 >) will make the inverting input terminal and non-inverting input terminal of the differential amplifier OP1 have the same potential, that is, the potential V (-) of the inverting input terminal will be maintained And the potential of the non-inverting input terminal v (+ Xiang, etc. For example, if the potential of the inverting input terminal V (−) is greater than the potential of the non-inverting input terminal v (+), the voltage at the output terminal of the differential amplifier OP1 will go negative. Increasing the direction 'At this time, the current flowing through the first transmission gateway XI will cause the potential of the inverting input terminal v (-) to be adjusted downward. In the figure In the example, the role of the first transmission gateway XI will cause the potential V (-) of the inverting input terminal to be equal to the potential V (+) of the non-inverting input terminal, which is equal to the potential Vref of the reference voltage source. The differential amplifier OP2 and The relationship between the second transmission gateway X2 is also the same as the description of the feedback action of the differential amplifier OP1 and the first transmission gateway XI. If the current on the current mode data bus CMB is zero, then the difference amplifier on and In the circuit of the first transmission gateway XI, according to the above discussion, the voltage v (cmb) of the current mode data bus will be equal to the reference power voltage Vref. In fact, in this state, no current flows through the first transmission gateway XI, so the potential difference across the first transmission gateway XI is equal to zero, so the voltage ν (α) at the output of the differential amplifier OP1 will be equal to the voltage V (CMB) and also equal to the reference voltage source voltage Vref. Going to the third transmission gateway X3 will cause the third transmission gateway X3 to be closed, so the communication between the differential amplifier 0P2 and the second transmission gateway X2 and the current mode data bus CMB is closed, which also makes the differential amplifier The potential v (-of the inverting input terminal of OP2 is transmitted to the potential v (+) of the non-inverting input terminal, which is equal to the potential Vref of the reference voltage source, and no current flows through the second transmission gateway X2. Therefore, the differential amplifier OP2 The output terminal voltage V (call) is equal to the potential Vref of the reference voltage source, which means that the voltage V (α) is equal to the voltage V (yS) equal to the voltage I! ---- ^ ------ install ---- ---- Order · (Please read the notes on the back before filling in this page) This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs? 5. Description of the invention (if) V (CMB) and the magnitude is the potential Vref of the reference voltage source. If the current transmitting device in Fig. 2 sends a current signal to the current mode data bus CMB, the result will change the potential V (CMB) on the current mode data bus. For example, suppose that the current 1 ′ flows from the first high-voltage source into the current mode data bus CMB. The voltage V (CMB) will be driven to positive. At this time, the output voltage V (o of the differential amplifier will go to negative. The direction boost port compensates for the rise of the potential V (CMB) on the data bus of the current mode. The ratio of the metal oxide semi-transistor M1 and the transistor M7 / M8 of the first transmission channel XI can be adjusted appropriately to make MTX into logic The current caused by the level (1) is approximately equal to the current flowing through the first transmission gateway XI caused by the output voltage V (α) of the differential amplifier Opl, and the output voltage V (a) of the differential amplifier Opl will be equal to the first The second low voltage source Vss2, and the potential V (CMB) on the current mode data bus will be equal to the potential Vref of the reference voltage source. Since the output voltage V (a of the differential amplifier Opl is equal to the second low voltage source Vss2, so P The metal oxide semiconductor M12 will be turned on. However, all the current from the transmission device will be absorbed by the circuit of the differential amplifier 〇P 1 and the first transmission channel XI. The output voltage V (/ 5) of the differential amplifier 0p2 Will still be maintained at the reference voltage source potential Vref. The state of the situation is listed in the second column of Table 4 below, jS = Vref. Now, suppose that 1 + 2 in Figure 2 is also added, that is, b2TX also becomes the logical level (1). Because in the above case, We have first made the output voltage ν (α) of the differential amplifier Opl equal to the second low voltage source Vss2, and the current I + i flows through the first transmission channel XI, so this part of the circuit will not respond to 1 " 2, It is also called that it has reached the compliant limit. At this time, this part of the circuit will no longer be a paper rule. It is a national standard (CNS) A4 specification (2i0 X 297 mm) ------- ---! t -------- Order · (Please read the precautions on the back before filling out this page) 436704 A7 V. Description of Invention (lT) Current I + 2 on the current sink CMB Since the P-type metal-oxide semiconductor transistor M12 has been turned on, the current 1 + 2 will flow to the circuit of the differential amplifier 0P2 and the second transmission gateway X2, making the circuit of this part act. The same as the 1 ' Analysis, the output voltage V (/ 9) of the differential amplifier oop2 will be biased to the negative potential to compensate the current 1 + 2. Similarly, we adjust the P-type metal-oxide semiconductor transistor M9 The size of the N-type metal-oxide semiconductor transistor M10 is such that the voltage V (/ 3) is equal to the second low voltage source Vss2. At this time, the current on the current mode data bus CMB is (1 '+ Γ2), and the voltage V ( α) is equal to the voltage V (/ 5) is equal to the second low voltage source Vss2. This is the case in the third column of Table 4 'α = 〇, not = 〇. Now' Assume that only the current IΊ flows from the current mode data bus CMB First low voltage source Vssi. The voltage V (CMB) will be driven to a negative level. At this time, the output voltage V (a) of the differential amplifier Opl will increase in a positive direction 'to compensate for the drop in the potential V (CMB) on the data bus of the current mode. The ratio of the metal-oxide semi-transistor M2 and the transistor M7 / M8 of the first transmission gateway XI can be adjusted appropriately so that the current caused by blTX becoming the logic level (0) is approximately equal to the output voltage V (α of the differential amplifier Opl ) Caused by the current flowing through the first transmission gateway XI, and the output voltage ν (α) of the differential amplifier 0pl will be equal to the second high voltage source Vcc2, and the potential V (CMB) on the current mode data bus will be It is equal to the potential Vref of the reference voltage source. Since the output voltage V (a) of the differential amplifier Opl will be equal to the second high voltage source Vcc2, the N-type metal-oxide semiconductor transistor Mil will be turned on. However, all the current from the transmission device will be absorbed by the differential amplifier oop and the circuit of the first transmission wide track XI, and no current will flow through the N-type metal-oxide semiconductor transistor M11. The output voltage v (/ 3) of the differential amplifier 0P2 is still in accordance with the Chinese national standard specifications (210 X297 mm) on this paper. Please read the weeping on the back before filling this page) --------- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 3 67 0 4 A7 _ B7 V. The invention description (丨 t) will be maintained at the reference voltage source potential Vref. The above situation is reflected in the fourth column of Table 4, a = 1 ,; S = Vref. Now, suppose that when Γ2 in Figure 2 is also added, that is, b2TX also becomes the logic level (0). In the above case, we have first made the output voltage V (a) of the differential amplifier Opl equal to the second high-voltage source Vcc2, and the first transmission gateway XI is carrying a current Π, so this part of the circuit will not affect Γ2 There is a response, also called that it has reached the complmnt limit. At this time, the part of the circuit will no longer absorb the current Γ2 on the current mode data bus CMB. Since the N-type metal-oxide semiconductor transistor Mil has been turned on, the current Γ2 will flow to the circuits of the differential amplifier 0ρ2 and the second transmission gateway X2, and the circuits of this part will be activated. Similar to the analysis of I, the output voltage V (/ 3) of the differential amplifier 0ρ2 will be biased to a positive potential to compensate the current Γ2. Similarly, we adjust the size of the P-type metal-oxide-semiconductor M9 and N-type metal-oxide-semiconductor M10 so that the voltage V (yS) is equal to the second high-voltage source Vcc2. At this time, the current on the current-mode data bus CMB is (I > Γ2), and the voltage V (α) is equal to the voltage V (/ 3) equal to the second high voltage source Vcc2. This is the case in the first column of Table IV ’" = 1, / 5 = 1. Table 4 shows the relationship between the bit level of the uncorrected data signal and the current levels A, B, C, and D in Figure 6. ---------- '-Installation -------- Order- (Please read the notes on the back before filling out this page) Employee Co-operation of Intellectual Property Bureau, Ministry of Economic Affairs a β Α (Γι + r2) 1 1 Β (Ι + ι) 0 Vref C (IV ι + 2) 0 0 D (I'i) 1 Vref This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs ^ 3 6 7 Ο 4 Α7 —-------- Β7 ___ _ V. Description of the invention (/ ;?) Output terminal α of the current receiving device and / 5 is connected to a correction circuit as shown in Figures 4A, 4B, and 4C or a Bollinger Function diagram of the correction circuit. As shown in Figure 4A, the first data bit blRX of the two data bits is the logical NOT of the uncorrected data bit α, so a simple inverter can be used to implement this part. Correct the circuit. The circuit for determining whether the second uncorrected data bit / 5 is the potential of the reference voltage source is shown in Figure 4B. The second uncorrected data bit / 3 of the current receiving device of Fig. 3 is connected to the input terminal of the inverting buffer circuit U1. The action of the inverting buffer circuit U1 is that the logic level of the output terminal will change when the potential of the input terminal is greater than its set threshold potential. In this embodiment, the threshold potential of the 'inverting buffer circuit U1 needs to be greater than the potential of the reference voltage source, that is, the inverter must ensure that the logic level cannot be changed when the second uncorrected data bit Θ is the potential of the reference voltage source. However, the inverter must be able to change from the second logic level (1) to the first logic level (0) when the second uncorrected data bit / 5 is the second logic level ⑴. The second uncorrected data bit Θ is also connected to the input of the buffer circuit composed of U2 and IB. In this embodiment, the buffer circuit composed of U2 and U3 is designed to have a low threshold potential, that is, when the potential of the input terminal is greater than the first logic level (0), the output potential of the buffer circuit is immediately changed by the first A logic level (0) is changed to a second logic level (1). This design is to ensure that before the potential of the input terminal reaches the potential of the reference voltage source, the output terminal has already transitioned to the second logic level and the gate (NAND) U4 and the inverter (mVerter) U5 combine to form a logical AND function. The end signal is called / 3 ΜΠ), only in the second uncorrected installation -------- Order ---------- Please read the precautions on the back before filling this page) This paper size Applicable to China National Standard (CNS) A4 specification (210 X 297) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 4367 04 A7 ____B7__ V. Description of the invention (β) Data bit / 3 is the reference voltage source potential Vref, / 3 MID will be the second logic level (1). Finally, FIG. 4C is used to explain how to modify to obtain the second data bit b2RX. The second data bit b2RX is the output result of the logic function circuit described in Fig. 4C. Many mathematical communication systems have a basic requirement, that is, they must be able to use the same transmission medium for two-way communication between two function units. Now, please refer to Figure 5. Figure 5 is used to describe a multi-bit bidirectional current mode digital communication system. The multi-bit bidirectional current mode digital communication system includes: transmitting devices CMTXi, CMTX2 and receiving devices CMRX !, CMRX2, which are respectively connected to both ends of the current mode data bus. The transmission device CMT & is used to combine the two data bits M1TX and bl2TX to form a current mode signal CMS1. After the current mode signal CMS1 is received by the current mode receiving device CMRX2, the receiving device CMRX2 will process the current mode signal CMS1 to obtain the digital data bits bl 1RX and bl2RX. The transmission device CMTX2 is used to combine the two data bits b21TX and b22TX to form a current mode signal CMS2. After the current mode signal CMS2 is received by the current mode receiving device CMRXi, the receiving device CMRX1 will process the current mode signal CMS2 to obtain Digital data bits b21RX and b22RX. In this embodiment, the current mode data bus CMB can only be a transmission signal in one direction at the same time, and the transmission operation in the other direction can be started after transmission in one direction is stopped. For example, when the current-mode conveying device ---------- * ware ^, 1 ------ order, {Please read the precautions on the back before filling this page)-10__ ^ The paper size is suitable闬 Chinese National Standard (CNS) A4 grill (210 κ 297 mm) 436704 A7 _ B7 V. Description of the invention ((/) When CMTXi transmits data to the receiving device cmrx2, the transmitting device cmtx2 and the receiving device CMRXI must stop operating. The same When the current mode transmitting device CMTX2 transmits data to the receiving device CMKK, the transmitting device CMTXi and the receiving device CMRX2 must stop operating. Such a communication mode is generally called a simplex transmission. Figure 2 Current mode transmitting device If the potentials of the two input terminals MTX and b2TX are between the threshold voltage of the metal-oxide-semiconductor (MOS) and the reference voltage source potential Vref, the current mode transmission device will be in a static state. In the case of communication, we can stop the operation by making the input terminal voltage of the transmitting device 値 the potential of the reference voltage source. The current mode receiving device in Figure 3 is also necessary in the case of two-way communication. It quickly enters a stationary state. This can be achieved by connecting a transmission channel formed by a metal-oxide semiconductor transistor in series between the inverting input (-) of the differential amplifier Opl and the current mode data bus CMB. Because the current mode data bus The voltage level above is close to the reference voltage source Vref, so only one transistor is needed for the transmission gateway. Because N-type metal-oxide semiconductor transistor has a relatively high gain, it will be selected. If the transmission gateway of the two receiving ends When both are not turned on (OFF), the current mode data bus CMB in Figure 5 will form a floating state. If the current mode data bus is floating, there will be an unexpected operating mode, and it may be too high or too low If the transmission gateways at both receiving ends are turned on, the current mode data bus CMB in Figure 5 will be maintained at a potential Vref close to the reference voltage source when it is not operating. Current mode transmission The structure of the device CMTX ^ CMTX2 is as described above for Figure 2. The structure of the current mode receiving device CMRX ^ CMRX2 is _ ^ ... _ — oc \ This paper is fully compliant with the Chinese National Standard (CNS > A4 (210 X 297 mm) (Please read the precautions on the back before filling out this page) k I n II l 一 & ,, nnn I. Printed by A7, Intellectual Property of the Ministry of Economic Affairs and Employees' Cooperatives V. Invention Description ( Canton 4 has explained c in Fig. 3. A two-way data bus has one transmission line in each direction and two bits of data on each transmission line. Then two-way data transmission can be achieved at the same time, and data bus arbitration is not required. Device and steering design. Such a two-way data bus has a better working efficiency than the traditional unit-element duplex transmission method. The description of the above embodiment can easily explain the operation principle of the present invention. As shown in Figures 2 and 3, The technique of Figure 4 can be applied to more bit data transmitting or receiving devices. The metal-oxide-semiconductor elements in Figures 2, 3, and 4 can also be replaced by bipolar junction transistors by those skilled in the art. The principle and technical content of the present invention can be understood and understood by those skilled in the art through the above description and illustrations. Anyone skilled in the invention may make changes and modifications without departing from the spirit of the invention and the scope of patent application. — 丨 ---: ------ Installation -------- Order. (Please read the notes on the back before filling out this page) The paper printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs is applicable China National Standard (CNS) A4 Specification (21 × 297 mm)