經濟部中央標準局貝工消費合作社印裝 3483 5 A7 B7 _______ 五、發明説明（） 發明領域_J_ 本發明係與一種半導體製程有關，特別是有關於一種 可用以形成具有雙重起始電壓（dual threshold)之互補式金 氧半場效電晶體（complementary metal oxide semiconductor field effect transistor; CMOSFET)電路的處理方法 β 發明背景匕 隨著半導體技術的發展，積體電路的製程技術發展已 由早期的大型積禮電路（large scale integration; LSI)發展至 的現階段的極大型積體電路（ultra large scale integration; ULSI)，而半導體製程中的元件積集度（integrity)也隨之快 速增加，使單一晶片上所能容納的元件數目可達到數百萬 個以上的數量= 以動態隨機存取記憶體（dynamic random access memory; DRAM)為例，半導體製程元件積集度的增加，己 使單一晶片上動態隨機存取記憶體的容量由早期的4百萬 位元（megabit)增加至16百萬位元及64百萬位元，並向更 高的容量邁進。 因此，半導體晶片上如電晶體、電容器、及連線等皆 必須進一步縮減其所使用面積，以配合更高的元件積集 度’此一要求形成對半導體製程技術的一大挑戰，每一個 半導體元件皆必須在不影響其功能的前提下，進一步縮減 本紙張尺度適用中國國家標準（CNS ) A4^格（210X297公楚） ---.1--Ϊ--- (請先閱讀背面之注意事項再填寫本頁) 訂 43483 5 A7 B7 五、發明説明（） 其尺寸或使用的面積，而在更高的積集度之下，整體元件 或電路之功能仍須維持不變，並須具有更好的可靠度、工 作壽命、並同時加入低功率消耗及低發熱率的特性》因此 半導趙製程中的四大製程技術，也就是包含微影、#刻、 薄膜、及擴散的製程技術，必須同時的研究與發展，以達 成下一代積體電路的發展目標》 在目前次微米（sub-micrometer)或更小尺寸的製程以及 應用電路的設計中，開始應用具有低潰起始電壓（low threshold voltage)特性的元件，以提供更快速的操作；而在 另一部分的電路中，仍需使用具有高潰起始電壓特性的元 件，以避免電路運作時的漏電問題。因此，在單一電路上 使用雙重起始電壓的設計，已廣為應用，·而實際應用於動 態隨機存取記憶體（DRAM)上的例子中，也顯示出其改善儲 存時間（retention time)的效果。 T. Kuroda 等人於其著作：“A0.9-V, 1 5 0-MHz，1 0-mW， 4 mm2，2-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage (VT) Scheme55 (IEEE Journal of Solid-State Circuits, Vol· 31，No. 11，1996)中，揭露有關雙 重起始電壓及動態起始電壓的技術應用，並提到降低起始 電壓可提供電路高速而低功率的操作》 經濟部中央標準局貝工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁〕 而有關動態隨機存取記憶體中改善儲存時間及縮短延 遲時間的效果，可見於 S. Thompson 等人於：“Dual Threshold Voltages and Substrate Bias: Keys to High Performance, Low Power, 0.1 μιη Logic Designs，’ （1997 本紙張尺度逍用中國國家標準（CNS ) A4规格,（210X297公釐） 434835 A7 B7 五、發明説明（）Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, 3483 5 A7 B7 _______ 5. Description of the invention () Field of invention _J_ This invention relates to a semiconductor process, and in particular, it relates to a method that can be used to form a dual starting voltage (dual threshold) complementary metal oxide semiconductor field effect transistor (CMOSFET) circuit processing method β BACKGROUND OF THE INVENTION With the development of semiconductor technology, the development of process technology for integrated circuits has been developed by early large-scale products. At the current stage of ultra large scale integration (ULSI), the development of large scale integration (LSI) circuits, and the integration of components in semiconductor processes have also increased rapidly, making a single chip The number of components that can be accommodated on the device can reach millions or more. Taking dynamic random access memory (DRAM) as an example, the increase in the accumulation degree of semiconductor process components has made a single chip dynamic. Increased the capacity of the random access memory from the earlier 4 megabits to 1 6 million bits and 64 million bits, and moving towards higher capacity. Therefore, semiconductor wafers such as transistors, capacitors, and wiring must be further reduced in area to match the higher degree of component accumulation. This requirement poses a major challenge to semiconductor process technology. Every semiconductor The components must be further reduced without affecting the function of this paper. Applicable to China National Standard (CNS) A4 ^ (210X297). ---. 1--Ϊ --- (Please read the note on the back first Please fill out this page again) Order 43483 5 A7 B7 V. Description of the invention () its size or area used, and under a higher degree of integration, the function of the overall component or circuit must remain unchanged and must have Better reliability, working life, and the characteristics of low power consumption and low heating rate are added at the same time "Therefore, the four major process technologies in the semi-conductor Zhao process, that is, lithography, #lithography, thin film, and diffusion process technology , Must be researched and developed simultaneously to achieve the development goals of the next generation of integrated circuits. "In the current sub-micrometer or smaller size process and the design of application circuits, Use components with low threshold voltage characteristics to provide faster operation; while in the other part of the circuit, components with high threshold voltage characteristics still need to be used to avoid circuit operation. Leakage problem. Therefore, the design using a double starting voltage on a single circuit has been widely used, and the example actually applied to dynamic random access memory (DRAM) has also shown its improved retention time. effect. T. Kuroda et al. In his book: "A0.9-V, 1 50-MHz, 10-mW, 4 mm2, 2-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage (VT) Scheme55 (IEEE Journal of Solid-State Circuits, Vol. 31, No. 11, 1996), reveals the technical application of double starting voltage and dynamic starting voltage, and mentions that lowering the starting voltage can provide high-speed and low-power operation of the circuit " Printed by the Shell Standard Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the notes on the back before filling this page). The effect of improving the storage time and reducing the delay time in the dynamic random access memory can be found in S. Thompson et al. In: "Dual Threshold Voltages and Substrate Bias: Keys to High Performance, Low Power, 0.1 μιη Logic Designs, '(1997 This paper is scaled to the Chinese National Standard (CNS) A4 specification, (210X297 mm) 434835 A7 B7 V. Invention description ()
Symposium on VLSI Technology Digest of Technical Papers) 的研究之中。由於一般使用電池做電源的系統等的需要’ 已使得低功率的設計成為相當重要的應用，而如何生產低 功率的元件，亦成為製程技術上的一大挑戰》而為了避免 低起始電壓元件所產生之高漏電流的問題，也必需使用具 有雙重起始電壓的設計，以應用低起始電壓的元件於需要 高速的電路中，而應用高起始電壓的元件於一般的電路 中，以減少洩漏電流的問題β 一般而言’在傳統的製程中往往需要使用到數個罩 幕，才能形成雙重起始電壓電路所需要的通道區，因此比 起單一起始電壓電路的製程要複雜許多《在Ζ. Chen等人 的研究：“0.18 μιη Dual Vt MOSFET Process and Energy-Delay Measurement” （ IEDM Tech· Dig” p. 851， 1996) 中， 對此製程有相關的介绍。 因此’傳統中形成雙重起始電壓電路所需要的複雜製 程，在製造上的步驟及成本較高，目前需要提供更簡化的 製程，以提昇雙重起始電壓電路之應用性《 務明目的及概述： 經濟部中央標準局貝工消費合作社印製 (讀先閱讀背面之注意事項再填寫本頁} 本發明的目的為提供一種形成具有雙重起始電魔電路 之方法。 本發明的另一目的為提供一種形成具有雙重起始電塵 電路之方法，使用更為簡化的製程，以降低生產的成本， 本紙張尺度適用中國國家標準（CMS) A4規格_( 210X297公釐） 434835 A7 B7 五、發明説明（） 並提高量產的速度。 本發明的另一目的為提供一種形成具有雙重起始電壓 電路之方法，以應用於具有雙重起始電壓的互補式金氧半 電晶體的製程中。 本發明中提供形成雙重起始電壓電路於半導體基材之 方法，基材具有一第一區域、一第二區域、及一第三區域， 本發明中之方法可包含以下步驟：首先摻雜第一型離子至 第一區域、第二區域、及第三區域；並接著摻雜第二型離 子至第一區域及第二區域，第二型離子與第一型離子為用 以於基材内產生相異型電性之離子，即可形成雙重起始電 壓電路所須之摻雜區。 上述之第一區域可為P型金氧半場效電晶體區，上述 之第二區域可為低起始電壓之N型金氧半場效電晶體區， 上述之第三區域可為高起始電壓之N型金氧半場效電晶體 區。並可進一步分別形成電晶體於第一區域、第二區域、 及第三區域上° (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印裝 圖式簡單說明： 第- 圖 顯 示 本發明 之半 導 體 基材 ，具有第- 區域 第 二 區域、 及第 三 區 域的 截面示意 圖。 第二 二圖 顯 示 本發明 摻雜 第 一 型離 子至第一 區域、 第 二 區 域、及 Λώ" —* 第二 域 内的 截面示意 圖。 第i :圊 顯 示 本發明 摻雜 1第 二型離子至第- _區域 及 本紙張尺度適用中國國家標率（CNS > A4規格（2Ϊ0Χ：Ζ97公釐） 434835 A7 B7 五、發明説明（ 第四圖 第二區域内之截面示意圖。 顯示本發明中分別形成電晶趙於第一區 域、第二區域、及第三區域上之截面示意 圖。 經濟部中央標準扃負工消费合作社印製 發明詳細説篮―L· 本發明中提供一種形成具有雙重起始電壓之互補式金 氧半場效電晶體電路之方法，不需使用額外增加的光罩， 即可製造具有雙重起始電壓電路所需的不同摻雜濃度的通 道區，利用摻雜相異型電性離子的過程，可形成部分離子 相互抵消的效果’而於不同的區域上得到所需的，遭度，藉 以減少製程的負擔，減低生產的成本。 本發明之方法’可用以於半導體基材上形成多個電性 及摻雜濃度不同的區域，為便於介紹，此處僅以形成包含p 型金氧半場效電晶體區、低起始電壓之N型金氧半場效電 晶體區、及高起始電壓之N型金氧半場效電晶體區之過程 為例，說明本發明之貪施，而熟知此領域技藝者，當可應 用本發明之方法，做等同之替換，以形成不同之摻雜區* 其細節即不多做贅述。 參見第一圖所述，首先提供一半導體基材10 ’ 一般的 應用是使用矽材質’晶向為的基材，亦可針尉不同的 應用，選擇其他晶向或是材質的基材。基材10上具有隔離 π A·该作，隔 區域12，以隔離各元件區’提供個別元件的獨立 請 閲 讀 .背 面 之 注 意 事 項 再 訂 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐）. ^34835 A7Symposium on VLSI Technology Digest of Technical Papers). Because of the need for batteries and other power systems, low-power design has become a very important application, and how to produce low-power components has become a major challenge in process technology. ”In order to avoid low-start-voltage components, For the problem of high leakage current, it is also necessary to use a design with double starting voltage to apply components with low starting voltage to circuits that require high speed, while using components with high starting voltage to general circuits. The problem of reducing leakage current β Generally speaking, in the traditional process, it is often necessary to use several masks to form the channel area required by the dual starting voltage circuit, so it is much more complicated than the process of a single starting voltage circuit. "In the research of Z. Chen et al .:" 0.18 μιη Dual Vt MOSFET Process and Energy-Delay Measurement "(IEDM Tech · Dig" p. 851, 1996), there is a related introduction to this process. Therefore 'form in tradition' The complex process required for the double-start voltage circuit has higher manufacturing steps and costs, and currently requires a more simplified process To improve the applicability of the double-start voltage circuit. "Purpose of purpose and overview: Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (read the precautions on the back before filling this page). The object of the present invention is to provide a Method for forming electric magic circuit with double starting. Another object of the present invention is to provide a method for forming electric dust circuit with double starting, which uses a more simplified manufacturing process to reduce production costs. Standard (CMS) A4 specifications_ (210X297 mm) 434835 A7 B7 5. Description of the invention () and increase the speed of mass production. Another object of the present invention is to provide a method for forming a circuit with a dual starting voltage for application to In the manufacturing process of a complementary metal-oxide-semiconductor with a double starting voltage, the present invention provides a method for forming a double starting voltage circuit on a semiconductor substrate, the substrate having a first region, a second region, and a first region. Three regions. The method of the present invention may include the following steps: firstly doping a first type ion into the first region, the second region, and the third region; and Then doping the second-type ions into the first region and the second region, the second-type ions and the first-type ions are used to generate different-type electrical ions in the substrate, so as to form a double-start voltage circuit. The above-mentioned first region may be a P-type metal-oxide-semiconductor field-effect transistor region, the above-mentioned second region may be a low-start-voltage N-type metal-oxide-semiconductor field-effect transistor region, and the third region may be It is an N-type metal-oxide-semiconductor half-effect transistor region with a high starting voltage. It can further form transistors on the first region, the second region, and the third region. (Please read the precautions on the back before filling this page ) Brief description of the printed layout of the staff consumer cooperative of the Central Standards Bureau of the Ministry of Economic Affairs: Figure-shows a cross-sectional schematic diagram of the semiconductor substrate of the present invention, which has a second region, a third region, and a third region. The second and second figures show schematic cross-sectional views of the present invention doped with the first type ions to the first region, the second region, and the second region. No. i: 圊 shows that the present invention is doped with 1 type 2 ions to No.-_ region and this paper size applies Chinese national standard (CNS > A4 specification (2Ϊ0 ×: Z97 mm) 434835 A7 B7 V. Description of the invention (No. The schematic diagram of the cross section in the second region of the four figures. Shows the schematic diagram of the cross section of the first, second, and third regions of the transistor formed in the present invention. The details of the invention printed by the Central Standard and Consumers Cooperative of the Ministry of Economic Affairs Said basket-L. The present invention provides a method for forming a complementary metal-oxide-semiconductor half-field-effect transistor circuit with a double starting voltage, which can be used to manufacture a circuit with a double starting voltage without using an additional photomask. Channel regions with different doping concentrations can use the process of doping differently-shaped electrical ions to form partial ions that cancel each other out, and get the desired exposure in different regions, thereby reducing the burden on the process and production. The cost of the method of the present invention can be used to form a plurality of regions with different electrical properties and doping concentrations on a semiconductor substrate. The process of the p-type metal-oxide-semiconductor field-effect transistor region, the N-type metal-oxide-semiconductor field-effect transistor region with a low initial voltage, and the N-type metal-oxide-semiconductor half-field-effect transistor region with a high initial voltage are taken as examples to illustrate the invention For those who are familiar with this field, those skilled in the art can apply the method of the present invention and make equivalent substitutions to form different doped regions. The details are not repeated here. See the first figure, first provide a semiconductor Substrate 10 'General application is to use silicon material' crystal orientation substrate, but also can choose different substrates with different crystal orientations or materials for different applications. Substrate 10 has isolation π A. This operation, Separate the area 12 to isolate each component area 'to provide the independence of individual components. Please read the precautions on the back. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm). ^ 34835 A7
五、發明説明（） 離區域12可為如圓中所示的場氧化區，或羌使用其他的隔 離方式，例如溝渠隔離等；隔離區域12將基材10隔離為 第一區域10a、第二區域及第三區域i〇c。 本實施例中，第一區域10&係用以做為形成P型金氧 半場效電晶體之區域，第二區域1 〇b係用以做為形成低起 始電壓之N型金氧半場效電晶體之區域，而第三區域1〇C 則用以做為形成高起始電壓之N型金氧半場效電晶艘之區 域。用以形成各區所需的N型丼或P型井區，則為基材10 上已形成之區域，N型井用於形成P型金氧半場效電晶艘 而P型井則用於形成N型金氧半場效電晶體’至於形成N 型井或P型井之摻雜或離子植入製程則不多做介紹。 參見第二圖所示’摻雜第一型離子至第一區域10a、第 二區域10b、及第三區域之中，以本例而言，可使用全 面性離子植入的方式，植入第一型離子至基材10之中’第 —型離子可使用用以形成p型摻雜之離子、如含硼之離子 或BF2離子等，以調整N型電晶體區，也就是第二區域10b 及第三區域l〇c的起始電壓。第一型離子之植入能量可約 為5KeV至150KeV之間，而其劑量約為lEllatoms/cm2至 1E 1 4 atoms/cm2 之間。 經濟部中央標準局員工消費合作杜印製 (請先閲讀背面之注意事項再填寫本瓦) 接著摻雜第二型離子至第一區域及第二區域l〇b 之中，第二型離子可使用相對於第一型離子而言，用以於 基材10内產生相異型電性之離子’以形成部分離子在電性 上相抵消的效果，第二型離子可使用用以形成N型摻雜的 本紙乐尺反適用中國國家標準（CNS) A4規格（210X297公釐） A7 —---------------B7__ 五、發明説明（） 離子’如含填之離子等，並同樣可使用離芋植入的方式加 以摻雜。 為了避免第三區域l〇c受到掺雜，可使用一覆蓋層14 於第三區域l〇c之上，如第三囷所示，以防^ n型離子之 進入。覆蓋層可使用一光阻層，先形成光阻層於基材上後， 再以微影製程定義所須保留的區域，再使用光阻的顯影過 程將第一區域10a及第二區域1〇b上的光阻層去除，即得 到一覆蓋於第二區域l〇c上的光阻層14。 而第二型離子之植入能量約為 20KeV至200KeV之 間’其劑量則約為lEl2atoms/cm2至5E14atoms/cm2之 間’由於第二型離子相對於第一型離子而言，為電性相異 之離子’因此可於第二區域1〇b内產生抵消第一型離子的 效果’而調降其起始電壓，以做為形成低起始電壓之N型 金氧半場效電晶體之區域；並於P型電晶體區内，也就是 第一區域10a中，在較深的植入深度下，形成防随穿的區 ^(punchthrough stopping region)16 β 藉由上述之方法，即可於基材上形成具有雙重起始電 壓之電路所需的摻雜區，可應用於互補式金氧半場效電晶 體電路之製作，而不需使用額外增加的光罩。 (請先閲讀背面之注意事頃再填寫本頁) 經濟部中夬標準局貝工消費合作社印装 對晶 步電 一成 進形 可以 並， 示 所 程 製 的 體 晶 •Γ1 成 形 行 進 材 基 體 域 區 第 於 2 2 及 圖區 四二 第第 如L' 了 助 幫 以 libzr 於 用 4-°-」 僅 上 如 明 二 之J C 施 10實 域佳 區較 三一 第以 及明 、發 Ob本 本紙張尺度適用中國國家梯準（CNS ) Α4说格（210X297公楚） 4 3 4 g 5 - A7 B7 五、發明説明（） 解本發明之實施，非用以限定本發明之精神，而熟悉此領 域技藝者於領悟本發明之精神後，在不脫離本發明之精神 範圍内，當可作些許更動潤飾及等同之變化替換，其專利 保護範圍當視後附之申請專利範圍及其等同領域而定。 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消费合作社印製 9 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）V. Description of the invention () The isolation region 12 may be a field oxidation region as shown in the circle, or other isolation methods such as trench isolation are used; the isolation region 12 isolates the substrate 10 into a first region 10a and a second region. Area and third area ioc. In this embodiment, the first region 10 & is used as a region for forming a P-type metal-oxide half field effect transistor, and the second region 10b is used for forming a N-type metal-oxide half-field effect with a low initial voltage. The region of the transistor, and the third region 10C is used to form an N-type metal-oxide-semiconductor field-effect transistor with a high starting voltage. The N-type plutonium or P-type well area required to form each area is the area already formed on the substrate 10. The N-type well is used to form a P-type metal-oxygen half field effect transistor and the P-well is used to Forming N-type metal-oxide-semiconductor field-effect transistors' As for the doping or ion implantation process of forming N-type or P-type wells, I will not introduce more. Referring to the second figure, 'doping the first type ions into the first region 10a, the second region 10b, and the third region, for this example, a comprehensive ion implantation method can be used to implant the first The first type ions can be used in the substrate 10 to form a p-type doped ion, such as a boron-containing ion or a BF2 ion, to adjust the N-type transistor region, that is, the second region 10b. And the starting voltage of the third region 10c. The implantation energy of the first type ions may be between about 5 KeV and 150 KeV, and the dosage is between about 1 Ellatoms / cm2 and 1E 1 4 atoms / cm2. Printed by the staff of the Central Standards Bureau of the Ministry of Economic Affairs for consumer cooperation (please read the notes on the back before filling in this tile), and then dope the second type ions into the first and second regions 10b. The second type ions can be Compared with the first type ion, the ion type used to generate different types of electrical ions in the substrate 10 is used to form the effect of partially offsetting the ions. The second type ion can be used to form the N type dopant. Miscellaneous paper rulers apply Chinese National Standard (CNS) A4 specifications (210X297 mm) A7 —--------------- B7__ 5. Description of the invention () Ion 'if included Ions, etc., and can also be doped using the method of ion implantation. In order to prevent the third region 10c from being doped, a cover layer 14 may be used on the third region 10c, as shown in the third embodiment, to prevent the entry of n-type ions. The cover layer can use a photoresist layer. After the photoresist layer is formed on the substrate, the area to be retained is defined by the lithography process, and then the first area 10a and the second area 1 are developed using the photoresist development process. The photoresist layer on b is removed to obtain a photoresist layer 14 covering the second region 10c. The implantation energy of the second type ion is about 20KeV to 200KeV, and its dose is about 1El2atoms / cm2 to 5E14atoms / cm2. Because the second type ion is an electrical phase relative to the first type ion The foreign ion 'can therefore produce the effect of canceling the first-type ion in the second region 10b' and lower its initial voltage as a region for forming a N-type metal-oxygen half field effect transistor with a low initial voltage ; And in the P-type transistor region, that is, in the first region 10a, at a deeper implantation depth, a punch-through stopping region 16 β can be formed by the above method, The doped regions required to form a circuit with a double starting voltage on the substrate can be applied to the fabrication of complementary metal-oxide-semiconductor half-field-effect transistor circuits without the need for an additional photomask. (Please read the notes on the back before filling out this page) Printed by the Ministry of Economic Affairs, China Standards Bureau, Shellfish Consumer Cooperative, and can be integrated into the crystal step electricity, showing the volume of the crystals made by the process • Γ1 Forming material matrix The domain area is at 2 2 and the map area is at the second place as L '. It helps to use libzr to use 4- °-"Only the JC application of the Ming Dynasty is 10. The real area is better than the Sany area and Ming and Fat Ob. The size of this paper is applicable to the Chinese National Standard (CNS) A4 (210X297) 4 3 4 g 5-A7 B7 V. Description of the invention () Explain the implementation of the invention, not to limit the spirit of the invention, but to be familiar with After realizing the spirit of the present invention, those skilled in this field can make minor modifications and equivalent changes without departing from the spirit of the present invention. The scope of patent protection shall be the attached patent scope and its equivalent fields. It depends. (Please read the precautions on the back before filling out this page) Printed by Shellfish Consumer Cooperatives, Central Bureau of Standards, Ministry of Economic Affairs 9 This paper is sized for China National Standard (CNS) A4 (210X297 mm)