TW434775B - Failure mode analysis method of automatic wafer test - Google Patents

Abstract

The present invention relates to an automatic failure mode analysis device and method for performing parametric tests to wafer products in a semiconductor manufacturing process. The failure mode analysis device can receive N test results obtained from sampling and performing N test items to the wafers in one lot. The N test results is expressed by an N-order test result vector, wherein the I-th element of the test result vector represents a failure ratio of the I-th test item. Then the N-order test result vector is multiplied with one NxN-order transform matrix in the failure mode analysis device to obtain a N-order failure mode vector, wherein the I-th element of the failure mode vector represents a ratio of the I-th failure mode. With the device and method, it is able to expand the features of assembling analysis and failure cause to products of all lots, thereby compiling a statistical and comprehensive data, and obtaining the correlation of the functional failure mode, including the cause of the manufacturing machine, the wafer and the lot.

Description

Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, 434775 2831twf.doc / 006 A 7 i? 7 V. Description of the Invention (/) The present invention relates to a device and method for identifying failure modes, and in particular, to a device for identifying failure modes. In the manufacturing process, an automatic failure mode identification device and method for wafer acceptance test (Wafer Acceptance Test, WAT for short) performed on wafer products. In the semiconductor process, there are many factors that affect the availability of the manufactured product. Therefore, when designing the circuit, you must consider the test requirements after the production is completed, and add test points or test structures in advance. When the wafer manufacturing is completed, The test items are WAT data tests. The test results can evaluate the problems that may occur during the manufacturing process. However, because of the large number of products, it is impractical to complete all the test items for each finished product. 1 A good practice is to conduct sampling tests in each lot of products, that is, in a batch. A certain percentage of samples are selected from the product, all items are tested, and the problems that may occur during the process are analyzed according to the test results, and the results are pushed to all products in the same batch using statistical methods. Kerf macro is a kind of evaluation method. The method is to add a structure for data testing to the notch between the dice on the wafer, so that the wafer area can be effectively used without occupying production. The area of the wafer coming out. Collecting and evaluating parametric test data obtained from wafer qualification tests using nick test structures is a critical step in diagnosing the health-of-line of the production line and identifying process failures. WAT data is also necessary to provide supplementary information on the analysis of errors in functional tests. The principle of the notch test structure is to sample several papers in all product batches. Paper standards are applicable to the national standard (CNS) Λ4 regulations (2 丨 0X29h > ^), ys T service (锖 read the precautions on the back before reading) (Fill in this page)

Printed by the Central Bureau of Standards of the Ministry of Economic Affairs and other consumer cooperatives 4347? | 2831twf.doc / 006 A7 B7 V. Description of the invention (2) According to the test, the results are extended to all cases. However, because the amount of data obtained on the production line is extremely large, only a small amount of data can be analyzed in detail by the data testing engineer. In general, only the trend of each individual test item is tracked without evaluating the entire test average Combination of failures, but the combination of failure patterns (patterns) can usually clearly point out special process errors, and even, in many cases, test items can be filtered from each other. Based on the above discussion *, it is known that the practice of data analysis by the data test engineer has the following disadvantages: 1. It only tracks the problems of a single test item, and cannot make full use of the data obtained from the test. 2. It is impossible to analyze the correlation between the data obtained from the test and the machine, wafer, and batch produced. 3. Unable to use mathematical tools to make fuller use of data. Therefore, the main purpose of the present invention is to provide an automatic wafer test failure mode identification device and method, which can expand the combination analysis and failure cause characteristics to all product lots, and can compile statistical comprehensive data, And to get the correlation of functional failure modes, including the basis for production equipment, wafers, and batches, so that the availability of the WAT data obtained can be improved, and it is a powerful tool that can strengthen production. In order to achieve the above and other objectives of the invention, the present invention proposes a failure mode identification device and method for automated wafer testing. The failure mode identification device can accept N tests obtained by performing N test items on a batch of wafer samples. As a result, after processing by the failure mode recognition device, a paper size is output to apply the National Solid State Standard (CNS) Λ4 specification (2IOX297 public) I — — — —J .—— (l · 装 ———— Order .--- (Line (Jing first read the notes on the back and then fill out this page) Printed by the Central Standards Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 434775 2831twf, doc / 006 A7 Η 7 V. Description of the Invention (>) A failure mode is the identification result of the base. The processing method of the failure mode identification device is to 'represent the N test results by an N-th order test result vector after receiving the N test results, where the first The i element represents the failure ratio of the i-th test item, and then the N-th order test result vector is multiplied by an N × N-th order transformation matrix inside the failure mode identification device to obtain an N-th order failure mode vector. The i-th element of the failure mode vector represents the proportion of the i-th failure mode, and the failure mode vector is the recognition result. According to a preferred embodiment of the present invention, the failure mode recognition device can further accept a failure mode setting. The input is used to set the transformation matrix. In order to make the above and other objects, features, and advantages of the present invention more obvious and understandable, a preferred embodiment is given below, and will be described in detail with the accompanying drawings as follows : Brief description of the figure: Figure 1 is the failed spectrum obtained from the WAT data test. Figures 2A and 2B are two sub-spectrums of the failed spectrum of Figure 1. Figure 3 is based on the failure mode. Spectrum. Figure 4 is an example of vector transformation in a three-dimensional space. Figure 5 is an example of a 5x5 transformation matrix multiplied by a fifth-order failure vector. Figure 6 is a block diagram of the failure mode identification device of the present invention. The diagram is a schematic flow chart of the failure mode identification method of the present invention. Fig. 8 is a part of the authenticity table of the DRAM wafer test example. This paper standard is applicable to the Chinese National Standard (CNS) Λ4 regulation. Broadcast (2 丨 OX 297 males) ---; --lr --- ^ 1 pack ------ order ^ -------, line (诮 first read the note on the back before filling in this Page) Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Zhengong Consumer Cooperative, 4347? § 2831twf .doc / 006 A 7 B7 V. Description of the invention (¥) A brief description marked in the drawing: 60. Batch products are tested for WAT data of N test items, and the percentage of test failure rates obtained from the N test items is arranged in a fixed sequence. The N test items are used as the horizontal axis, and the failure rate of each test item is reported as A graph is drawn on the axis, which can be used as the fail spectrum of this batch of products. Please refer to Figure 1 for this failed spectrum. This failed spectrum represents the status of the overall test data of this batch. The purpose of the analysis is to separate the spectrum from the problems of individual processes. According to the definition of the notch test structure, a special process problem will cause a specific combination of failure peaks, which can be regarded as sub-spectnim. Therefore, for a special process problem, a sub-spectrum can be separated, and this process problem can be regarded as a fail pattern. If there are N failure modes, N sub-spectrums can be separated, as shown in Figure 2A and Figure 2B shows two graphs of the sub-spectrum. Therefore, the overall failure spectrum is the superposition of all weighted sub-spectrums, which can be expressed as follows: a 1 .pat 1 + a2 .pat2 + ... + aN.patN = overall failure spectrum where patl to patN represent N failure modes, and al to aN is the contribution of N failure modes to the overall failure spectrum, that is, its addition coefficient. Converting the failed spectrum based on the test item into the spectrum based on the failure mode can more easily identify the process problems. As shown in Figure 3, a spectrum chart based on the failure mode is shown. Paper size applies to Chinese National Standards (CNS U Vision grid (210X297 public power) --- ^ — y --- ί Loading ------ Irl · —.--- Lacquer {Please read the precautions on the back first (Fill in this page) 434771 2831twf.doc / 006 A7 B7 V. Description of Invention (ί) Therefore, the purpose of the method for identifying patterns in automated wafer testing is to convert the spectrum based on the test items into the spectrum based on the failure mode. The graph 'can easily see the contribution of each unit spectrum to the entire failed spectrum' This process is just like the work of a spectrum analyzer. A good analogy is that the mass spectrometer can separate the mass spectrum into the separated spectrum of individual molecular objects. From a mathematical point of view, a failure spectrum can be regarded as a vector in N-dimensional space, and the percentage of failure is its coefficient, and a single test item is regarded as a unit vector of the Karst coordinate. The failure feature The pattern (characteristic fail pattern) can be regarded as the base vector of the transformed card-type coordinates. The failure pattern recognition device projects the vector of the failure spectrum onto the base of the failure characteristic pattern. After the failure mode is defined, the conversion work becomes a simple matrix operation, which can be simply applied to all the original data. The work of the test analysis expert or engineer is only to define the definition of the failure mode. To define the failure mode, This can be done using the correlation between the failure mode and the actual failure analysis results. Printed by the Employees' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (read the precautions on the back before filling this page). Figure 4 shows an example of vector transformation in three-dimensional space. The unit vectors are [100], [010], and [001] is a unit vector of card-shaped coordinates in a three-dimensional space, and the three vectors correspond to three test items, and a combined vector P can be obtained from the results obtained from the three test items. If 23, and C are the basis vectors of the failure mode, the purpose of the automatic failure mode identification device and method is to project the vector f onto the new unit vectors of gi and ^, and obtain the coefficients a, b, and And C, these three coefficients represent the contribution of each failure mode to the overall test result, that is, the impact of a certain process factor of the actual production line on the product yield. Therefore, the vector P can be expressed as the common solid state national standard (CNS) Αϋ size (2 丨 0X297-year-old) of the paper standard. The central standard bureau of the Ministry of Economic Affairs prints 434 ?? 2831twf.doc / 006 A7 B7 V. Invention Description (6)

F ^ a A- ^ b-B + C'C is implemented by technology. During the test process, N test items are performed, and the N test results obtained can be represented by a test result vector of order N. Among the test result vectors, The nth coefficient represents the percentage failure of the nth test item. Then according to the actual process, define N unit vectors representing failure modes. These failure modes represent new base vectors. In the defined failure modes, some failure modes can be the same as the test items. Basically, the separation process is The test result based on the test item is transformed into a failure mode vector based on the failure mode. In terms of actual conversion technology, this is just a multiplication operation of an N-th order vector and a matrix of size χχΝ. It does not use complex operations such as neural networks, and can be directly and directly operated by numbers. Get the desired result. Therefore, the failure percentage of the N test items can be regarded as a vector, and the failure spectrum representing the whole can be converted into a vector based on the failure mode 'through a simple matrix multiplication operation. For example, the vector F represents the test result based on the test item. To convert to the vector p based on the failure mode, it can be expressed by the following formula:

P = T xF where matrix T is the transformation matrix, which represents the relationship between the actual test items and process errors. The transformation matrix T is a sparse matrix composed of unit vectors, that is, the elements in it are either 0 or 1, and there are fewer elements with 1 in the matrix. A practical example of this conversion is shown in Figure 5. In this example, the Chinese National Standard (CNS) Λ4 Grid (2 丨 OX297) is applied to the 5x5 paper size --- M · J ---.- --L Pack ------ Order --ι .--- ^ ball (read the precautions on the back before filling this page) 434775 2831twf * d〇c / 006 A7 B7 Central Bureau of Standards, Ministry of Economic Affairs Printed by the Industrial and Consumer Cooperatives. 5. The transformation matrix of the invention description (7) is taken as an example, that is, the failure vector F representing the failure rate obtained from 5 test items is [0.2,0,0.4,0,0.1], which is calculated by the matrix. After multiplying with the transformation matrix T, the transformation vector p based on the failure mode can be obtained as [0.2,0,0,0,0.3]. As shown in FIG. 6, it is a block diagram of a preferred embodiment of a failure mode identification device for an automated wafer test of the present invention. The failure mode identification device 60 may accept test data obtained from the test results. The test data is a The group of data representing the percentage of failures of all test items. The main function of the failure mode identification device 60 is to process the input test data to obtain an identification result, and the processing process is the aforementioned matrix multiplication operation to obtain The identification results are based on failure mode data, which can be used to analyze potential problems in the process. The failure mode identification device 60 can accept the failure mode setting. This function is used to set the content of the conversion matrix of the failure mode identification device 60, such as changing the dimensions of the matrix according to the test items, and setting specific settings for different products or production processes. Transformation matrix. As shown in FIG. 7, it is a schematic flowchart of a preferred embodiment of a method for identifying a failure mode of an automated wafer test of the present invention. After the start, in step 71, a predetermined test item is performed for a production wafer. In step 72, the failure percentage of each item is obtained from the test items, and the test result is represented by a test result vector, and the coefficients in the vector are the failure percentages of the corresponding test items. In step 73, the test result vector representing the test result is sent to (please read the precautions on the back before filling out this page)-binding. The f-line paper size is applicable to the Chinese Standard for Homelessness (CNS) Λ4 saying grid ( 210X297 public loan) Employees' Cooperatives of the Central Standards Bureau, Ministry of Economic Affairs, Consumer Cooperatives, India 434W§ 2831twf.doc / 006 A7 B7 V. Description of the Invention (y) Failure mode identification device 60 for vector conversion. This conversion method uses the aforementioned matrix Multiplication method. Before the conversion, according to the relationship between the actual test items and the failure mode, the content of the conversion matrix is set by the test expert or engineer. In step 74, a failure mode vector based on the failure mode is obtained by the failure mode identification device 60 for analysis. In step 75, according to the obtained failure mode vector, an expert or a responsible engineer analyzes a possible problem in the manufacturing process, and improves the manufacturing process according to the analysis result, so as to improve the yield of the finished product. According to the discussion above, when the experts in test analysis set up a conversion matrix for the failure mode identification device or method according to the predetermined test items and process problems, in actual testing, the test results are obtained according to each test item. , The defect rate of each test item is represented by a vector, and this vector is multiplied with a transformation matrix to convert it into a vector based on the failure mode. It can analyze the product defect rate of that process step in the manufacturing process. The greatest impact can be used to improve the process. The following illustrates the practical application of the present invention with an example. The application example of the failure mode analysis of the wafer test is based on a test example of Dynamic Random Access Memory (DRAM). A wide kerf is used on this wafer, which can be added. Test structure for extensive data testing. Data testing on a wide cut on this DRAM wafer is mainly used to identify the front-end-of-connection structure under the first metallization layer (or Metal 0, M0 for short). line This paper size is applicable to China National Building Standard (CNS) A4 specification {2 丨) (Please read the back note ^^ before filling this page) • ------ Order -------- -The Central Laboratories of the Ministry of Economic Affairs, Central Labor Bureau, Consumer Cooperative Cooperative, printed 434776 2831twf.doc / 006 A7 B7 V. Description of the invention (7) Short circuit, leakage, and open circuit between structures). This is done by the so-called defect array (Rdefect array). A defect array is a structure that does not work and has a similar cell array. A simple DC data test can be performed on it to determine a short circuit or an open circuit. . Different defect arrays can be designed. Each different defect array omits some different structures to reduce the scope of the main cause of failure. The defect array has a curved and comb-shaped conductive layer, that is, the gate contact point (Gate Contact, GC for short) of M0 and the MOSFET. On these conductive layers, the conducting current versus voltage is simply measured by direct current. Characteristic curve. When the current from one end to the other end of the curved wire is blocked, it means that it is open. When the current between the curved wire and the comb wire exceeds an intrinsic leakage limit, it means It is a short circuit. At the same time, the integrated leakage current is measured by a conducting condition between the bias structure and the surrounding ground, and the polarity of the bias is changed to test the diode effect. The defect array can be divided into four types according to the structure composition. All tests are repeated on these four types of defect arrays. The difference between the four forms is as follows: The first form is without CD (Contact to Diffusion) and SS (Surface Strap), where CD refers to the contact between the bit line and the drain diffusion of the cell crystal, and SS refers to contact Polycrystalline silicon contact point to cell transistor source diffusion and trench storage capacitor; the second form is without CD and SS; the third form is without CD and SS; and the fourth form is both CD and SS. This paper size applies to China National Standard (CNS) A4 regulations (2 丨 0X2W public dream) *-i ---- I --- n ΙΊ V --- ----- rn --r --- (please Read the note on the back and fill in this page) 2831twf. Doc / 006 A7 B7 Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of Invention (/ 0) The above tests are performed in the presence or absence of CD or SS , Test it to be open or short between CD and SS. Similarly, the gc layer can be set to high or low potential * for M0 to M0 related tests; yes; ^ conductive. Based on the combination of test items and test conditions, a truth table can be established, and special process failure factors are mapped to certain test results. As shown in Figure 8, this is part of the truth table of the DRAM test example. In the truth table in the figure, each column is a test item, and the brackets after the test item are the test conditions. "+" Indicates a positive bias voltage, which indicates a negative bias voltage. "0N". Each row corresponds to a process failure factor, and the intersection of the rows with "x" indicates an expected failure, which means that when a test item is a failure, there is a corresponding process failure factor marked "X" in the space of the column of the test item All of them may cause this test item to fail. In contrast, when a process failure factor is established, corresponding test items marked with an “X” in the blank space of the line where the process fails should receive a failure result when tested. . For example, the 8th test item in the Shinji table is "GC to all (·)". According to the note of "X" in the table, it can be known that the process failure factors that cause this test item to fail are "gate Ox crash", "GC to GC short circuit (caused in the mode)" and "GC to M0 direct short circuit" and so on. In contrast, the sixth process failure factor in the table is "GC to CD short circuit (rectifier or diode) "), If the failure caused by this process failure factor, failure results will be obtained in the" GC to all (-, SS, CD) "and" GC to all (-'CD) "test items, in other The test items are normal. (Please read the notes on the back before filling this page) jA | 装 _

/ 1T

A The paper scale is applicable to the National Standard for Difficulties (CNS) A4 specification (210XN7 public office) Printed by the Consumer Cooperative of Zhongrong Standards Bureau, Ministry of Economic Affairs

S 2 8 3 11 wf * doc / 0 0 6 A7 B7 V. Description of the invention (/ ί) The truth table created according to the test items and process failure factors is equal to the set of unit failure vectors, so the truth table can be created directly The conversion matrix, in actual testing, as long as the failure vectors obtained from all the test items are passed through the pre-failure pattern recognition device or method described above, a vector based on the failure mode is obtained, that is, the obtained result is analyzed from the perspective of the process failure factor Test Results. The example of the defect array described above is only a partial set of the actual unit failure vector. To establish the entire conversion matrix, a complete wafer test process must also be considered. Therefore, according to the above device and method, after a batch of semiconductor wafers is completed, various tests are performed according to predetermined test items to obtain a test result vector composed of the failure percentage of each test item. The invented automatic wafer test failure mode identification device and method can convert the test result vector into a failure mode vector based on the failure mode, that is, isolate the influence of each process failure factor on the failure of this batch of wafers This is also a statistical overview of the entire batch of products. Test experts or engineers can easily know the characteristics of this batch of products. It can also be between the failure factor and the production machine, wafer materials, and batches. Find out their relevance and analyze which has the biggest impact on the quality of the product. From the above discussion, it can be seen that the failed pattern recognition device and method comparison method of the automated wafer test of the present invention has the following advantages: 1. The combination analysis and failure cause characteristics can be extended to all product lots. 2. Compile statistics overview data "This paper uses China National Standard Vehicle (CNS) Λ4 specification (2 丨 〇297297) (Please read the precautions on the back before filling this page)

1T Λ " 4341 "? 5 2831twf * doc / 006 Λ7 Η7 V. Description of the invention (/ 2) 3. The correlation of functional failure modes can be obtained, including the basis for production equipment, wafers, and batches. . Therefore, the availability of the WAT data obtained can be enhanced, and it is a powerful tool to enhance production. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make a few changes and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. (Please read the notes on the back before filling out this page) The Central Standards Bureau of the Ministry of Economic Affairs only prints and prints on the consumer cooperatives. The paper size is applicable to the Chinese household standard rate (CNS) Λ4 specification (210 X 2 men's money)

Claims (1)

1. A method for identifying a failure pattern of an automated wafer test, comprising the following steps: N test results obtained by performing N test items on a batch of wafer samples; and expressing the N test results as an N-order test result vector 'Where the i-th element of the failure vector represents the failure ratio of the i-th test item; providing a transformation matrix of order N × N; multiplying the transformation matrix by the test result vector of the order N to obtain a failure mode vector of order N; And the failure mode vector is based on a failure mode ', where the i-th element of the output vector represents the proportion of the i-th failure mode. > (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm)