434537鱷 B7434537 Crocodile B7
消 五、發明説明（1 ) 在傳統的靜態隨機存取記憶體之記憶單元中（參閱圖1)， 是使用兩條位元線（bit line)做讀冩的動作，也就是讀與寫 均是經由同樣的一對位元線來達成，是以在同一時間內只能 進行讀或寫的動作。因此，當欲設計具有同時讀寫能力之雙 埠(two-port)靜態隨機存取記憶體時，便需要多加入兩顆通 過電晶體（pass transistor)以及一對位元線（參閱圖2)，使 得記憶單元的面積大大地增加。如果我們能夠簡化記憶單元 的架構，使得一條位元線負責讀取的動作，而另一條負責寫 入的動作，則在設計雙埠靜態隨機存取記憶體時，記憶單元 便不需要多加入兩顆電晶體及一對位兀線，這樣記憶單元的 面積便會減小許多。傳統的靜態隨機存取記憶體之所以不採 用這種方法，是因爲無法達成寫入邏輯1的動作。此困難可 以由圖3中看出。圖中的MP3是寫入位元線WBL的驅動電晶 體。茲考慮記憶單元左側接點nl原本儲存邏輯0的情況，當 我們欲經由寫入位元線WBL寫入邏輯1至nl時，因爲通過電 晶體ΜΝ1Ϊ體效應（Body Effect)的關係，即使在完全無阻 力的情況下WBL最多也只能將nl的電壓拉高到VDD—V™的位 準，其中V™是MN1的臨界電壓。除此之外，基於此時由電晶 體MNI，MN2，以及MP3串聯所形成的比例（ratioed)邏輯架 構，又N型金氧半電晶體（NMOS)的電子遷移率（mobility) 大於P型金氧半電晶體（PMOS)的電洞遷移率，故使得η 1的 電壓很難被提升。因此，傳統的靜態隨機存取記憶體之記憶 單元當被使用於雙埠記憶電路時，在這兩項限制下不能達成 單位元線同時讀寫的寫入邏輯1動作。在本專利中，我們藉 本紙張尺度適用中國國家榇準（CMS > Α4規格（210X297公釐）5. Explanation of the invention (1) In a conventional static random access memory memory unit (see FIG. 1), two bit lines are used for reading and writing, that is, both reading and writing are performed. It is achieved through the same pair of bit lines, so that only reading or writing can be performed at the same time. Therefore, when designing a two-port static random access memory with simultaneous read and write capabilities, it is necessary to add two more pass transistors and a pair of bit lines (see Figure 2). So that the area of the memory unit is greatly increased. If we can simplify the structure of the memory unit so that one bit line is responsible for reading and the other is for writing, then when designing a dual-port static random access memory, the memory unit does not need to add two A transistor and a pair of bit lines, so that the area of the memory cell will be greatly reduced. The traditional static random access memory does not use this method because it cannot achieve the action of writing logic 1. This difficulty can be seen in Figure 3. MP3 in the figure is a driving transistor for writing the bit line WBL. Consider the case where the logic n 0 was originally stored on the left contact nl of the memory cell. When we want to write logic 1 to nl via the write bit line WBL, because of the body effect of the transistor MN1, Without resistance, WBL can only pull nl voltage up to the level of VDD-V ™, where V ™ is the threshold voltage of MN1. In addition, based on the ratiometric logic structure formed by the transistors MNI, MN2, and MP3 in series at this time, the electron mobility of the N-type metal-oxide-semiconductor (NMOS) is greater than that of the P-type gold The hole mobility of an oxygen semi-transistor (PMOS) makes it difficult to increase the voltage of η 1. Therefore, when a conventional static random access memory memory unit is used in a dual-port memory circuit, under these two restrictions, the unit logic line cannot be read and written simultaneously. In this patent, we apply the Chinese paper standard (CMS > Α4 specification (210X297mm))
合 作 社 印 製Printed by the cooperative
A7 B7 4 34537' 五、發明説明（2 ) 由將一N型金氧半電晶體的源極連接至寫入字元線，此靜態 隨機存取記憶體之記億單元電路提供了操作於1伏特之超大 型積電靜態隨機存取記憶體單位兀線同時讀寫的能力。在下 面幾段中，我們將介紹適用於單位元線同時讀寫之低電壓靜 態隨機存取記憶體的六顆電晶體雙埠記憶單元電路的架構， 並對其操作作一說明。 圖4(a)顯不了 一個適用於單位元線同時讀寫之低電壓靜態 隨機存取記憶體的六顆電晶體雙埠記憶單元電路。由圖中可 以看出，與傳統記憶單元電路不同的是，N型金氧半電晶體 MN3的源極端不再連接至地線（ground)，而改爲連接至寫入 字元線WWL。在此電路中，左側儲存點nl經由通過電晶體MN1 連接至寫入位元線WBL，其中Mn1是被寫入字元線WWL所控 制。而右側儲存點n2則是經由通過電晶體MN2而連接至讀取 位元線RBL，其中⑽^是被讀取字元線RWL所控制。藉著這 種電路型態，單位元線同時讀寫的功能即可被達成。類似之 前對傳統記憶單元的分析，在寫入邏輯1的過程中（參閱圖 4(b))，WBL仍然最多只能把nl的電壓拉高到Vdd—V™ ;但 是由於MN3源極端所連接的寫入字元線WWL此時的電壓爲 VDD，所以MNI，MN2，及外3的串聯結構不會有比例（ratioed) 邏輯的問題存在，nl的電壓便能很輕易地往Vdd—Vto上升。 當til的電壓超過某一臨界電壓之後，MN4會導通’ 1^2關閉， π2的電壓隨即降到0V，此時nl的電壓便因正迴授的機制而提 升到VDD，完成整個寫入邏輯1的動作。 —^1 1ϋ I —^1» ---nn -λ,—/l丨 F- - -- - - ' c (請先閱讀背面之注意事項再填寫本頁) •言 d 經 濟 部 智 慧 財 產 局 員 X 消 合 作 社 印 製 本紙張尺度適用t國國家操準（CNS)A4規格（210X297公釐） 經濟部中央標準扃員工消費合作社印裝 ,4 3^537* a? B7 五、發明説明（3 ) 爲了驗證適用於單位元線同時讀寫之低電壓靜態隨機存 取記憶體的六顆電晶體雙埠記憶單元電路的有效性，我們以 SPICE模擬了操作於1伏特下記億單元寫入動作的暫態分析。 模擬是採用〇.25μΙη CMOS製程技術，記憶單元電路中所有的 電晶體其寬度均爲〇.3μιη微米，長度均爲〇.25μπι微米，寫入 位元線和讀取位元線的寄生電容都假設爲O.lpF。圖5顯示了 其寫入動作之暫態分析結果。如圖中所示，我們考慮了所有 的四種寫入情況，它們分別是：（1) nl原本儲存邏輯0，而 現在欲寫入邏輯〇 (邏輯邏輯〇) ; (2) nl原本儲存邏輯0， 而現在欲冩入邏輯1 (邏輯〇—邏輯1) ; (3) nl原本儲存邏 輯1，而現在欲寫入邏輯1 (邏輯1~>邏輯1) ; (4) nl原本儲 存邏輯1，而現在欲寫入邏輯〇 (邏輯1—邏輯0)。以下詳述 這些暫態動作的情形與原理： (1 )邏輯0—邏輯0 :在寫入動作發生前（WWL=0)，WBL 爲Low，Mn^ON。因爲Mn^ON，所以當寫入動作開 始時，WWL由Low轉High，nl的電壓會跟隨WWL的電壓 而上升。當WWL的電壓大於MN1的臨界電壓V™時，MNi turns ON，此時因爲WBL是Low，所以會將nl放電；基於 MNl和MN3所形成的比例邏輯架構，nl的電壓在大部分寫 入週期內（WWL=1 )會維持在約0.15V左右。當寫入動 作結束，WWL由High變Low時，MNI的轉導 (transconductance)漸漸變小，結果因爲MNJ[]MN3的比 例邏輯結構，nl的電壓會升高。當WWL降至V™後，MNi turns OFF，nl的電壓便跟隨WWL的電壓逐漸下降至〇V， V - -I upl ^nt - - - FI^H mu d - Λ y 0¾ VI、 (請先閲讀背面之注意事項再填寫本頁) 1—~IJ -·=" --- 本紙張尺度適用中國國家標準（CNS ) Α4規格（2丨ΟΧ29*/公釐） 4 34.53 T® at B7 經濟部中央標準局貝工消费合作杜印製 五、發明説明（4 ) 完成邏輯〇-邏輯0的寫入動作·， (2) 邏輯0—邏輯1 :在寫入動作發生前（WWL=0)，WBL 爲ffigh ’ IVWmON。由於MN3爲ON，所以當寫入動作開 始時’ WWL由Low轉High，nl的電壓會跟隨WWL的電壓 而上升a當WWL的電壓大於MN1的臨界電壓時，MNt turns ON，此時因爲WBL是High，因此WBL也會開始對nl 充電’使nl的電壓向VDD—提升。由於nl電壓的上升 會親合（couple)至n2，使MN3的閛極，即n2，出現一峰 値大於VDD的突波，故nl的電壓也會因此出現一個超過 VDD—V™的突波。此後MP2 turns OFF，MN4 turns ON，使 n2的電壓降至〇V。最後MP1 turns ON，nl的電壓隨即被提 升至VDD，完成邏輯Ο—邏輯1的寫入動作。 (3) 邏輯1—邏輯1 :在寫入動作發生前（WWL=0)，WBL 爲High，MN3爲OFF。當WWL由Low轉High至超過MN1的 臨界電壓V™時，MN1 turns ON。因爲WBL爲High，而nl 的電壓原本亦爲High，所以nl的電壓不會有變動，而會 平穩地保持在VDD直到寫入週期結束。 - (4) 邏輯1—邏輯0 :在寫入動作發生前（WWL=0)，WBL 爲Low，MN3爲OFF。當WWL由Low轉High至超過⑽^的 臨界電壓V™時，Mn1 turns ON，nl的電壓隨即因WBL爲 Low而下拉，導致MN4 turns OFF，ΜΡ：ί turns ON ;這同時 使得MPl turns OFF，MN3 turns ON。與前述，邏輯0—邏輯 之情況相同，這時WWL經]VtNJirU充電，WBL經Mni 對ni放電。基於Mni和MN3所形成的比例邏輯架構，nl的 --叫-----H萍— 、 C (請先閎讀背面之注意事項耳填寫本頁) , iA7 B7 4 34537 'V. Description of the invention (2) By connecting the source of an N-type metal-oxide-semiconductor transistor to the write word line, the hundred million unit circuit of this static random access memory provides operation at 1 Volt's ability to read and write at the same time as a large-scale power storage static random access memory unit. In the following paragraphs, we will introduce the architecture of a six-transistor dual-port memory cell circuit suitable for low-voltage static random access memory that simultaneously reads and writes unit cells, and explains its operation. Figure 4 (a) does not show a six-transistor dual-port memory cell circuit suitable for low-voltage static random access memory that reads and writes unit cells at the same time. It can be seen from the figure that, unlike the conventional memory cell circuit, the source terminal of the N-type metal-oxide semiconductor transistor MN3 is no longer connected to the ground, but instead is connected to the writing word line WWL. In this circuit, the left storage point nl is connected to the write bit line WBL via the transistor MN1, where Mn1 is controlled by the write word line WWL. The right storage point n2 is connected to the read bit line RBL through the transistor MN2, where ⑽ ^ is controlled by the read word line RWL. With this circuit type, the function of reading and writing unit cell lines simultaneously can be achieved. Similar to the previous analysis of traditional memory cells, in the process of writing logic 1 (see Figure 4 (b)), the WBL still can only pull up the voltage of nl to Vdd-V ™ at most; but because the MN3 source terminal is connected The voltage of the writing word line WWL at this time is VDD, so the serial structure of MNI, MN2, and outer 3 will not have a ratioed logic problem, and the voltage of nl can easily rise to Vdd-Vto. . When the voltage of til exceeds a certain threshold voltage, MN4 will be turned on, 1 ^ 2 will be turned off, and the voltage of π2 will then drop to 0V. At this time, the voltage of nl will be raised to VDD due to the positive feedback mechanism, completing the entire write logic 1 action. — ^ 1 1ϋ I — ^ 1 »--- nn -λ, — / l 丨 F-----'c (Please read the notes on the back before filling out this page) • d Member of Intellectual Property Bureau, Ministry of Economic Affairs Printed by X Consumer Cooperatives. The paper size is applicable to National Standards (CNS) A4 (210X297 mm) of the Ministry of Economic Affairs, Central Standard of the Ministry of Economics, printed by employee consumer cooperatives, 4 3 ^ 537 * a? B7 V. Description of Invention (3) In order to verify the validity of the six-transistor dual-port memory cell circuit suitable for low-voltage static random access memory that reads and writes to the unit cell at the same time, we simulated the transient operation of the write operation of a billion-volt cell with 1 volt with SPICE. Analysis. The simulation uses 0.25μΙη CMOS process technology. All transistors in the memory cell circuit have a width of 0.3μm and a length of 0.25μm. The parasitic capacitances of the bit line and the read bit line are both Assume it is O.lpF. Figure 5 shows the results of the transient analysis of its write action. As shown in the figure, we have considered all four write situations, which are: (1) nl originally stored logic 0, but now wants to write logic 0 (logical logic 0); (2) nl originally stored logic 0, and now want to enter logic 1 (Logic 0—Logic 1); (3) nl originally stores logic 1, and now wants to write logic 1 (Logic 1 ~ > Logic 1); (4) nl originally stores logic 1, and now want to write logic 0 (logic 1-logic 0). The conditions and principles of these transient actions are detailed below: (1) Logic 0—Logic 0: Before the write action occurs (WWL = 0), WBL is Low and Mn ^ ON. Because Mn ^ ON, when the write operation starts, WWL changes from Low to High, and the voltage of nl will increase following the voltage of WWL. When the voltage of WWL is greater than the threshold voltage V ™ of MN1, MNi turns ON. At this time, because WBL is Low, nl will be discharged. Based on the proportional logic architecture formed by MN1 and MN3, the voltage of nl is in most write cycles. (WWL = 1) will be maintained at about 0.15V. When the writing operation is completed and the WWL is changed from High to Low, the transconductance of the MNI gradually becomes smaller. As a result, the voltage of nl will increase due to the proportional logic structure of MNJ [] MN3. When the WWL drops to V ™, MNi turns OFF, and the voltage of nl gradually decreases to 0V following the voltage of WWL. V--I upl ^ nt---FI ^ H mu d-Λ y 0¾ VI, (please first Read the notes on the reverse side and fill out this page) 1— ~ IJ-· = " --- This paper size applies to China National Standard (CNS) Α4 specification (2 丨 〇 × 29 * / mm) 4 34.53 T® at B7 Economy Printed by the Ministry of Standards and Technology of the People's Republic of China. 5. Description of the invention (4) Complete the writing operation of logic 0-logic 0, (2) Logic 0-logic 1: Before the writing operation occurs (WWL = 0) , WBL is ffigh 'IVWmON. Because MN3 is ON, when the write operation starts, 'WWL turns from Low to High, and the voltage of nl will increase following the voltage of WWL. A When the voltage of WWL is greater than the threshold voltage of MN1, MNt turns ON. At this time, because WBL is High, so WBL will also start to charge nl 'to make the voltage of nl increase to VDD—. Because the rise of the nl voltage will couple to n2, so that the peak of MN3, that is, n2, will have a spike 値 larger than VDD, so the voltage of nl will also appear a surge exceeding VDD-V ™. After that MP2 turns OFF and MN4 turns ON, reducing the voltage of n2 to 0V. Finally, MP1 turns ON, and the voltage of nl is then raised to VDD, completing the writing operation of logic 0-logic 1. (3) Logic 1—Logic 1: Before the write operation (WWL = 0), WBL is High and MN3 is OFF. When WWL goes from Low to High and exceeds the threshold voltage V ™ of MN1, MN1 turns ON. Because WBL is High, and the voltage of nl is also High, the voltage of nl will not change, but will be kept at VDD smoothly until the end of the write cycle. -(4) Logic 1—Logic 0: Before the write operation (WWL = 0), WBL is Low and MN3 is OFF. When the WWL goes from Low to High and exceeds the critical voltage V ™, Mn1 turns ON, and the voltage of nl is pulled down because WBL is Low, causing MN4 turns OFF, MP: TURN turns ON; this also makes MPl turns OFF, MN3 turns ON. As in the case of logic 0-logic, WWL is charged via VtNJirU, and WBL is discharged to Ni via Mni. Based on the proportional logic architecture formed by Mni and MN3, nl ----------- H Ping--, C (please read the notes on the back first and fill in this page), i
Is 本紙張尺度適用t囷阐家被準（CNS ) A4規格（210X297公釐）Is This paper size applies to the standard (CNS) A4 (210X297 mm)
434*537® a? _______B7 五、發明説明（5 ) 電壓在大部分寫入週期內（WWL=1)會維持在約0.15V 左右。.當寫入動作結束，WWL由High變Low時，MN1的 轉導漸漸變小，結果因爲MNi和MN3的比例邏輯結構，nl 的電壓會被升高。當WWL降至後’ MNl turns OFF，nl 的電壓便跟隨WWL的電壓逐漸下降至〇V，完成邏輯1— 邏輯〇的寫入動作。 由以上分析可知適用於單位元線同時讀寫之低電壓靜態隨機 存取記憶體的六顆電晶體雙埠記憶單元電路在寫入的四種情 況下均可正常工作。 經濟部中夬標準局員工消费合作社印裝 (請先閱讀背面之注意事項再填寫本頁) 與傳統八顆電晶體雙埠記憶單元電路來比較，適用於單 位元線同時讀寫之低電壓靜態隨機存取記憶體的六顆電晶體 雙埠記憶單元電路僅需六顆電晶體及兩條位元線，而八顆電 晶體雙埠記憶單元電路則需八顆電晶體及四條位元線。因 此，適用於單位元線同時讀寫之低電壓靜態隨機存取記憶體 的六顆電晶體雙璋sat單元電路比傳統八顆電晶體雙埠記憶 單元電路來得精簡許多― 本纸法尺度適用令國國家株準（CNS ) A4規格（2iOX297公羡） Α9 Β9 C9 D9 圖示說明： 圖1所示爲傳統六顆電晶體靜態隨機存取記憶體之記憶單 元電路的電路圖。 圖2所示爲傳統八顆電晶體雙埠靜態隨機存取記憶體之記 憶單元電路的電路圖。 圖3所示爲傳統六顆電晶體靜態隨機存取記憶體之記憶單 元電路在單位元線寫入邏輯1之動作下的示意圖。 圖4(a)和圖4(b)所示爲根據本發明之適用於單位元線同時 讀寫之低電壓靜態隨機存取記憶體的六顆電晶體雙埠記憶單 元電路的⑻電路圖（b)單位元線寫入邏輯1之動作示意圖。 圖5所示爲根據本發明之適用於單位元線同時讀寫之低電 壓靜態隨機存取記憶體的六顆電晶體雙璋記憶單元電路於操 作電壓爲1伏特時寫入動作之暫態分析。 (請先s讀背面之注意事項再行繪裝) 經漭部中央標準局員工消費合作社印製 一 n …« - II * 一«4- — s I- - I ^^1 I - --Λ^ -_ - I ^^1 m i . 本紙張尺度逍用中國國家·搮準（CNS ) Μ規格（210X297公釐）434 * 537® a? _______B7 V. Description of the Invention (5) The voltage will be maintained at about 0.15V for most of the write cycle (WWL = 1). When the writing operation is completed and the WWL is changed from High to Low, the transduction of MN1 gradually becomes smaller. As a result, the voltage of nl will be increased due to the proportional logic structure of MNi and MN3. When WWL drops to ‘MN1 turns OFF, the voltage of nl gradually decreases to 0V following the voltage of WWL, completing the writing operation of logic 1—logic 0. From the above analysis, it can be known that the six transistor dual-port memory cell circuits suitable for low voltage static random access memory of unit cell lines reading and writing at the same time can work normally in the four cases of writing. Printed by the Consumers' Cooperative of the China Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page). Compared with the traditional eight-transistor dual-port memory cell circuit, it is suitable for low-voltage static reading and writing of unit cell lines at the same time. The six-transistor dual-port memory cell circuit of the random access memory requires only six transistors and two bit lines, and the eight-transistor dual-port memory cell circuit requires eight transistors and four bit lines. Therefore, the six-transistor dual 单元 sat cell circuit suitable for low-voltage static random access memory with unit cell lines reading and writing at the same time is much simpler than the traditional eight-transistor dual-port memory cell circuit. China National Standard (CNS) A4 specification (2iOX297 public envy) Α9 Β9 C9 D9 Graphic description: Figure 1 shows the circuit diagram of the memory cell circuit of the traditional six-transistor static random access memory. FIG. 2 is a circuit diagram of a memory cell circuit of a conventional eight transistor dual-port static random access memory. FIG. 3 is a schematic diagram of a conventional memory cell circuit of a static random access memory with six transistors under the action of writing a logic 1 to a unit cell line. FIGS. 4 (a) and 4 (b) are schematic circuit diagrams of a six-transistor dual-port memory cell circuit suitable for low-voltage static random access memory for simultaneous reading and writing of unit cell lines according to the present invention (b) ) Schematic diagram of unit cell writing logic 1. FIG. 5 shows a transient analysis of a write operation of a six-transistor dual-chip memory cell circuit suitable for low voltage static random access memory for simultaneous reading and writing of unit cell lines according to the present invention when the operating voltage is 1 volt . (Please read the precautions on the back before drawing.) Printed by the Consumer Standards Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs of the People's Republic of China printed a n… «-II *« 4- — s I--I ^^ 1 I---Λ ^ -_-I ^^ 1 mi. The size of this paper is in accordance with China National Standards (CNS) M specifications (210X297 mm)