TW432722B - A method for forming three dimensional poly-silicon layer on semiconductor chip - Google Patents

Abstract

A method for forming a three-dimensional poly-silicon layer on a semiconductor chip and further increasing the surface area of the ONO dielectric layers thereupon is provided in the present invention. The semiconductor chip includes a substrate, a first poly-silicon layer with an approximately square cross section provided on the predetermined region of the surface of the substrate, and a sacrificial layer provided over the first poly-silicon layer. The method first forms a dielectric layer with a thickness higher than the top of the sacrificial layer on the surface of the semiconductor chip. A CMP process is then conducted to completely remove the dielectric layer on the sacrificial layer, and horizontally removes the dielectric layer on the surface of the substrate downwards to a predetermined thickness. Thereafter, the sacrificial layer is completely removed such that a hole is constituted by the top surface of the first poly-silicon layer and the adjacent surrounding dielectric layer. A second poly-silicon layer is formed on a specific region of the surface of the first poly-silicon layer to fill up the hole such that the second poly-silicon layer can electrically connect the first poly-silicon layer. This completes the fabrication of the three dimensional poly-silicon layer and increases the contact area between the ONO dielectric layer and control gate subsequently formed upon the three dimensional poly-silicon layer.

Description

I. Description of the invention (I) 丨 Field of invention; The present invention provides a method for forming a polycrystalline silicon layer in a three-dimensional space, and 1 particularly a method for forming a floating gate on a semiconductor wafer. I background note in the application of integrated circuits' erasable and programmable read only memory (.EPROM), erasable and programmable read-only memory (eiectrjcaiiy erasable programmable read only memory (E2PROM) and flash memory are both non-volatile memory, which uses different threshold voltages (threshold voltage) to control The idle pole switch can achieve the function of memory, so that the data stored in the memory will not be affected by the power interruption. a The interrogation structure of volatile memory is generally designed as a stack-gate, which contains a floating gate (£ 丨 〇 ^ 丨 7 ^ 宫 ^ 6 for charging). ), A dielectric layer of a 0N0 (oxide-nitride-oxide) structure, and a control gate (contr01 gate) for controlling data access. So the principle of memory #: m capacity: store, sense λ charge in the stack. "V. Description of the invention (2) |. I Please refer to Figure 1 to Figure 4, Figure 1 to Figure 4 for making a stacked i. A schematic cross-sectional view of the method of the intermediate electrode 36. The method of making a stacked gate 36 of a non-volatile memory I is known, which is to make a pair on a semiconductor wafer 10 | 丨 twin cell gate As shown in Figure 1, 'the semiconductor wafer 10 includes 1 with a silicon substrate 12 and at least two field oxide layers 14 are provided on the silicon substrate 12' and the second gate i 1 oxide layer 16 is provided on the surface of the silicon substrate 12 The predetermined areas are all located between two adjacent i: field oxide layers 14; two first polycrystalline silicon layers 18 are provided on each of the gate oxide i_I layers 16 and two silicon nitride layers 20 respectively. It is set on each of the first polycrystalline silicon layers 1 8 |. 丨 As shown in FIG. 2, the conventional method is to first perform an ion implantation process on: the non-gate oxide layer 16 and the field oxide layer 1 4 The covered silicon substrate is doped with hetero ions under the surface of the substrate 2 and then subjected to a high-temperature oxidation process so that the doped ions are activated and diffused to form a predetermined depth of ion. The implantation layer 22 is used as a drain or a source. At the same time, the surface of the stone substrate 12 in the area of each ion implantation layer 22 will grow. —The thermal oxide layer_24 'is used as a buried drain and source (BD / BS). As shown in FIG. 3, the silicon-nitrogen layer 20 is then removed and removed to the semiconductor Two second and second polysilicon layers 26 are formed on predetermined areas on the surface of the wafer 10. Each of the first polycrystalline silicon layers 18 and the second polycrystalline silicon layer 26 overlying them form a three-dimensional structure. The space polycrystalline silicon layer 28 is used as; 丨 the floating gate of the non-volatile memory. 丨

Page 6! V. Description of the invention (3) 丨 As shown in Figure 4, a dielectric layer composed of 丨 ONO (oxide-nitride-oxide) structure is subsequently formed on the surface of each floating gate. It includes a first oxide layer (not shown), a nitride layer (not shown) provided on the first oxide layer, and a second oxide layer (not shown) provided on the nitride layer. Finally, a third polycrystalline silicon layer 32 is formed on the surface of the semiconductor wafer 10 so as to cover the surfaces of the dielectric layer 30 and the thermally-cured layer 24 in a predetermined area, and is used as the non-volatile memory. Control gate of the body. i: In this way, the floating gate, the dielectric layer 30, and the control gate constitute the stacked gate 36 of the non-volatile memory, and the two stacked gates 36 are located between the two field oxide layers. Then, a double-lattice gate is formed. When a high voltage is applied to the control of the stacked gate, the drain will experience carrier multiplication.

• I (Carrier Multiplication) phenomenon generates thermoelectrons. Among them: a part of the hot electrons will cross the gate oxide layer 16 and be injected into the | I floating gate, so that the floating gate will be charged. And these charges provided by the hot electron i will be trapped in the floating | because of the surrounding dielectric layer 30 and the gate oxide layer 16, and the data storage is completed. ;

I

| I Because the conventional manufacturing method is a high-temperature thermal oxidation process, a thermal oxidation layer 24 is formed on the surface of the silicon substrate 12 for use as a BD / BS. This will cause the thickness of the thermal oxide layer 24 to be clamped by the nitrogen silicon layer 20 at both ends to produce a bird's beak phenomenon, which will cause the thickness of the thermal oxide layer 24 to become abnormal. It is non-uniform and will damage the lattice structure on the surface of the silicon substrate 12, which greatly affects the reliability of the stacked gate 36 of the semiconductor wafer 10. In addition, used to shape |

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V. Explanation of the invention (4) 丨 The high-temperature thermal process that forms the thermal oxidation layer 24 will also excessively penetrate into the ions doped in the drain and source, thereby shortening the stacked gate 36 below relatively. I! Channel length can even cause abnormal electrical punching between the drain and source, which seriously affects the electrical performance of the stacked gate 36 and reduces the overall semiconductor product. Process yield (yieldrate). i. Summary of the Invention I Therefore, the main object of the present invention is to provide a method for fabricating a three-dimensional space i: a polycrystalline silicon layer to prepare a non-volatile memory stacked gate. In this way, not only the uneven thickness i BD / BS caused by the high temperature thermal process can be avoided, but also each i formed on the abundant conductor wafer can be accurately controlled; the channel length of the stacked gate and the BD / PS Thickness, which effectively reduces the size of each component, and increases the reliability of these components. In addition, this post 丨!

Ming Zhi's method for making polycrystalline silicon layers in three-dimensional space is more suitable for semiconductor wafers.

-I forms a three-dimensional three-dimensional stacked stack pole, which further increases the following: the contact area of the 0 N 0 dielectric layer formed on the control gate and the control gate, so that the stack gate's pole-folding ratio (Gate coupling ratio, GCR) is increased by about 65 to 70%, which greatly improves the electrical performance of these semiconductor products. i Brief description of the diagram i Figures 1 to 4 are cross-sectional views of a conventional method for manufacturing a stacked gate 丨: Intention. Figures 5 to 9 show how to form a three-dimensional polycrystalline silicon layer in the present invention.

笫 Page 8 '^ 7 ^ V. Description of the invention (5)! Fig. 10 is a schematic diagram of the structure of a stacked gate formed on the semiconductor wafer shown in Fig. 9 α: Figs. 11 to 10 are schematic diagrams of another method for forming a three-dimensional polycrystalline silicon 1 layer of the present invention. Description 40 semiconductor wafer 42 substrate 44 field oxide layer 46 gate oxide layer: 48 first polycrystalline silicon layer 50 sacrificial layer 52 doped region 54, 72 dielectric layer 5 6 '76 hole 58> 78 second polycrystalline silicon layer 60 > 80 Polycrystalline silicon layer 62 Onion structured dielectric layer: 64 Third dielectric layer 66 Stacked gate 74 Protective layer For a detailed description of the invention, please refer to FIG. 5 to FIG. 9 FIG. 5 to FIG. Schematic diagram of the method of polycrystalline silicon layer 60. The method of the present invention provides a method for forming a polycrystalline silicon layer 60 in a three-dimensional space on a semiconductor wafer 40. The method is used as a floating gate 0 of a non-volatile memory. Contains a substrate 42. At least two field oxide layers 4 4 are provided on the substrate 42. A second gate oxide layer 4 6 is provided on a predetermined 1¾ area on the surface of the substrate 4 2 and is located in a section between the adjacent field emulsified layer 4 4 Polycrystalline silicon layer approximately square 48

Page 9: V. Description of the invention (6) 丨 respectively disposed on the surface of the second gate oxide layer 46, two sacrificial layers 50 are disposed directly above each first polycrystalline silicon layer 48, and a plurality of doping The regions 5.2 are respectively provided on the surfaces 42 of the substrate 42 on the left and right sides of the first polycrystalline chip layer 48 and serve as a source and a drain of the floating gate. The substrate 42 is composed of a silicon element, and the sacrificial layer 50 is composed of a nitrogen silicon compound. As shown in FIG. 6, the method of the present invention first uses a high-density plasma chemical vapor deposition (high-density). plasma chemical vapor deposition (HDP CVD) method, a dielectric layer 54 made of silicon dioxide is deposited on the surface of the semiconductor wafer 40 so as to cover the substrate 42 and the sacrificial layer 50 and to form a dielectric on the surface of the substrate 42 The thickness of the layer 54 is greater than the height of the top of the sacrificial layer 50. As shown in FIG. 7, a chemical mechanical polishing (CMP) process is then performed to completely remove the dielectric layer 54 ′ above the sacrificial layer 50 and simultaneously remove the dielectric layer on the surface of the substrate 42 downward. 5 4 to a predetermined thickness. As shown in FIG. 8 ', then the sacrificial layer 50 above the first polycrystalline silicon layer 48 is completely removed, so that the top surface of each of the first polycrystalline silicon layers 4δ and the dielectric layer 5 4 surrounding it are formed separately—holes 5 6 ^ As shown in FIG. 9, a second polycrystalline silicon layer 5 is formed on a specific area of the surface of the conductor wafer 40 to fill the holes 5 6, and the second polycrystalline silicon layer 5 is formed. 8 is obtained: the first-polycrystalline stone layer 48 is used as a "floating interrogation pole" to complete the production of three = polycrystalline stone layer 60. It is located on the second polycrystalline sand, on both sides of 48: The dielectric layer 54 is used as a buried drain or source (buried

ο 5. Description of the invention (7) drain / source, BD / BS) 0 I Please refer to FIG. 10 ′ FIG. 10 is a schematic diagram of the structure of the stacked gate 66 formed on the semiconductor wafer shown in FIG. 9. After the fabrication of the floating gate I is completed, a first oxide layer (not shown), a nitride layer (not shown), and a second oxide can be sequentially formed on the surface of each second polycrystalline silicon layer 58. Layer 丨 (not shown), and the three-layer structure forms a dielectric layer 6 2 having a 10N0 structure. I finally formed a third polycrystalline dream layer 1 2 364 on the surface of the semiconductor crystal moon 40, and used it as a control gate. Among them, the floating gate, the dielectric layer 6 2 | of the 0N 〇 structure, and the control gate form a stacked interlayer of non-volatile memory 6 6 'and located between the two field oxide layers 4 4 Two stacked gates 6 β are recombined; a twin cei 1 gate is formed to serve as the non-volatile memory: floating gate of the memory. The method of the present invention is based on a Λ- ^ aa Shi Xizhan 48 solid dielectric layer: 5 to 4 BD / BS 'so it is not necessary to use a thermal oxidation process to grow into a thermal oxidation i polycrystalline rhyme and ^ g 6. Therefore, i subsequently forms the first layer on the first polycrystalline layer 4 8; the polycrystalline pair j, and the surface of the polycrystalline layer in the three-dimensional space of i will face each other with the hole jg_5L ^ Ljli gauge.

1 . Therefore, the method of HDP CVD can be used to obtain effective control, so that each stack 3 fabricated on the semiconductor wafer 40 can be dreamed. In addition, in the present invention, the first _ polycrystalline silicon layer 4 is only surrounded by a dielectric layer 5 4 whose surface is flat using a CMP method, and then an etching process is used to form the first I. The description of the invention (8) I becomes A three-dimensional series of squats, which in turn increases the contact surface of the gates that are subsequently formed on it. "This makes it possible to use # 发 丨 明 方法 straight -1 pole one-coupling ratio (GCR) ) Can be increased to 65 ~ 70% 'It is very helpful to improve the electrical performance of semiconductor products.

Please refer to FIG. 10 ′, FIG. 16 to FIG. 16, and FIG. 11 to FIG. 16 are schematic diagrams of another method for forming a three-dimensional polycrystalline silicon layer 80 in the present invention. As shown in Fig. 10 |, "Another method for forming a three-dimensional space polycrystalline silicon layer 80 on a semiconductor wafer 40 according to the present invention" is to first use a high-density plasma chemical vapor deposition (HDP CVD) method on a semiconductor On the surface of the wafer 40, a dielectric layer 72 'composed of SiO2 is deposited so as to cover the substrate 42 and the sacrificial layer 50: square, and the thickness of the dielectric layer 72 formed on the surface of the substrate 42 is greater than that of the first layer. The thickness of the polycrystalline yarn layer 48 does not exceed the top height of the sacrificial layer 50. As shown in circle twelve, a wet etching process is then performed, using diluted argon fluoride (diUte: HF, DHF) or buffered oxygen silicon etching solution (buffere (i oxide etchef, I BOE)) as the etching solution, To remove the side edge of the top edge of the sacrificial layer 50: the dielectric layer 72.} \ As shown in Figure 13, then a protective layer 74 composed of silicon silicon nitride is formed on the surface of the dielectric layer 72, so that The protective layer 74 is in contact with the sacrificial layer 50. After that, a chemical mechanical polishing I (CMP) process is performed as shown in FIG. 14 to remove the protection over the sacrificial layer 50 to a predetermined thickness. Then, as shown in FIG. Η Sacrifice the Heart to the Electric Layer]

I. Explanation of the invention (9) After the electrical layer 7 2 is completely removed, another wet etching process is performed, and a hot dish is used; acid is used as an etching solution to completely remove the protective layer 7 4 on the surface of the semiconductor wafer 7 0 And the sacrificial layer 5 0 ′ above the first polycrystalline silicon layer 48 makes the top surface of the first polycrystalline silicon layer 48 and the surrounding dielectric layer 72 to form a hole 76. As shown in FIG. 16, a second polycrystalline silicon layer 7 8 is formed on a specific area of the surface of the semiconductor wafer 40 and fills the hole 76, so that the second polycrystalline silicon layer 7 8 is electrically charged. The connection to the first polycrystalline silicon layer 4 8 ′ completes the fabrication of the poly-crystalline silicon layer 80 in a three-dimensional space. As shown in the process described in FIG. 11 to FIG. 16, another embodiment of the present invention is to remove the dielectric layer 72 on the top edge of the sacrificial layer 50 using the HDP CVD method, and then to the surface of the dielectric layer 72 A protective layer 74 is formed. Therefore, in the follow-up | when the CMP process is performed, the protection 74 can effectively prevent the CMP process from over-grinding a part of the surface of the semi-conductor wafer 40, causing non-uniformity of the polishing, and then affecting the first polycrystalline silicon. The thickness of the dielectric layer 72 around the layer 48 is also 2 BD ^ BS. Moreover, by the protection of the protective layer 74, the surface of the ^ layer Γ can be prevented from being polluted by the slurry or metal contamination used in the CMP process. The method of the present invention is applied to non-volatile I, and can also be used to make and dynamically access a polycrystalline layer 60 in a two-dimensional space, in addition to being embedded in a non-voiatile memory process. Embedded flash memory (embedded f 1 ash) to lose one's own memory (dynamic random access memory,

: V. Description of the invention (10) Storage node of the capacitor element of the DRAM). Compared with the conventional method for manufacturing the composite polycrystalline silicon layer 28, the method for forming the polycrystalline silicon layer 60 in the three-dimensional space according to the present invention is a method using HDP CVD | The dielectric is formed before the first polycrystalline silicon layer 48 Layer 54 is used as BD / BS. Then, the surface of the dielectric layer 54 is planarized by the CMP method, and the sacrifice layer 50 above the first polycrystalline silicon layer 48 is removed by an etching process to form a hole 76. After the second polycrystalline silicon layer 78 is formed on the first polycrystalline layer 48, the surface of the polycrystalline silicon layer 80 in the entire three-dimensional space will be relatively formed into a 3D three-dimensional structure with the appearance of the holes 76. The contact area of the ONO dielectric layer and the control gate formed subsequently thereon increases the gate coupling rate. In another embodiment, the protective layer 74 is formed on the surface of the dielectric layer 72 before the f MP process, so that the thickness of the dielectric layer 72 formed around the first polycrystalline silicon layer 48 is controlled. Can prevent the surface of BD / BS from being polluted by slurry used in CMP process or its metal contaminants (meta contamination) < == The above is only a preferred embodiment of the present invention All equal changes and modifications made in accordance with the scope of the present invention application should be within the scope of the patent of the present invention®

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Claims (1)

i. Scope of patent application; i. A method for forming a three-dimensional poly-silicon layer on a semiconductor wafer, the semiconductor wafer includes a substrate, and a first polycrystalline silicon layer having an approximately square cross-section The method is disposed on a predetermined j region of the substrate surface, and a sacrificial layer is disposed directly above the first polycrystalline silicon layer. The method includes the following steps: I forming a dielectric layer on the surface of the semiconductor wafer and The thickness of the dielectric layer that covers the substrate and I and the sacrificial layer and is formed on the surface of the substrate is large! At the height of the top of the sacrificial layer; 丨 a chemical mechanical polishing (CMP) process is performed to completely remove the dielectric I layer above the sacrificial layer, and horizontally remove the dielectric on the substrate surface downward The electrical layer is a predetermined thickness! I degree; 丨 completely remove the sacrificial layer above the first polycrystalline silicon layer, so that the top surface of the first polycrystalline silicon layer and the dielectric layer bordering the surrounding form a hole; I and I forming a second polycrystalline silicon layer on a specific area of the surface of the semiconductor wafer and filling the hole, so that the second polycrystalline silicon layer can be electrically connected | I touch the first polycrystalline silicon layer The crystalline silicon layer completes the production of the polycrystalline silicon layer in the three-dimensional space: π. : 2. As the scope of the patent application i is composed of silicon oxide. Weng ^ iii method where the dielectric layer is based on the patent application scope, with the method '·-!-J' where the substrate is based on silicon P.15 6. Scope of patent application i. Many capacitors are separately packaged for use. 4. If the scope of patent application is @method, the three-dimensional hollow spar layer is used as a floating gate (f 1 〇atinggate) or: storage lower electrode of the component (storage node). 5. If the method of applying for a patent scope, wherein the base table 3 contains two doped regions respectively provided on the left and right sides of the ^ polycrystalline silicon layer as the source (s0U rce) and the drier (drai) of the floating gate n). 6. For example, a method of applying a patent wherein the sacrificial layer I is a silicon layer formed by a nitrogen oxide compound, and the thickness of the first sacrificial step substrate is at the top end surface: 7. A method for forming a three-dimensional space on a semiconductor wafer Polycrystalline: Method, the semiconductor wafer includes a substrate, a polycrystalline silicon layer having an approximately square cross-section is provided on a predetermined area of the surface of the substrate, and a layer is provided directly above the first polycrystalline silicon layer. The method includes the following : Step: A dielectric layer is formed on the surface of the semiconductor wafer and covers the sacrificial layer, and the dielectric layer formed on the surface of the substrate is greater than the thickness of the first polycrystalline layer and does not exceed the thickness 1 degree of the sacrificial layer; remove the dielectric layer on the side edge of the top of the sacrificial layer; form a protective layer on the surface of the dielectric layer, and make the protective layer and the top of the sacrificial layer of patent application scope I The side edges are in contact; a chemical mechanical polishing (CMP) process is performed to remove the protective layer and the dielectric layer above the sacrificial layer to a predetermined thickness; | completely remove the dielectric above the sacrificial layer The protective layer on the surface of the semiconductor wafer and the sacrificial layer above the first polycrystalline silicon layer are completely removed, so that the top surface of the first polycrystalline silicon layer and its surroundings: a dielectric layer adjacent to each other forms a hole; And forming a second polycrystalline silicon bite layer on a specific area of the surface of the semiconductor wafer and filling the hole, so that the second polycrystalline silicon layer can be electrically connected to the first polycrystalline silicon layer to complete the Fabrication of polycrystalline silicon layers in three dimensions. 8. As claimed in the Patent Scope® method, wherein the dielectric layer is formed of silicon dioxide deposited by high-density plasma chemical vapor deposition (HDP CVD). 9. For example, the scope of patent application method, wherein the method of removing the dielectric layer is a wet etching process, and the wet etching process uses diluted hydrofluoric acid (dilute HF, DHF) or buffered oxygen silicon etched solution (buffered oxide etcher, BOE). 10. The method according to the scope of the patent application, wherein the sacrificial layer and the protective layer are both composed of a nitrogen oxide compound Method 1 1. As the scope of patent application, which removes the semiconductor crystal Page 17 6. Scope of Patent Application | Method for protecting the surface of the wafer and the sacrificial layer over the first polycrystalline silicon layer | i is a wet etching process using hot phosphoric acid as an etching solution.丨 μ 2. The method according to the patent application, wherein the substrate is composed of silicon elements. ^ j.4 Xu Da i | 丨 1 3. As applied for the patent Fan Xing # method, wherein the three-dimensional space is as much as possible; a crystalline silicon layer is used as a gate or a storage lower electrode of a capacitor.丨 ； Essentials 1 | 14. If the scope of the patent application _ method, wherein the surface of the substrate is separately packaged;; The two doped regions are located on the left and right sides of the polycrystalline silicon layer, respectively, and are used as: Source and drain of the gate. i I [15. — A method for increasing the gate coupling i rat io (GCR) of a floating gate, the floating gate is made on a semiconductor wafer |: The semiconductor wafer contains a On the Shi Xi substrate, a polycrystalline silicon layer with an approximately square cross-section is provided on a predetermined area of the surface of the silicon substrate, and a sacrificial layer is provided directly above the first polycrystalline silicon layer. The method includes The following steps! I step: | forming a dielectric layer on the surface of the semiconductor wafer and covering the silicon substrate 1 and the sacrificial layer, wherein the dielectric layer is formed on the surface of the silicon substrate. I: the thickness is greater than the The thickness of the first polycrystalline silicon layer does not exceed the top i 丨 end of the sacrificial layer by Γ% degrees, j Page 18 6. The scope of the application for a patent removes the dielectric layer on the side edge portion of the top of the sacrificial layer; forms a protective layer on the surface of the dielectric layer and makes the protective layer contact the top side edge of the I sacrificial layer; Chemical mechanical polishing (CMP) process to remove the protective layer and dielectric layer on the sacrificial layer to a predetermined thickness; completely remove the dielectric layer above the sacrificial layer: 丨 completely remove the protective layer on the surface of the semiconductor wafer and The first polycrystalline silicon i: a sacrificial layer above the shixi layer, so that the top surface of the first polycrystalline silicon layer and the dielectric layer bordering the surrounding i form a hole; 丨: a specific area on the surface of the semiconductor wafer A second polycrystalline i sand layer is formed thereon, filled in the hole and electrically connected to the first polycrystalline silicon layer to form the floating gate; and i forms an insulating layer on the surface of the floating gate; j! The surface of the second polycrystalline silicon layer will follow the position of the hole j: recessed to the ground, forming a three-dimensional three-dimensional structure, and then increasing the subsequent insulation layer and control gate formed on it Contact area Improving the gate coupling of the floating gate 丨 I, Minna .. 1; 丨 1 6. If the method of patent application is applied, wherein the dielectric layer is a high I: density plasma chemical vapor deposition ( hdT CVD) deposition of silicon dioxide, and the method of removing the dielectric layer is a wet etching process, and the wet etching process uses diluted hydrofluoric acid (DHF) or buffered oxygen Silicon Etching Solution: (BOE) as the etching solution. i Page 19 ^ JC (^ JC (VI. Scope of patent application 1 7. If you apply for a special protection layer, Scope method-composed of nitrogen silicon compounds, where the sacrificial layer and the 18. If the scope of patent application: the protection of the surface of the sheet is a use of heat. 19. If the application specifically contains two dopings as the floating I. 20. If the application is for mono-oxygen compounds, i. A method in which the semiconductor crystal layer and the sacrificial layer over the first polycrystalline silicon layer are removed by a wet etching process using phosphoric acid as an etching solution. This method uses a range method in which the other areas of the silicon substrate surface are respectively located on the left and right sides of the first polycrystalline silicon layer, and the source and the drain of the gate are used. Method, wherein the insulating layer is composed of a silicon nitride compound and a silicon oxide compound sequentially stacked Page 20