罾4 326 2 2 A7 -----B7五、發明說明（） 發明頜娀： 本發明與—種半導體製程中形成雙重鑲嵌结構（dual damascene)之方法有關，特别是一種形成雙重鑲嵌結構於低 介電値介電層（low K dielectric)中之製程。 發明背景： 隨著半導體工業持續的進展，在超大型積體電路（ULSI) 的開發與設計中’爲了符合高密度積體電路之設計趨勢，各 式凡件之尺寸皆降至次微米以下。並且由於元件不斷的縮 小’也導致在進行相關半導體製程時，往往遭遇了前所未有 之難題，且製程之複雜程度亦不斷提高。一般而言，積體電 路包括在晶圓上某特定區域中，形成數以百萬計的元件，以 及用以連接這些元件的電子連結結構，以便能執行所需之特 定功能。囡此積體電路的性能，除了依靠所含元件之性能及 可靠度外，更需要無數精密細微的金屬内連線，以便能有效 傳遞元件間的電子訊號。特别是随著積體電路尺寸持績的縮 小，當前的積體電路設計，已朝著多重金屬内連線發展。 (請先閱讀背面之注意事項再填寫本頁) 裝 訂· 經濟部智慧財產局員工消費合作社印製 …、而在多重金屬内連線的相關製程中，由於受制於微 影解析度的限制、曝光聚焦（Focus)的誤差、影像傳遞的精 確度與解析度（Re solution)與可使用空間的縮小，導致雙重 本紙張尺度適用中國國家標準（CNS)A4規格（210 * 297公釐） A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（ 鑲嵌製程（dual damascene pr〇Cess)技術受到廣泛的發展與 運用，並藉以製造多重金屬内連線。如同熟悉該項技術者所 熟知的，雙重鑲嵌結構的製程，可同步形成半導體底材上之 溝渠連線與連接至底材之導電插塞。如此一來，除了有效提 昇積體電路連線技術外，更大幅提昇了積體電路之可靠度與 良率。因此雙重鑲嵌結構，被大量的應用於大型積體電路内 連線之製程中。 請參照第一圖至第四囷，其中類示了傳統製程卡，形 成雙重鎮嵌結構於半導體底材上之方珐。如第—圖所示，t 先可在半導體底材10之上’依序形成第一介電層丨2、氮化 石夕層14、弟一介電廣16與抗反射介電層（Die丨ectric Anti _ ReflecUve Uyer; DARC) 18。接著，可在抗反射介電層18 上，形成光阻層20。其中’此光阻層2〇上具有用來定義介 電層間内連線（via)之圖案。 接著，如第二圖所示，如對上述所形成之抗反射介電 層18、第二介電層16、氮化矽層14與第一介電層12進行 独刻程序，以形成開口 22，且曝露出半導體底材之上表 面。然後’在移除光阻層20後，再於抗反射介電層18上， 形成光阻層24’此光阻層24乃用以定義溝渠圖索於半導體 底材10上。再使用光阻層24作爲蝕刻罩冪，對抗反射介電 層18與第二介電層16進行蝕刻程序後，可定義出所需的溝 本纸張尺度適用中國國家標準（CNS)A4規格（210 * 297公釐） ----------- 裝--------訂· f請先閱讀背面之注惠事項再填鸾本頁) 4 32622 五、發明說明（ ΒΩ 本固累。 f靖先閲讀背面之注意事項再填寫本頁) &參見第三囷，在定義溝渠圖案於半導體底材10上 之後，接著形成一阻障層（barrier layer)26於抗反射介電層 18、第二介電層16、氮化矽層丨4、第一介電層12與半導體 底材10之表面上。隨後，再形成導電層28於阻障層26之 上表面，且塡充至上述開口 22與溝渠中。接著，使用化學 機械研磨法（CMP)，對半導體底材ι〇進行研磨程序，直至 抵達第二介電層16爲止4如此，彳以得到如第四圖中所顯 不I雙重鑲嵌結構。其中，此雙重鑲嵌結構31包括了位於 第一介電層12中之導電插塞3〇,以及位於第二 中之溝渠内連線32。 6 經濟部智慧財產局員工消費合作社印製 値彳于；王意的是如同前述，由於高密度積體電路中所需 之各式元件，其尺寸皆在次微米以τ，是以爲了更有效的防 止積體電路良率與可靠度下降。在製作上述第一介電層12 與第二介電層16時，往往採用具有較低介電値（i〇wK)之材 料，以便減少所形成元件之RC延遲，並提高元件之操作速 度。但是在使用此種材料在形成所需介電層時，亦遭遇諸多 問題。其中’由於所使用低介電値介電屠，其主要構成材料 包括破原子（carbon base)，是以在使用光阻層（2〇輿24)來作 爲蚀刻罩冪，以定義圖案於介電層（丨2與16)時，其蝕刻選 擇性並不佳。亦即，會導致進行蝕刻程序時，需形成更厚的 本紙張尺度適用中國國家標準（CNS)A4说格（210 X 297公爱） 經濟部智慧財產局員工消費合作社印製 五、發明說明（） 光阻層，來防止蝕刻寮透（etch thro ugh)的情況發生；此外， 也會導致定義於介電層上之圖案，具有精確度較低的維度。 由此，而導致需耗費更多的時間與成本。 爲了解決:餘刻選择性不佳的問題，往往藉著通入氧氣 而提昇介電層之蝕刻選擇性。但是’由於低介電値介電層材 料’具有大量的碳原子，是以在蝕刻程序進行中通入氧氣， 往往會產生更多的高分子附著物。請參照第五圖，該圖所靖 示’爲在使用光阻層20來定義卩^^22於半導體底材1〇上 時，所產生之高分子附著物34。在定義開口 22時， 需先後蝕刻第二介電層16與第一介是以將產生更 多的高分子附著物34，附著在開口 22 與半導趙底材 10之上表面。嚴重者，甚至可能導致開口 22無法有效的曝 露出半導體底材1〇，而使後續製造之插塞無法有效的連行 電性傳導。 另外’値得注意的是’在定義開口圖案22與溝渠圖 案於介電層（12與16)上時所使用之乾式蝕刻術，與在移除 光阻層（2 0與2 4)時所進行的濕式清洗程序，往往會造成介 电層持績的曝露於充滿侵独性氣體、溶液的環境中，是以辟 常會導致所定義開口圖案與溝渠圖案之側壁，產生如第六圖 中所不之回侵蝕（erosi〇n back)36、38。除了造成所定義圖 案維度的不精確外’並造成開口與溝渠形狀（pr〇fUe)的故 本紙張又度適用中國囷家標準（CNS)A4規格<210 X 297公釐） ------------- 裝—-----—訂—-------線、 (請先閱讀背面之注意事項再填寫本頁} A7 1326 2 2 B7 五、發明說明（） 變。特别是如第七圖中所示，具有較低介電値之介電材料 12，往往具有極多的孔隙（p〇rous)4〇，而上述介電層側壁之 回侵蝕36、38’則會導致孔隙外露42。並且，由於孔隙外 露42，造成介電層12間之應力不均句，而使介電層12沿 著其中孔隙40而產生裂缝（searn)44，造成整個半導體元件 可靠性的降低。 發明目的及概述： 本發明之目的爲一種形成雙重鑲嵌結構於低介電値 (K芸3)介電層中之製程方法。 本發明之再一目的爲一種可有效避免低介電値介電 層產生裂缝之雙重鑲嵌結構製造方法。 本發明之又一目的爲提供一種有效提昇雙重鑲嵌結 構其維度精確性之製造方法。 本發明提供’了一種形成雙重鑲嵌結構於半導體底材 上之方法。在較佳實施例中，此方法包括了下列步驟。首先， 形成第一低介電値（K^3)介電層於半導體底材上，且形成抗 反射介電層於第一低介電値介電層上。接著，蝕刻抗反射介 電層與第一低介電値介電層，以便形成第一開口於抗反射介 本紙張尺度適用中國圉家標準（CNS)A4規格（210 x 297公釐） 111111—·'1' ·1111111 ^ ·11111111 (請先閱讀背面之沒意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印5衣 經濟部智慧財產局員工消费合作社印製 Λ 3262 2 Α7 ---Β7 五、發明說明（） 電層與第一低介電値介電層中，並且曝露出部份半導體底材 上表面。 然後，形成光阻層於抗反射介電層上，其中光阻層具 有作爲溝渠圖案之第二開口，且此第二開口位於第一開口上 方，第二開口並曝露出部份抗反射介電層與部份半導體底材 上表面。隨後，形成阻障層於光阻層、抗反射介電層與半導 體底材之上表面，其中阻障層並覆蓋於第一開口與第二開口 之表面上。 接著，形成一薄銅層於阻障層表面，以作爲銅晶種（Cu seeding)房。再使用電鍍法形成銅層於阻障層表面上，且填 充至第一開口與第二開口中。接著，移除部份銅層與部份阻 障層，直至光阻層上表面曝露出來爲止。再移除光阻層，以 曝露出抗反射介電層之上表面。然後，形成第二低介電値（κ $3)介電層於抗反射介電層與阻障層之表面上。 圖式簡單説明： 藉由以下詳細之描述結合所附阖示，將可輕易的了解 上述内容及此項發明之諸多優點，其中： 第一圖爲半導體晶片之截面圖，顯示根據傳統技術形 成第一介電層、氮化矽層、第二介電層與抗反射層於半導體 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -n ^1 ^1 ^1 ^1 ^1 一 I ^1 ^1 ^1 ^1- .^1 I (請先閱讀背面之注意事項再填寫本頁) 43262 2 A7 B7 五、發明說明（ 經濟部智慧財產局員工消費合作社印製 底材上之步驟； 第一圖爲半導體晶片之截面圖， 義開口囷案於半導體底材上之步驟； 第三圖爲半導體晶片之截面圖， 義溝渠圖案於半導體底材上之步驟； 弟四圖爲半導體晶片之截面圖： 成雙重讓狀結構於半導體底材上之步驟. ^五圖爲半導體晶片之截面圖，顏示根據傳统技術独 刻介電層時’所產生之高分子附著物； 第六圖爲半導體晶片之截面圖，顯示根據傳統技術定 義開口圖案與溝渠圖案於半導體底材上時，所造成介電層側 壁發生回侵蝕之現象； 第七圖爲半導體晶片之截面圖，顯示根據傳统技術進 行定義圖案程序，導致介電層中孔隙發生裂縫之現象； 第八囷爲半導體晶片之截面圖，顯示根據本發明形成 介電層、抗反射層於半導體底材上之步騍； 第九圖爲半導體晶片之截面圖，顯示根據本發明定義 開口圖案於半導體底材上之步驟； 第十圖爲半導體晶片之截面圖，顯示根據本發明形成 導電材料於開口與溝渠圖案中之步驟； 第十一圖爲半導體晶片之截面圖，顯示根據本發明形 成雙重鑲嵌結構於半導體底材上之步騍；及 類示根據傳統技術定 顯示根據傳統技術定 顯示根據傳統技術形 (請先閱讀背面之注意事項r.^寫本頁) 裝 SJ· ;線 本紙張尺度適用中關家標準（CNS)A4規格⑽χ 297公爱） A7 432622 五、發明說明（） 第十圖爲半導體晶片之截面圖，顯示根據本發明形 成介電層於溝渠連線週圍之步裸。 發明詳細説明： 本發明所揭示爲—種形成雙重鑲嵌結構於低介電値 介電層中之方法。藉著使用—犧牲層，來定義雙重鑲嵌結構 中之溝；連線，可有效的防止介電層曝露於餘刻環境中。並 且，可有效的減少介電層側壁產生回侵蝕，而降低介電層產 生裂缝之機會。有關本發明之詳細説明如下所述β 首先，請參照第八圖，在—較佳之具體實施例中，提 供一具<100>晶向之單晶矽底材1〇〇。一般而言，其它種類 之半導體材料’諸如砷化鎵（gallium arsenide)、鍺 (germanium)或是位於絶緣層上之矽底材（siHc〇n⑽ insulator，s〇i)亦可作爲半導體底材使用。另外，由於半導 體底材表面的特性對本發明而言，並不會造成特别的影晌， 是以其晶向亦可選擇<11〇>或<m>。値得注意的是，在進 行本發明後績製程前，半導體底材100上已依照需要，先形 成各式各樣所需之元件與相關膜層。 接著，仍如第八圖所示，形成第一介電層102於半導 體底材100上。其中，上述之第一介電層是由低介電値（κ 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝--------訂----- 嗲！ 經濟部智慧財產局員工消費合作社印製 A7 B7 rM326 2 2 五、發明說明（） —3)材料所構成。例如’可選擇 FLARE、silk、xerogel、Aerogel 等材料或其任意的組合，來形成此第一介電層。並且，在一 較佳實施例中’此第一介電層具有約5000至10000埃之厚 度》 然後，可選擇性的形成抗反射層（Anti-Reflection layer; ARC)104於第一介電層1〇2上，以提昇微影解析度。—般 來説’可選擇抗反射介電層（Dielectrie ARC; DARC)來作爲 抗反射層104。其中，由於氮氧化矽層之製作較容易與其它 半導體底材之處理過程整合’且其材料之光學品質及相關製 程之參數’業以徹底的了解。是以在一較佳實施例中，可由 厚度約3 00至1200埃的氮氧化矽層來構成抗反射層104。 其中，所形成之氮氧化矽層，是使用電漿增強化學氣相沉積 法（plasma enhanced chemical vapor deposition; PECVD)所 形成e並且，在形成氮氧化矽層時，通入反應室令之反應氣 體包括了 SiH4、N2〇與He等等。至於進行反應之溫度則大 約爲3 50至4 5 01〇，且壓力約5至7 torr。 接著，可形成光阻層106於上述抗反射層1〇6之上。 其中’該光阻層106具有用來定義介電層間連線（via)之第 —開口圏案。然後，蝕刻抗反射層104與第一介電層1〇2， 以形成如第九圖所顯示之第一開口 108於抗反射層1〇4與 第一介電層102中。此第一開口 108，並曝露出部份半導體 本紙張尺度適用_國國家標準（CNS)A4規格（210x297公釐） <請先閱讀背面之注意事項再填寫本頁) n ϋ n n ϋ I n ϋ n I i < 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 432622 Α7 Β7 五、發明說明（） 底材丨〇〇上表面。値知注意的是如同前述，第一開口圖案 108可用來定義出後績製程中’所形成介電層間連線（via) 或導電插塞（plug)之位置。在一較佳實施例中，可使用反應 離子蝕刻程序來進行上述的蝕刻程序，且對作爲抗反射層 104之氮氧化矽材料而言，其蝕刻配方可選擇CF4/H2、 CHFyl CH3CHF2。 接著，仍如第九圖所示，形成犧牲層（sacrificial layer)l 10於抗反射層上。其中犧牲層11〇具有作爲溝 渠圖案之第二開口 112’且遠第二開口 112位於第一開口 108上方。此第二開σ Π2並曝露出部份抗反射層ι〇4、部 份第一介電層102與部份半導體底材1〇〇表面。在一較佳實 施例中，上述犧牲層可選擇厚度約8000至12000埃之光阻 層來加以形成。此外，諸如氧化層等之介電材料，亦可作爲 此犧牲層110使用。値得注意的是，如同上述第二開口圖案 112，可用來定義後續所形成溝渠内連線其位置。 値得注意的是’當使用氧化層材料，來做爲上述犧牲 層110時，可先形成一氧化層於半導體底材1〇〇上，再藉著 微影蚀刻程序’而定義第二開口圖索112於該氧化層上。在 —較佳實施例中，可使用化學氣相沈積法（C ν D),以四乙基 矽酸鹽（TEOS)爲材料，來沉積所需之氧化矽層。接著，可 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閲讀背面之注意事項再填寫本頁) β 裝 *-------訂-----I---ί A7 B7 432622 五、發明說明（） 再形成一光阻層於此氧化層上，以作爲蝕刻罩冪，並藉著進 行钱刻程序’而定義出第二開口圖案於此氧化層上。其中， 蚀刻氧化層之蝕刻配方，可選擇CC12F2、CHF3/CF4 ' chf3/ 〇2、CH3CHF2 ' CFJ〇2 ο 然後’清參照弟十圖，形成阻障層（barrier layer)〗1 4 於犧牲層110、抗反射層1〇4、第一介電層丨〇2與半導體底 材100之表面上。其_，此阻障層114除了可提昇後績所形 成導電層’與其下第一介電層1〇2、抗反射層1〇4、半導體 底材1 0 0之間的接觸面性質外，以增加其間的附著能力外； 亦可防止後續所形成導電層材料，產生擴散而入侵至第一介 電層102中。一般而言’阻障層114可使用物理氣相沉積法 (physical vapor deposition; PVD)來形成，且其材料可選擇 鉅、氮化鉅或其任意組合。至於，所形成之阻障層丨丨4约具 有250至350埃的厚度，且最好約爲300埃。 在一較佳實施例中，作爲阻障層丨丨4使用之氮化舶 層’可使用氮化反應（Nitridation)製程來形成。首先，進行 濺鍍（sputtering)程序，以沉積一鉅層於犧牲層11〇、抗反射 層104、第一介電層102與半導體底材1〇〇之表面上。再於 N2或NH3的環境中，經由高溫處理而形成所需之氮化起層. 此外，也可利用反應性濺鍍程序來形成氮化鉅層。藉著利用 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公« ) ----------- -裝--I-----訂 ----I---^ -- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局貝工消費合作社印製 經 濟 部 智 慧 財 產 員 工 消 費 合 作 社 印 製 鬮 432622 五、發明說明（） 電漿離子轟擊鉅金屬，且通入氬氣與氮氣，以便經轟擊所濺 出的钽原子，可與經由解離反應（Dissociation Reaction)所 形成的氮原子’反應並生成氮化鉅而沉積。 接著，仍如第十圖所示，形成導電層116於阻障層114 之上，且填充至第一開口 1()8與第二開口 ι12之中。其中， 上述導電層116的材料，可選擇捧雜多晶石夕（d〇ped polysilicon)、同步摻雜多晶矽（in_situ d〇ped polysilicon)、 銅、鋁、鈦、鎢、白金或其任意組合。在—較佳實施例中， 上述導電層116是由铜所構成並且，形成銅層於阻障層 114上之步驟，包括了先使用物理氧相沉積（pVD)法或化學 氣相沉積法（CVD)，沉積一薄銅層於阻障層丨14表面，以作 爲銅日日種（Cu seeding)層。接著，再使用電鍵製程 (electroplating)，沉積所需的銅層於阻障層表面114上，且 填充至第一開口 1〇8與第二開口 112之中，而形成如第十圖 中所示之導電層116。 隨後’請參照第十一圖’移除位於犧牲層n 〇上方之 部份導電層1丨6與部份阻陣層i 14。在較佳實施例中，可使 用化學機械研磨法（CMP)來對半導體底材丨〇〇進行研磨程 序’以移除上述部份導電層116與部份阻障層U4。接著， 將殘餘犧牲層110加以移除，以曝露出抗反射層1〇4之上表 面。其中當使用光阻層來作爲犧牲層Uo使用時，可將整個 13 張尺度適用T S國家標準（CNS)A4規格（210 χ 297公釐） {請先聞讀背面之注意事項再填寫本頁) 裝--1 i I丨訂------1—'今 432622罾 4 326 2 2 A7 ----- B7 V. Description of the invention () Inventive jaw: This invention is related to a method of forming a dual damascene in a semiconductor process, especially a method of forming a dual damascene in Process in low K dielectric. Background of the Invention: With the continuous progress of the semiconductor industry, in the development and design of ultra-large integrated circuits (ULSI), in order to meet the design trend of high-density integrated circuits, the size of all kinds of components has been reduced to sub-micron. And due to the continuous shrinking of components, it also causes unprecedented difficulties in the related semiconductor manufacturing process, and the complexity of the process is also increasing. In general, integrated circuits include millions of components in a specific area on a wafer, as well as electronic connection structures used to connect these components in order to perform the specific functions required.积 In addition to the performance and reliability of the contained components, the performance of this integrated circuit requires countless precise and fine metal interconnections in order to effectively transfer the electronic signals between the components. Especially as the size of integrated circuits continues to shrink, current integrated circuit designs have evolved toward multi-metal interconnects. (Please read the precautions on the back before filling out this page.) Printed by the Consumption Cooperative of Employees of the Intellectual Property Bureau of the Ministry of Economics and Binding ... In the related process of multi-metal interconnection, due to the limitation of lithographic resolution, exposure Focus (Focus) error, image transmission accuracy and resolution (Re solution) and reduction of usable space, resulting in a double paper size applicable to China National Standard (CNS) A4 specifications (210 * 297 mm) A7 B7 Economy Printed by the Consumer Cooperatives of the Ministry of Intellectual Property Bureau 5. Invention Description (Dual damascene prOcess) technology has been widely developed and used to manufacture multi-metal interconnects. As is familiar to those skilled in the technology, The manufacturing process of the dual damascene structure can simultaneously form the trench connection on the semiconductor substrate and the conductive plug connected to the substrate. In this way, in addition to effectively improving the integrated circuit connection technology, the integrated circuit has been greatly improved. Reliability and yield. Therefore, the dual mosaic structure is widely used in the process of interconnecting large integrated circuits. Please refer to the first figure To the fourth step, which shows the traditional process card, which forms a double-embedded structure on the semiconductor substrate. As shown in the first figure, t can first form the first on the semiconductor substrate 10 in order. Dielectric layer 丨 2, nitride nitride layer 14, Di-dielectric layer 16 and anti-reflective dielectric layer (Die 丨 ectric Anti_ReflecUve Uyer; DARC) 18. Next, an anti-reflective dielectric layer 18 can be formed Photoresist layer 20. Among them, 'this photoresist layer 20 has a pattern defining a via between dielectric layers. Then, as shown in the second figure, the anti-reflective dielectric layer formed as described above is shown. 18. The second dielectric layer 16, the silicon nitride layer 14 and the first dielectric layer 12 are individually etched to form an opening 22 and expose the upper surface of the semiconductor substrate. Then, the photoresist layer 20 is removed Then, a photoresist layer 24 is formed on the anti-reflection dielectric layer 18. This photoresist layer 24 is used to define a trench pattern on the semiconductor substrate 10. The photoresist layer 24 is used as an etching mask to prevent reflection. After the dielectric layer 18 and the second dielectric layer 16 are etched, the required groove paper size can be defined for the Chinese country. Standard (CNS) A4 (210 * 297 mm) ----------- Packing -------- Order · f Please read the note on the back before filling this page) 4 32622 V. Description of the invention (ΒΩ Ben Gu tired. F Jing first read the precautions on the back before filling out this page) & See the third paragraph, after defining the trench pattern on the semiconductor substrate 10, then a barrier layer is formed A barrier layer 26 is formed on the surfaces of the anti-reflective dielectric layer 18, the second dielectric layer 16, the silicon nitride layer 4, the first dielectric layer 12, and the semiconductor substrate 10. Subsequently, a conductive layer 28 is formed on the upper surface of the barrier layer 26 and filled into the openings 22 and trenches. Then, a chemical mechanical polishing method (CMP) is used to perform a polishing process on the semiconductor substrate ι until it reaches the second dielectric layer 16 4 so as to obtain a double damascene structure as shown in the fourth figure. The dual damascene structure 31 includes a conductive plug 30 located in the first dielectric layer 12, and a trench interconnect 32 located in the second middle. 6 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs; Wang Yi's is the same as above. Because of the various components required in high-density integrated circuits, their dimensions are in the sub-micron to τ, in order to be more effective. The yield and reliability of the integrated circuit are prevented from decreasing. When the first dielectric layer 12 and the second dielectric layer 16 are fabricated, materials with a lower dielectric chirp (iowK) are often used in order to reduce the RC delay of the formed element and increase the operation speed of the element. However, there are also many problems encountered when using this material to form the required dielectric layer. Among them, 'because of the low-dielectric and dielectric materials used, the main constituent materials include carbon bases, and the photoresist layer (24) is used as an etching mask to define the pattern on the dielectric. The layers (2 and 16) have poor etching selectivity. That is, it will lead to a thicker paper size when the etching process is carried out. Applicable to China National Standard (CNS) A4 standard (210 X 297 public love) Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs ) Photoresist layer to prevent etch thro ugh; in addition, it will also cause the pattern defined on the dielectric layer to have a less accurate dimension. As a result, more time and costs are required. In order to solve the problem of poor selectivity at the rest of the time, the etching selectivity of the dielectric layer is often improved by introducing oxygen. However, since the "low-dielectric / dielectric-layer material" has a large number of carbon atoms, the introduction of oxygen during the etching process tends to generate more polymer deposits. Please refer to the fifth figure, which shows the polymer attachments 34 generated when the photoresist layer 20 is used to define 卩 ^^ 22 on the semiconductor substrate 10. When defining the opening 22, the second dielectric layer 16 and the first dielectric need to be etched successively so that more polymer attachments 34 will be generated and adhere to the upper surface of the opening 22 and the semiconductor substrate 10. In severe cases, it may even cause the opening 22 to be unable to effectively expose the semiconductor substrate 10, and the subsequent manufacturing of the plug cannot effectively conduct electrical conduction. In addition, it should be noted that the dry etching technique used when defining the opening pattern 22 and the trench pattern on the dielectric layers (12 and 16), and the method used when removing the photoresist layer (20 and 24) The wet cleaning process often causes the dielectric layer to be constantly exposed to an environment full of aggressive gases and solutions, which often leads to the sidewalls of the defined opening patterns and trench patterns, as shown in the sixth figure. Erosion back 36, 38. In addition to the inaccuracy of the defined pattern dimensions, and the shape of the openings and trenches (pr0fUe), the paper is again suitable for the Chinese Standard (CNS) A4 specification < 210 X 297 mm) ---- --------- Install —-----— Order —------- Line, (Please read the notes on the back before filling out this page} A7 1326 2 2 B7 V. Description of the invention () Change. Especially as shown in the seventh figure, the dielectric material 12 with a lower dielectric constant tends to have a large number of porosity 40, and the above-mentioned dielectric layer side wall erodes 36 , 38 'will cause the pores to be exposed 42. Moreover, due to the pores being exposed 42, the stress unevenness between the dielectric layers 12 will be caused, and the dielectric layer 12 will generate cracks 44 along the pores 40 therein, causing the entire Reduction of the reliability of semiconductor devices. Object and Summary of the Invention: The object of the present invention is a process for forming a dual damascene structure in a low dielectric chirp (Kyun 3) dielectric layer. Another object of the present invention is an effective method. Manufacturing method of double damascene structure for avoiding cracks in low-dielectric chirped dielectric layer. Another object of the present invention is to provide A manufacturing method for effectively improving the dimensional accuracy of a dual damascene structure. The present invention provides a method for forming a dual damascene structure on a semiconductor substrate. In a preferred embodiment, this method includes the following steps. First, forming a first A low-k dielectric (K ^ 3) dielectric layer is formed on the semiconductor substrate, and an anti-reflective dielectric layer is formed on the first low-dielectric K dielectric layer. Next, the anti-reflective dielectric layer and the first low-dielectric layer are etched. Electrical dielectric layer in order to form the first opening in the anti-reflective dielectric. This paper is sized according to Chinese Standard (CNS) A4 (210 x 297 mm) 111111— · '1' · 1111111 ^ · 11111111 (Please read first Please fill in this page again on the unintentional matter on the back) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Λ 3262 2 Α7 --- Β7 V. Description of Invention In the low-k dielectric layer, the upper surface of the semiconductor substrate is exposed. Then, a photoresist layer is formed on the anti-reflection dielectric layer, wherein the photoresist layer has a second opening as a trench pattern, and this first Two openings are located at the Above the opening, a second opening exposes part of the upper surface of the anti-reflection dielectric layer and part of the semiconductor substrate. Subsequently, a barrier layer is formed on the photoresist layer, the anti-reflection dielectric layer and the upper surface of the semiconductor substrate. The barrier layer covers the surfaces of the first opening and the second opening. Next, a thin copper layer is formed on the surface of the barrier layer to serve as a Cu seeding room. Then, a copper layer is formed on the barrier using electroplating. The surface of the barrier layer is filled into the first opening and the second opening. Then, remove part of the copper layer and part of the barrier layer until the upper surface of the photoresist layer is exposed. Then remove the photoresist layer to The upper surface of the anti-reflection dielectric layer is exposed. Then, a second low-k dielectric (κ $ 3) dielectric layer is formed on the surfaces of the anti-reflection dielectric layer and the barrier layer. Brief description of the drawings: The above-mentioned content and many advantages of this invention can be easily understood through the following detailed description combined with the attached instructions, where: The first figure is a cross-sectional view of a semiconductor wafer, showing the formation of the A dielectric layer, a silicon nitride layer, a second dielectric layer, and an anti-reflection layer are applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) at the semiconductor paper size -n ^ 1 ^ 1 ^ 1 ^ 1 ^ 1 I I ^ 1 ^ 1 ^ 1 ^ 1-. ^ 1 I (Please read the notes on the back before filling out this page) 43262 2 A7 B7 V. Description of the invention (printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs) Steps on the material; The first figure is a cross-sectional view of a semiconductor wafer, which is a step for opening a semiconductor substrate; the third figure is a cross-sectional view of a semiconductor wafer, which is a step for patterning a trench on a semiconductor substrate; The figure is a cross-sectional view of a semiconductor wafer: Steps of forming a double-convex structure on a semiconductor substrate. ^ The fifth figure is a cross-sectional view of a semiconductor wafer, showing the polymer attachments produced when the dielectric layer is etched in accordance with traditional technology. The sixth figure is a semiconductor crystal The cross-sectional view of the wafer shows the phenomenon of back erosion of the sidewall of the dielectric layer when the opening pattern and the trench pattern are defined on the semiconductor substrate according to the conventional technology. The patterning procedure causes the phenomenon of cracks in the pores in the dielectric layer. The eighth step is a cross-sectional view of a semiconductor wafer, showing the steps of forming a dielectric layer and an anti-reflection layer on a semiconductor substrate according to the present invention. The ninth view shows a semiconductor. A cross-sectional view of a wafer shows a step of defining an opening pattern on a semiconductor substrate according to the present invention; a tenth view is a cross-sectional view of a semiconductor wafer, showing a step of forming a conductive material in the opening and trench pattern according to the present invention; an eleventh view This is a cross-sectional view of a semiconductor wafer, showing the steps of forming a dual damascene structure on a semiconductor substrate according to the present invention; and showing the display according to the traditional technology. The display according to the traditional technology. . ^ Write this page) Install SJ ·; The size of thread paper is applicable to Zhongguanjia Standard (CNS) A4 specification⑽χ 297 Love) A7 432622 V. invention is described in () picture shows a cross-sectional view of a tenth of a semiconductor wafer, according to the present invention is shown as a dielectric layer formed around the trench in the step of the bare wires. Detailed description of the invention: The present invention discloses a method for forming a dual damascene structure in a low dielectric 値 dielectric layer. By using the sacrifice layer, the trench in the dual damascene structure is defined; the wiring can effectively prevent the dielectric layer from being exposed to the environment at the moment. And, it can effectively reduce the back erosion of the dielectric layer side wall, and reduce the chance of cracks in the dielectric layer. The detailed description of the present invention is as follows. Β First, please refer to the eighth figure. In the preferred embodiment, a single crystal silicon substrate 100 with a crystal orientation of < 100 > is provided. Generally speaking, other types of semiconductor materials such as gallium arsenide, germanium, or a silicon substrate (siHc〇n⑽ insulator (soi)) on the insulating layer can also be used as a semiconductor substrate. . In addition, since the characteristics of the surface of the semiconductor substrate do not cause special effects to the present invention, the crystal orientation can also be selected as < 11〇 > or < m >. It should be noted that, before carrying out the post-production process of the present invention, the semiconductor substrate 100 has been formed with various required components and related film layers as required. Then, as shown in FIG. 8, a first dielectric layer 102 is formed on the semiconductor substrate 100. Among them, the above-mentioned first dielectric layer is made of low dielectric 値 (κ This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page)) -------- Order ----- 嗲! A7 B7 rM326 printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 2 2 V. Description of the invention () — 3) Composition of materials. For example, the first dielectric layer may be formed by selecting materials such as FLARE, silk, xerogel, Aerogel, or any combination thereof. And, in a preferred embodiment, 'this first dielectric layer has a thickness of about 5000 to 10,000 angstroms. "Then, an anti-reflection layer (ARC) 104 can be selectively formed on the first dielectric layer. 10, to improve the lithographic resolution. In general, an anti-reflection dielectric layer (Dielectrie ARC; DARC) can be selected as the anti-reflection layer 104. Among them, since the fabrication of the silicon oxynitride layer is easier to integrate with the processing processes of other semiconductor substrates ', and the optical quality of the materials and related process parameters' are thoroughly understood. Therefore, in a preferred embodiment, the anti-reflection layer 104 may be formed of a silicon oxynitride layer having a thickness of about 300 to 1200 angstroms. The silicon oxynitride layer formed is formed by plasma enhanced chemical vapor deposition (PECVD), and when the silicon oxynitride layer is formed, the reaction gas is passed through the reaction chamber. Including SiH4, N2O and He and so on. As for the temperature at which the reaction is carried out, it is about 3 50 to 45 1 0, and the pressure is about 5 to 7 torr. Then, a photoresist layer 106 may be formed on the anti-reflection layer 106 described above. Among them, the photoresist layer 106 has a first opening scheme for defining a dielectric interlayer via. Then, the anti-reflection layer 104 and the first dielectric layer 102 are etched to form a first opening 108 in the anti-reflection layer 104 and the first dielectric layer 102 as shown in the ninth figure. This first opening 108 exposes some semiconductors. This paper is suitable for the size of the paper. _National Standard (CNS) A4 (210x297 mm) < Please read the precautions on the back before filling this page.) N ϋ nn ϋ I n ϋ n I i < Printed by the Employees 'Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Employees' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by 432622 Α7 Β7 V. Description of the invention () Substrate 丨 〇〇 Top surface. It should be noted that, as mentioned above, the first opening pattern 108 may be used to define a position of a dielectric interlayer via or a conductive plug formed in the later process. In a preferred embodiment, the above-mentioned etching process can be performed using a reactive ion etching process, and for the silicon oxynitride material as the anti-reflection layer 104, the etching formula can be selected from CF4 / H2, CHFyl CH3CHF2. Next, as shown in the ninth figure, a sacrificial layer 110 is formed on the anti-reflection layer. The sacrificial layer 110 has a second opening 112 'as a trench pattern, and the second opening 112 is located above the first opening 108. This second opening σ Π 2 exposes part of the anti-reflection layer ι04, part of the first dielectric layer 102, and part of the surface of the semiconductor substrate 100. In a preferred embodiment, the sacrificial layer may be formed by selecting a photoresist layer having a thickness of about 8000 to 12000 angstroms. In addition, a dielectric material such as an oxide layer can also be used as the sacrificial layer 110. It should be noted that, like the second opening pattern 112 described above, it can be used to define the position of the interconnecting lines formed in the trenches that are subsequently formed. It should be noted that when an oxide layer material is used as the sacrificial layer 110, an oxide layer can be formed on the semiconductor substrate 100 first, and then the second opening pattern is defined by the lithography etching process. The cable 112 is on the oxide layer. In a preferred embodiment, a chemical vapor deposition method (C v D) can be used to deposit a desired silicon oxide layer using tetraethyl silicate (TEOS) as a material. Then, this paper size can be applied to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page) β Packing * ------- Order ---- -I --- ί A7 B7 432622 V. Description of the invention () A photoresist layer is further formed on this oxide layer as an etching mask, and the second opening pattern is defined here by performing a money engraving process. On the oxide layer. Among them, the etching formula for etching the oxide layer can be selected from CC12F2, CHF3 / CF4 'chf3 / 〇2, CH3CHF2' CFJ〇2 ο Then, referring to the figure of the younger brother, form a barrier layer 〖1 4 on the sacrificial layer 110. The anti-reflection layer 104, the first dielectric layer 100 and the surface of the semiconductor substrate 100. In addition, in addition to the barrier layer 114, in addition to improving the properties of the contact layer formed between the conductive layer formed later and the first dielectric layer 102, the anti-reflection layer 104, and the semiconductor substrate 100, In addition to increasing the adhesion capacity therebetween, it can also prevent the subsequent formation of the conductive layer material from diffusing into the first dielectric layer 102. In general, the barrier layer 114 can be formed using physical vapor deposition (PVD), and the material of the barrier layer 114 can be selected from giant, nitride giant, or any combination thereof. As for the formed barrier layer, the thickness is about 250 to 350 angstroms, and preferably about 300 angstroms. In a preferred embodiment, the nitride layer ′ used as the barrier layer 4 can be formed using a nitridation process. First, a sputtering process is performed to deposit a giant layer on the surfaces of the sacrificial layer 110, the anti-reflection layer 104, the first dielectric layer 102, and the semiconductor substrate 100. Then in a N2 or NH3 environment, the required nitrided layer is formed through high temperature treatment. In addition, a reactive sputtering process can also be used to form a nitrided giant layer. By using this paper size, the Chinese National Standard (CNS) A4 specification (210 X 297 male «) is used. ----------- -Installation --I ----- Order ---- I- -^-(Please read the precautions on the back before filling out this page) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by the Shellfish Consumer Cooperative, printed by the Ministry of Economic Affairs ’Intellectual Property Employees’ Consumer Cooperative, printed 432622 Giant metal, and argon and nitrogen are introduced, so that the tantalum atoms that are splashed by bombardment can react with the nitrogen atoms formed through the dissociation reaction and form nitrided deposits. Next, as shown in the tenth figure, a conductive layer 116 is formed on the barrier layer 114 and filled in the first opening 1 () 8 and the second opening 12. The material of the conductive layer 116 can be doped polysilicon, in-situ doped polysilicon, copper, aluminum, titanium, tungsten, platinum, or any combination thereof. In a preferred embodiment, the conductive layer 116 is made of copper and the step of forming a copper layer on the barrier layer 114 includes using a physical oxygen phase deposition (pVD) method or a chemical vapor deposition method ( CVD), depositing a thin copper layer on the surface of the barrier layer 14 as a Cu seeding layer. Then, an electroplating process is used to deposit a desired copper layer on the barrier layer surface 114, and fill the first opening 108 and the second opening 112, so as to form as shown in the tenth figure. The conductive layer 116. Subsequently, "please refer to the eleventh figure" to remove a part of the conductive layer 1 and a part of the barrier layer i 14 above the sacrificial layer n0. In a preferred embodiment, a chemical mechanical polishing method (CMP) may be used to perform a polishing process on the semiconductor substrate OO ′ to remove the above-mentioned part of the conductive layer 116 and the part of the barrier layer U4. Next, the residual sacrificial layer 110 is removed to expose the surface above the anti-reflection layer 104. When the photoresist layer is used as the sacrificial layer Uo, the entire 13 scales can be applied to the TS National Standard (CNS) A4 specification (210 x 297 mm) {Please read the precautions on the back before filling this page) Equipment--1 i I 丨 order ------ 1- 'today 432622
五、發明說明（） =性之有機溶劑中，行濕_ 接著，清參照第十二圖，形成第二介電層U8於抗月 射層二4與阻障層114之表面上。其中，在一較佳實施分 中’此第二介電層118與第—介電層1〇2相同，是由低介# 値（Kg 3)材料所構成。並且，此第：介電層較佳的厚度^ 5〇〇〇至1 0000埃。如此，將可得到如第十二圖中所示之肩 重鑲嵌結構121。其中，此雙重鑲嵌結構121包括了位於澤 一介電層102中之導電插塞12〇，與連接於導電插塞 且位於第二介電層118中之溝渠内連線結 ---------- ^------ (請先閱讀背面之注恚事項再填寫本頁) 經濟部智M財產局員工消費合作社印製 本發明具有極多的優點。其中，在定義第一開 108於第一介電層1〇2中之後，此第一開口〗〇8隨即 層114所覆蓋。如此一來，可有效避免在先前技術 於第一介電層側壁，遭受數次的乾蝕刻與濕蝕刻程 導致產生回侵蝕效果，並造成第一開口圖案發生改 而使整個製程的維度受到影響。並且，根據本發明之 第二介電層118是在雙重鑲嵌結構121形成後，才 半導體底材上。是以，就第二介電層ιι8而言，將 會發生先前技術中之回侵姓現象。如此一來，將可 昇所製作雙重鑲嵌結構其維度之精確性。更者，由 開口與第二開口之側壁，不會由於蝕刻程序而產 口圖案 爲阻障 中，由 序，而 變，從 方法， 沉積於 完全不 大幅提 於第一 生回侵 訂 14 本紙張尺度適用中國固家標準（CNS>A4規格（210 X 297公釐） A7 s?4 326 2 2 五、發明說明（） 蝕，是以將可免除由於介電層中空隙曝露，所導致之應力 不均問題，更可由此而避免介電層發生先前技術中之裂缝 等缺陷。 本發明雖以一較佳實例闡明如上，然其並非用以限定 本發明精神與發明實體，僅止於此一實施例爾。是以，在不 脱離本發明之精神與範圍内所作之修改，均應包含在下述之 申請專利範圍内。 I n m n _· t— ! It i^i I n it-^eJ· ^^1 .^1 .^1 I 樣 n (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公t )5. Description of the invention () = Wet in organic solvents_ Next, referring to the twelfth figure, a second dielectric layer U8 is formed on the surface of the anti-radiation layer 24 and the barrier layer 114. Among them, in a preferred embodiment, the second dielectric layer 118 is the same as the first dielectric layer 102 and is made of a low dielectric # 値 (Kg 3) material. And, the preferred thickness of the dielectric layer is from 5,000 to 10,000 angstroms. In this way, a shoulder-mounting structure 121 as shown in Fig. 12 can be obtained. Wherein, the dual damascene structure 121 includes a conductive plug 12 located in the first dielectric layer 102 and a junction connected to the conductive plug and a trench located in the second dielectric layer 118 ----- ----- ^ ------ (Please read the notes on the back before filling out this page) The printing of this invention by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs has many advantages. Among them, after the first opening 108 is defined in the first dielectric layer 102, the first opening 108 is then covered by the layer 114. In this way, it is possible to effectively avoid the back etching effect caused by the dry etching and wet etching processes on the sidewall of the first dielectric layer several times in the prior art, and the first opening pattern is changed to affect the dimension of the entire process. . Also, the second dielectric layer 118 according to the present invention is formed on the semiconductor substrate after the dual damascene structure 121 is formed. Therefore, as far as the second dielectric layer ι8 is concerned, the phenomenon of hacking the name in the prior art will occur. In this way, the accuracy of the dimensions of the dual mosaic structure produced can be enhanced. What's more, the side walls of the opening and the second opening will not be blocked by the etching process due to the etching process. The order will change, and the method will be deposited in a way that does not significantly improve the 14th edition. Paper size applies Chinese solid standard (CNS > A4 specification (210 X 297 mm) A7 s? 4 326 2 2 V. Description of the invention ()) Etching is to avoid the exposure caused by the voids in the dielectric layer. The problem of uneven stress can also prevent defects such as cracks in the prior art from occurring in the dielectric layer. Although the present invention is illustrated above with a preferred example, it is not intended to limit the spirit and the inventive entity of the present invention, and only stops there An embodiment: Therefore, all modifications made without departing from the spirit and scope of the present invention should be included in the scope of the following patent applications. I nmn _ · t—! It i ^ i I n it- ^ eJ · ^^ 1. ^ 1. ^ 1 I sample n (Please read the precautions on the back before filling out this page) Printed on the paper standard of the China National Standards (CNS) A4 specification (printed on the paper) 210 X 297 t)