TW432589B - Shallow trench isolation processing for reducing junction current leakage - Google Patents

Abstract

The present invention discloses a method for forming shallow trench isolation region which can reduce the junction current leakage at the border between the shallow trench isolation region and adjacent transistor contact metal, and preventing the reduction of carrier density in the source and drain areas of transistors adjacent to the shallow trench. The method includes the following steps: firstly, providing a semiconductor substrate having a surface covered by at least one layer of insulation material, and a plurality of shallow trenches formed on the surface of the semiconductor substrate; next, growing an insulation layer with doped nitride on the inner surface or sidewall of the shallow trench; depositing a gap filling insulation layer covering on the surface of the semiconductor substrate to fill up the shallow trench; then, planarizing the gap filling insulation layer to remove the redundant material of the gap filling insulation layer and leaving the gap filling insulation layer within the shallow trench.

Description

f. 43258 9 V. Description of the invention (1) [Field of the invention] The present invention relates to the manufacture of semiconductor devices, and more particularly to a method for manufacturing a shallow trench isolation region (STI) for integrated circuits. [Explanation of the know-how] The structure and function of the shallow trench isolation region (STI) are well known to those skilled in the art. Shallow trench isolation is usually used to provide extremely high impedance 'between the circuit elements of the integrated circuit to effectively isolate the circuit elements from each other. To form a shallow trench isolation region ', first, a recess or trench 10 is selectively formed on the surface of the semiconductor substrate 5, as shown in FIG. An insulating substance 'such as silicon dioxide (S i 02) 1 5 is filled in the trench. Traditionally, the above-mentioned silicon dioxide (Si02) filling layer is formed by chemical vapor deposition (c) of ozone-tetraethoxysilylmethane (〇3-TEOS), or by spin-on-glass (SOG) Formation of silicon dioxide. Then, the silicon dioxide 5 filling layer can be surface-planarized by a chemical / mechanical planarization process (CMp), or by chemically etching the silicon dioxide on the surface of the semiconductor substrate 5. The silicon nitride planarization stop layer (SixNy) 20 and silicon dioxide (si0m1) are removed to form a transistor of the integrated circuit. Impurities, such as boron 2 or arsenic, diffuse into the surface of the semiconductor substrate adjacent to the trench 10 Area of the side wall] This diffusion process will form the source and diode surfaces of the integrated circuit transistor, and then etch with diluted hydrofluoric acid (HF) to form a surface that contacts the metal to the source and engraved the semiconductor substrate. Remove any residues before the drain region

^ 43258 9 V. Description of the invention (2) The remaining oxide is filled and oxidized to form a titanium cap. After the thickness of the transistor CoSi layer (CoS layer thickness), it is scattered into the shallow trench electrode and the non-electrode region, and junction leakage occurs, and In the later stage of the Wilson trench structure, the stone layer, a multiple layer, and the multiple crystals are broken to form a trench layer (the liner is located on the trench fill structure. Chemical treatment. ° This diluted hydrofluoric acid will be further reduced The thickness of the middle layer of the shallow trench. The titanium, silicon, or titanium nitride alloy is deposited on the source and drain regions over the surface of the semiconductor substrate to form titanium silicide (T 丨 s L) or ix) ° The aforementioned hydrogen due to dilution Fluoric acid will decrease the filling oxygen at the moment. At this time, the junction leakage current will increase β. In the P-type source and drain regions, the boron implanted therein will expand the filled oxide layer in the trench. This will cause a decrease in the carrier concentration in the P-type diffusion source and further increase the probability of transistor transistor. Subsequent processes on the semiconductor substrate to complete the metallization process, that is, the required integrated circuit is formed. Et al. U.S. Patent No. 5, 1 1 2, 772 discloses a manufacturing ^ A layer of silicon dioxide crystal is formed on the surface of the semiconductor substrate; and a silicon nitride layer is passed through the above silicon dioxide groove. The chemical conversion layer 'and enters a part of the semiconductor substrate), then 'A dielectric liner y is first formed on the sidewall of the trench, and then a trench filler is filled. The liner layer is removed, then the upper part is formed, and a uniform layer is formed to cover the trench. The uniform layer and part of the trench filling material are oxygenated.

Okazawa ’s US-specific integrated circuit, such as β No. 5 ’20179, discloses a method of manufacturing a semiconducting method that first forms the first two-program-only memory (). The electrode insulation layer is on a surface of a semiconductor substrate.

3258 9 V. Description of the invention (3) Next, a first polycrystalline silicon layer, a second gate insulating layer, and a second polycrystalline silicon layer are sequentially formed on the surface of the semiconductor substrate. An insulating trench is formed by selectively removing a portion of the second polycrystalline silicon layer, the second gate insulating layer, the first polycrystalline silicon layer, and the first gate insulating layer. A butterfly scale glass (BPSG) layer is formed over the entire trench surface. The BPSG layer is selectively removed so that only the portion within the trench is left. In the known technique proposed by Okazawa, the boron and phosphorus contained in the BpsG layer will escape due to the heat treatment that forms the gate insulating layer. In this way, part of the escaped boron or phosphorus will enter the gate insulation layer, which reduces the characteristics and reliability of the PROMs's cell bb body. However, since the BPSG layer is grown after the first and second gate insulating layers are formed by the inventive method, the boron and phosphorus contained in the BPSG layer will not diffuse into the above-mentioned gate insulating layer. U.S. Patent No. 5, 3 1 6, 965 by Philipossian et al. Discloses an improved process' for planarizing an insulating barrier when manufacturing integrated circuits on a semiconductor substrate. This process involves reducing the erosion rate of the field oxide layer to make it equivalent to the sacrificial oxide layer. The field oxide layer is first implanted with nitrogen ions, and then is thermally annealed to harden and densify the field oxide layer. In the subsequent process A, a sacrificial oxide layer is formed on the upper surface of the semiconductor by a thermal oxidation process. When hydrofluoric acid (HF) is used for etching, the etching rate of the hardened field oxide layer is significantly lower than that of the untreated field oxide layer. In this way, the etching rate of the exposed hardened field oxide layer is about the same as that of the sacrificial oxygen layer. In the proposed example, the etching rate of the untreated TE0S field oxide layer = 1 is about 6 9 Angstroms "" in the HF solution, while the 2TE0S field oxide layer is hardened by this process. It is 5.9 Angstroms / sec. Flattening the field oxide layer of this hardening treatment can avoid ^ 43258 9__ V. Description of the invention (4) Insulation of insulation barriers. U.S. Patent No. 5,447,8 84 discloses a process for forming a trench isolation region, wherein the trench is etched by an active ion etching process and lined with a nitride liner layer having a thickness of less than 5 nm . The invention is characterized by performing a pyrolytic oxide annealing process (wet oxidation reaction) at a temperature of about 80 ° C. Although this annealing procedure densifies the oxide liner layer like a conventional procedure, it is performed at a temperature much lower than the conventional argon annealing procedure.

U.S. Patent No. 5,49 2,858 to Bose et al. Discloses a method for flattening the round surface of Shi Xijing using shallow trench isolation technology in integrated circuit manufacturing processes. Before the trench and active area platforms are covered with a silicon oxide layer, a silicon nitride protective liner layer is first covered on the etched trench. Next, a steam annealing process is performed to densify the silicon oxide layer, and then the surface of the wafer is etched and ground down to the surface of the active area platform to form a substantially flat surface. [Summary of the Invention] In view of this, an object of the present invention is to provide a method for forming a shallow trench isolation region, which reduces a junction leakage current on a metal boundary between the shallow trench isolation region and an adjacent transistor. Another object of the present invention is to provide a method for forming a shallow trench isolation region, which avoids a reduction in the concentration of the source and drain regions of a transistor adjacent to the shallow trench. In order to achieve the above and other objectives, the present invention proposes a method for forming a shallow trench isolation region structure of integrated circuits on a semiconductor substrate. First, mention

^ 4 325 8 9 V. Description of the invention (5) A semiconductor substrate is provided which has a surface covered with at least one layer of an insulating substance and has a plurality of shallow trenches formed in a surface of the semiconductor substrate. Then, on the inner surface or sidewall of the shallow trench, a nitrogen-doped insulating layer D is grown to deposit a gap-fill insulating layer on the surface of the semiconductor substrate to 'fill the shallow trench' and then planarize the gap fill. The insulating layer removes excess material from the gap-filling insulating layer from the surface of the semiconductor substrate and leaves the gap-filling insulating layer in the shallow trench. The step of growing the above-mentioned nitrogen-doped insulating layer is performed by sequentially using an oxygen-rich gas such as water (H2O) and oxygen (O2), and a nitrogen-containing compound such as nitrogen (N2), Ammonia (m3), nitrous oxide (N2O), IUNO), and other nitrogen-containing compounds are formed by treating the inner surfaces of these shallow trenches. According to a preferred embodiment of the present invention, the inner surfaces of the shallow trenches are treated with an oxygen-rich gas under the conditions of a temperature of "❶ 艺 to" ㈧C and a pressure of 600 to 760 Torr, For about 60 to 120 minutes, and treating the inner surfaces of these shallow trenches with a nitrogen-containing compound is performed at a temperature of 900 C to ΐοοοχ: and a pressure of 600 to 760 Torr for about 30 to 90 minute. The aforementioned step of growing a nitrogen-doped insulating layer on the inner surfaces of the shallow trenches may also be performed by exposing the inner surfaces of the shallow trenches to a mixed gas rich in nitrogen and oxygen. A thermally grown silicon nitride layer covers the inner surfaces of the shallow trenches. The above is to treat these with a mixed gas rich in nitrogen and oxygen.

Page 8? 4 3258 9 V. Description of the invention (6) The inner surface of the shallow groove is at a temperature of 900-1000 ° C and a pressure of 600-760 Torr. 120 to 180 minutes. Among them, the nitrogen-containing component includes nitrogen (N2), ammonia (Nh3), nitrous oxide (n20), nitric oxide (NO), and other nitrogen-containing compounds, and the oxygen-containing component includes water vapor (H20) and Oxygen (02). The thickness of the nitrogen-doped insulating layer ranges from 10 nm to 3011111. The above-mentioned gap-filling insulating layer is a silicon oxide layer formed by a CVD process or a spin-on-glass (SOG) silicon dioxide layer. The planarization process is performed using a chemical / mechanical planarization polishing process. [Brief description of the drawings] In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below, and in conjunction with the attached drawings, the detailed description is as follows: Sections 1A to 1 Figure F is a cross-sectional view for illustrating the manufacturing process of forming the shallow trench isolation region of the present invention; and Figure 2 is a flowchart of the method of forming the shallow trench isolation region of the present invention. [Detailed description of the invention] and FIG. 2 discuss the steps of forming the present invention and performing step 100 of FIG. 2 to provide a background 5. The semiconductor substrate 5 has a first trench-isolated method. First, the semiconductor-based insulating layer 15 'shown in FIG. 1A is usually a silicon oxide (Si 0χ) layer and a second insulating layer 20, for example. Conventionally, the second insulating layer 20 is a silicon nitride (s ijy) layer, which will be used as a termination layer for the planarization process in the subsequent steps of the method. Next, the above-mentioned first insulating layer 15 and the second insulating layer 20 are selectively etched, and

mm Page 9 ί 432589 V. Description of the invention (7) Semiconductor substrate 5 to form a trench 10. Next, step 105 is performed to grow on the inner surface or the sidewall of the trench 10-an insulating pad layer 25 rich in nitrogen, as shown in Fig. 1B. Wherein, the above-mentioned insulating liner layer 25 is obtained by exposing the inner surface or sidewall of the trench 10 to a nitrogen gas (N2) or nitrogen compounds (for example, ammonia gas (NH3), nitrous oxide (N20) ), And nitric oxide (NO), etc., and a compound rich in oxygen, such as formed in a mixed gas of water gas (H20) or oxygen (02). The pressure for performing this step is between 600 and 760 Torr 'and the temperature is between 900 ° C and 1,000 ° C. The exposure time to the above mixed gas ranges from about 120 minutes to about 180 minutes, or until the thickness of the liner layer is greater than 8 nm. Alternatively, you can first provide only oxygen-rich compounds, such as water (H2O) or oxygen (02), at a temperature between 900 X: to 1000 ° C and a pressure between 600 and 760 Torr. Perform the reaction. The time that the trench 10 is exposed to the above-mentioned water vapor (ίο) or oxygen (02) is between about 60 minutes and about 120 minutes', and the steps described above are basically equivalent to the conventional thermal oxidation growth process. Next, the nitrogen gas (e.g., nitrogen (N2), ammonia (nh3), nitrous oxide (N2O), and nitrogen monoxide (no)) is used to replace the water gas (h2) of the oxygen-rich compound. ) Or oxygen (〇2) to grow a silicon nitride oxide (SixOyNz) liner. The pressure at which this step is performed is between 600 and mo Torr 'and the temperature is between 901 TC and 100 ° C. The exposure time to the above-mentioned nitride gas ranges from about 30 minutes to about 90 minutes, or until the thickness of the lining layer reaches more than 10 nm or more. Next, step 110 'is performed to deposit on the surface of the semiconductor substrate 5.

Page 10 ¥ 1 ^ 43258 9 ___ V. Description of the invention (8) A gap-filling layer 30, as shown in Figure 1C. The gap-filling layer 30 can be fabricated by methods well known to those skilled in the art, including: using various chemical vapor deposition (CVD) procedures, such as atmospheric pressure chemical vapor deposition (APCVD), sub-normal pressure chemistry Vapor Deposition (SACVD), Low Pressure Chemical Vapor Deposition (LPCVD), or High Density Plasma Chemical Vapor Deposition (HDPCVD) procedures, etc. 'using ozone-tetraethoxysilylmethane (〇3_TEOS) as the raw material Depositors; or those formed by spin-on-glass-breaking (SOG) technology. Therefore, the material of the gap-filling layer 30 may be silicon dioxide (SiO 2) or borophosphorus glass (BPSG). Then 'step 115' is performed at a temperature between 8 00 t and 120 (TC), and a thermal annealing process is performed on this aged filling layer 30 for about 1 to 20 minutes. This high temperature thermal annealing process The gap filling layer 3 can be made denser. After the thermal annealing process in step 115, a planarization process for the semiconductor substrate 5 in step 120 is performed to remove the excess gap filling layer 3 from the surface of the semiconductor substrate. As shown in Fig. 1d. The remaining gap-filling layer 30 fills the trench 10 and is at the same height as the surface of the semiconductor substrate 5. The planarization process of the gap-filling layer 30 in step 12 is performed. Basically, the conventional chemical / mechanical planarization polishing (CMp) procedure or the conventional wet etching technique can be used to perform the method. The method of the present invention continues to step 130 to form an electric current on the surface of the semiconductor substrate 5. The crystal 40 is shown in FIG. E. By diffusing an impurity, such as butterfly (B) ', into the surface of the semiconductor substrate 5 to form the source and non-electrode regions 35 of the transistor 40. As mentioned earlier, However, doped boron in the process

Point 3258 9 V. Description of the invention (9) (B) Easily diffuses into the gap-filling layer 30. However, since the insulating spacer layer 25 of the present invention contains nitrogen element ', it can effectively block the diffusion of boron (B) without entering the gap-filling layer 30. In this way, the source and drain regions 35 adjacent to the sidewall of the trench 10 will not have their carrier concentration reduced to an unacceptable level due to diffusion, which can prevent an increase in leakage current at the junction of the transistor 40. 0. Referring to FIG. 1F, after the transistor 40 is formed, an etching process of step 140 is performed, and the surface of the source and drain regions 35 of the semiconductor substrate 5 is soaked with a diluted hydrofluoric acid (HF) solution. The diluted hydrofluoric acid (HF) solution 'is used here to remove any remaining gap-fill layer 30 from the surface of the source and drain regions 35 on the semiconductor substrate 5. Among them, the insulating pad layer 25 will be used as an etching barrier layer again to prevent the gap-filling layer 30 from becoming thinner to avoid increasing the junction leakage current of the transistor 40. Next, a step 145 is performed to form a contact metallurgy. First, a titanium layer, a cobalt layer, or a cobalt layer is deposited. Layer and an atmospheric layer (both not shown) 'followed by a rapid thermal annealing (RTA) treatment on the above-mentioned contact metal at a temperature between 500t and 80 (c) between about 20 and 40 Seconds, allowing it to react with the silicon layer in contact. Then, the portion of the contact metal that does not react with the silicon layer is selectively etched away, and a second rapid thermal annealing process is performed at a temperature between 650 C and 750 C. Then, a titanium silicide or cobalt silicide layer can be formed on the interface between the contact metal and the source and drain regions 35. After that, the step 15f shown in the second figure is executed to complete the fabrication of the integrated circuit with a general back end processing. due to

Page 12 -Hi4 325Q 9- V. The description of the invention (ίο) is not the focus of the present invention and will not be repeated here. Although the present invention is disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application.

Page 13

Claims (1)

432589 Patent Scope ~ 1. A method for forming a shallow trench isolation region of an integrated circuit on a semiconductor substrate, including the following steps: providing a semiconductor substrate having a surface covered by at least one layer of an insulating substance and having a plurality of Shallow trenches are formed in the surface of the semiconductor substrate; a nitrogen-doped insulating layer is grown on the inner surfaces of the shallow trenches, and a gap-filling insulating layer is deposited on the surface of the semiconductor substrate to Fill the shallow trenches; and planarize the gap-fill insulation layer to remove excess material from the gap-fill insulation layer from the surface of the semiconductor substrate, and leave the gap-fill insulation in the shallow trenches Floor. 2. The method according to item 1 of the scope of the patent application, wherein the step of growing the doped nitrogen insulating layer includes: sequentially treating the inner surfaces of the shallow trenches with an oxygen-rich gas and a nitrogen-containing compound, The nitrogen-containing compound is selected from the group consisting of nitrogen (Ns), ammonia (N3), nitrous oxide (10), nitric oxide (NO), and other nitrogen-containing compounds. 3. The method as described in item 2 of the scope of patent application, which makes the element-rich gas system selected from the group consisting of water gas (1120) and oxygen (02) 4. As the scope of patent application, item 2 According to the method, the inner surfaces of the shallow trenches are treated with an oxygen-rich gas at a temperature of 90 (3 ° C to 1000 ° C, and a pressure of 600 to 760). Under Torr conditions, it takes about 60 to 120 minutes. 5. The method described in item 4 of the scope of patent application, wherein the inner surfaces of the shallow trenches are treated with a nitrogen-containing compound at a temperature between 90 ° 〇t to Page 14 f 歴 43258 9__ VI. Patent Application Scope ---- ---- 1 00 0 ° C and pressure between 600 and 760 Torr ιτ 卜 ’for about 30 to 90 minutes. 6. The method according to item 丨 of the patent application scope, wherein the step of growing the nitrogen-doped insulating layer comprises: exposing the inner surfaces of the shallow trenches to a mixture of a nitrogen-rich element and an oxygen-rich element. In the gas, through thermal growth-a silicon nitride layer covers the inner surfaces of the shallow trenches. μ 7. The method as described in item 6 of the patent claim, wherein the inner surfaces of the shallow trenches are treated with a gas mixture rich in gas and oxygen, at a temperature between 900 ° C and 1000 At a temperature of 600 ° C to 760 Torr, the temperature is about 120 to 180 minutes. The method according to item 6 of the scope of patent application, wherein the nitrogen-rich and oxygen-rich mixed gas includes: a nitrogen-containing component selected from the group consisting of nitrogen (N2), ammonia (NH3), and A group of nitrogen (n2〇), nitric oxide (NO), and other nitrogen-containing compounds; and an oxygen-containing component selected from the group consisting of water gas (H20) and oxygen (〇2) . 9. The method according to item 1 of the scope of the patent application, wherein the gap-filling insulating layer is a silicon oxide formed by a CVD process, or a spin-on-glass (SOG) silicon dioxide layer. 10. The method according to item 1 of the scope of the patent application, wherein the planarization treatment is performed using a chemical / mechanical planarization polishing treatment. Π. The method according to item 1 of the scope of patent application, wherein the planarization treatment is performed by etching the gap-fill insulating layer. 1 2. The method as described in item 丨 of the patent application, wherein the thickness of the nitrogen-doped insulating layer is between 1010] 1] to 31011). Page 15-L · κ 8 3 ----- Six 'Patent Application Range 13 ·-A shallow trench isolation region structure formed on the surface of a semiconductor substrate' includes: a plurality of shallow trenches formed in the In the surface of the semiconductor substrate; an insulating liner layer doped with nitrogen is grown on the inner surfaces of the shallow trenches; and a gap-filling insulating material is filled in addition to filling the shallow trenches with the surface of the semiconductor substrate Cut flat. 14. The shallow trench isolation region structure described in item 13 of the scope of the patent application, wherein the step of growing the nitrogen-doped insulating layer includes: sequentially treating the shallow trenches with an oxygen-rich gas and a nitrogen-containing compound. The inner surface of the tank, and the nitrogen-containing compound is selected from the group consisting of nitrogen (N2), ammonia (NΗ3), nitrous oxide (N20), nitric oxide (NO), and other nitrogen-containing compounds . 15. The shallow trench isolation area structure described in item 14 of the scope of the patent application, wherein the gas-rich gas system is selected from the group consisting of water gas (H20) and oxygen (02). For example, the structure of the shallow trench isolation area selected in the scope of application for patent No. 14 wherein the inner surfaces of the shallow trenches are treated with an oxygen-rich gas at a temperature between 90 ° C and 100 ° C, the pressure is between 60 to 76 () Torr, the implementation of about 60 to 120 minutes. 17. The shallow trench isolation region structure described in item 16 of the scope of the patent application, wherein the inner surfaces of the shallow trenches treated with a nitrogen-containing compound are at a temperature between 900 ° C and 100 QC, pressure Under the conditions of 600 to 760 Torr, it is performed for about 30 to 90 minutes. 18. The shallow trench isolation area structure as described in the patent application No. 丨 4 Page 16 P43258 9 _____ VI. The scope of the patent application is to 'the step of growing the nitrogen-doped insulating layer includes: exposing the inner surfaces of the shallow trenches to a mixed gas rich in nitrogen and milk. Zhong 'used this to grow a gasification dream layer over the inner surfaces of these shallow trenches. 19. The shallow trench isolation area structure described in item 18 of the scope of the patent application, wherein the inner surfaces of the shallow trenches are treated with a mixed gas rich in nitrogen and oxygen, at a temperature between 900 ° C to 1 000 ° C, pressure of 600 to 760 Torr, for about 120 to 180 minutes. 20_ The shallow trench isolation zone structure described in item 18 of the scope of the patent application, wherein the nitrogen-rich and oxygen-rich mixed gas includes: a nitrogen-containing component selected from nitrogen (D, ammonia gas) (Nh3), nitrous oxide (n2 0), nitric oxide (NO), and other nitrogen-containing compounds; and an oxygen-containing component selected from the group consisting of water vapor (1 {2〇) and oxygen (〇2). 21. The shallow trench isolation region structure described in item 13 of the scope of the patent application, wherein the thickness of the nitrogen-doped insulating layer is between 1011111 and 3011111. 22 The structure of the shallow trench isolation region described in item 13 of the patent application scope, wherein the gap-fill insulating layer is a silicon oxide 'or a spin-on-glass (S0G) silicon dioxide layer formed by a CVD process.