TW430895B - Method of manufacturing semiconductor integrated circuits or electronic packages for avoiding dishing in wide soft metal wires - Google Patents

Method of manufacturing semiconductor integrated circuits or electronic packages for avoiding dishing in wide soft metal wires

Info

Publication number
TW430895B
TW430895B TW88102272A TW88102272A TW430895B TW 430895 B TW430895 B TW 430895B TW 88102272 A TW88102272 A TW 88102272A TW 88102272 A TW88102272 A TW 88102272A TW 430895 B TW430895 B TW 430895B
Authority
TW
Taiwan
Prior art keywords
manufacturing semiconductor
electronic packages
integrated circuits
semiconductor integrated
metal wires
Prior art date
Application number
TW88102272A
Other languages
Chinese (zh)
Inventor
George English
Joachim Keinert
Oliver Rettig
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of TW430895B publication Critical patent/TW430895B/en

Links

Landscapes

  • Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

A method of manufacturing semiconductor circuits or electronic packages is provided. The step of splitting up wide metal areas into metal stripes is included into the physical design step of such devices. This method does not increase the data complexity significantly and guarantees correctness of the design. Furthermore, the method allows to solve the dishing problem that is inherent to copper wiring technologies.
TW88102272A 1998-08-21 1999-02-12 Method of manufacturing semiconductor integrated circuits or electronic packages for avoiding dishing in wide soft metal wires TW430895B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP98115777 1998-08-21

Publications (1)

Publication Number Publication Date
TW430895B true TW430895B (en) 2001-04-21

Family

ID=8232495

Family Applications (1)

Application Number Title Priority Date Filing Date
TW88102272A TW430895B (en) 1998-08-21 1999-02-12 Method of manufacturing semiconductor integrated circuits or electronic packages for avoiding dishing in wide soft metal wires

Country Status (3)

Country Link
JP (1) JP3782904B2 (en)
KR (1) KR20000016933A (en)
TW (1) TW430895B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5185560B2 (en) 2006-05-23 2013-04-17 ルネサスエレクトロニクス株式会社 Semiconductor device design method
JP5313474B2 (en) * 2007-09-28 2013-10-09 スパンション エルエルシー Semiconductor device and manufacturing method thereof
US10366919B2 (en) * 2017-09-20 2019-07-30 Globalfoundries Inc. Fully aligned via in ground rule region

Also Published As

Publication number Publication date
KR20000016933A (en) 2000-03-25
JP3782904B2 (en) 2006-06-07
JP2000068277A (en) 2000-03-03

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Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees