TW429705B - Shared memory allocation method to improve the accessing efficiency - Google Patents

Shared memory allocation method to improve the accessing efficiency

Info

Publication number
TW429705B
TW429705B TW88107911A TW88107911A TW429705B TW 429705 B TW429705 B TW 429705B TW 88107911 A TW88107911 A TW 88107911A TW 88107911 A TW88107911 A TW 88107911A TW 429705 B TW429705 B TW 429705B
Authority
TW
Taiwan
Prior art keywords
memory
improve
shared memory
allocation method
memory allocation
Prior art date
Application number
TW88107911A
Other languages
Chinese (zh)
Inventor
Ren-Kai Chen
Jian-Hua Liou
Original Assignee
Via Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Via Tech Inc filed Critical Via Tech Inc
Priority to TW88107911A priority Critical patent/TW429705B/en
Priority to DE1999157862 priority patent/DE19957862A1/en
Application granted granted Critical
Publication of TW429705B publication Critical patent/TW429705B/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/387—Information transfer, e.g. on bus using universal interface adapter for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system

Abstract

There is provided a shared memory allocation method to improve the accessing efficiency, which is suitable to the method for allocating the buffer in the shared memory of a network switch. The method comprises the steps of: providing a memory with multiple memory sets, each having multiple memory pages; next, allocating multiple buffer areas in the memory, each buffer area being divided into multiple blocks; and allocating the blocks of each buffer area in the memory pages, wherein the continuous blocks of each buffer area are allocated in the memory pages of different memory set.
TW88107911A 1999-05-15 1999-05-15 Shared memory allocation method to improve the accessing efficiency TW429705B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW88107911A TW429705B (en) 1999-05-15 1999-05-15 Shared memory allocation method to improve the accessing efficiency
DE1999157862 DE19957862A1 (en) 1999-05-15 1999-12-01 Common allocation of memory to increase memory access efficiency involves allocating buffer blocks different pages so successive blocks are located in page of different memory banks

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW88107911A TW429705B (en) 1999-05-15 1999-05-15 Shared memory allocation method to improve the accessing efficiency

Publications (1)

Publication Number Publication Date
TW429705B true TW429705B (en) 2001-04-11

Family

ID=21640691

Family Applications (1)

Application Number Title Priority Date Filing Date
TW88107911A TW429705B (en) 1999-05-15 1999-05-15 Shared memory allocation method to improve the accessing efficiency

Country Status (2)

Country Link
DE (1) DE19957862A1 (en)
TW (1) TW429705B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9411635B2 (en) 2007-09-18 2016-08-09 Microsoft Technology Licensing, Llc Parallel nested transactions in transactional memory
TWI703840B (en) * 2019-01-16 2020-09-01 瑞昱半導體股份有限公司 Circuit within switch and method for managing memory within switch

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9411635B2 (en) 2007-09-18 2016-08-09 Microsoft Technology Licensing, Llc Parallel nested transactions in transactional memory
TWI703840B (en) * 2019-01-16 2020-09-01 瑞昱半導體股份有限公司 Circuit within switch and method for managing memory within switch

Also Published As

Publication number Publication date
DE19957862A1 (en) 2000-11-16

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Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees